bugzilla-daemon [Sun, 3 May 2020 14:07:06 +0000 (14:07 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sun, 3 May 2020 13:23:01 +0000 (13:23 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sun, 3 May 2020 11:58:32 +0000 (11:58 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Luke Kenneth Casson Leighton [Sun, 3 May 2020 11:02:11 +0000 (12:02 +0100)]
Re: [libre-riscv-dev] experimental code & monorepo
Jacob Lifshay [Sun, 3 May 2020 04:49:15 +0000 (21:49 -0700)]
[libre-riscv-dev] experimental code & monorepo
Luke Kenneth Casson Leighton [Sun, 3 May 2020 00:21:45 +0000 (01:21 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sun, 3 May 2020 00:09:46 +0000 (20:09 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sun, 3 May 2020 00:08:53 +0000 (20:08 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 23:34:52 +0000 (00:34 +0100)]
Re: [libre-riscv-dev] Needed Subset of POWER
Luke Kenneth Casson Leighton [Sat, 2 May 2020 23:24:38 +0000 (00:24 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Yehowshua [Sat, 2 May 2020 22:07:02 +0000 (18:07 -0400)]
[libre-riscv-dev] Needed Subset of POWER
Yehowshua [Sat, 2 May 2020 20:59:03 +0000 (16:59 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 19:30:22 +0000 (20:30 +0100)]
Re: [libre-riscv-dev] GItlab For SOC repo
Yehowshua [Sat, 2 May 2020 18:47:32 +0000 (14:47 -0400)]
Re: [libre-riscv-dev] GItlab For SOC repo
Yehowshua [Sat, 2 May 2020 18:45:20 +0000 (14:45 -0400)]
[libre-riscv-dev] GItlab For SOC repo
bugzilla-daemon [Sat, 2 May 2020 15:02:55 +0000 (15:02 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sat, 2 May 2020 13:15:16 +0000 (13:15 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Sat, 2 May 2020 05:28:25 +0000 (05:28 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Yehowshua [Sat, 2 May 2020 04:42:44 +0000 (00:42 -0400)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
Luke Kenneth Casson Leighton [Sat, 2 May 2020 04:40:39 +0000 (05:40 +0100)]
Re: [libre-riscv-dev] Documenting the SOC tree Repository
bugzilla-daemon [Sat, 2 May 2020 04:00:41 +0000 (04:00 +0000)]
[libre-riscv-dev] [Bug 186] Create decoder for SOC: Power ISA and RISC-V
Yehowshua [Sat, 2 May 2020 03:09:13 +0000 (23:09 -0400)]
[libre-riscv-dev] Documenting the SOC tree Repository
bugzilla-daemon [Sat, 2 May 2020 02:01:39 +0000 (02:01 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 23:39:59 +0000 (23:39 +0000)]
[libre-riscv-dev] [Bug 299] New: improve memory clash detection
bugzilla-daemon [Fri, 1 May 2020 23:21:10 +0000 (23:21 +0000)]
[libre-riscv-dev] [Bug 298] consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
bugzilla-daemon [Fri, 1 May 2020 23:04:36 +0000 (23:04 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 22:00:08 +0000 (22:00 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 21:55:15 +0000 (21:55 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
Hendrik Boom [Fri, 1 May 2020 21:43:22 +0000 (17:43 -0400)]
Re: [libre-riscv-dev] Verilog book
bugzilla-daemon [Fri, 1 May 2020 21:28:24 +0000 (21:28 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 20:51:33 +0000 (20:51 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 20:23:37 +0000 (20:23 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Hendrik Boom [Fri, 1 May 2020 20:08:57 +0000 (16:08 -0400)]
[libre-riscv-dev] Verilog book
bugzilla-daemon [Fri, 1 May 2020 19:17:25 +0000 (19:17 +0000)]
[libre-riscv-dev] [Bug 298] New: consider using sum-addressed decoder in L1 cache (maybe also L1 I cache)
bugzilla-daemon [Fri, 1 May 2020 19:12:35 +0000 (19:12 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Luke Kenneth Casson Leighton [Fri, 1 May 2020 19:09:19 +0000 (20:09 +0100)]
Re: [libre-riscv-dev] sum-addressed decoder
bugzilla-daemon [Fri, 1 May 2020 18:54:22 +0000 (18:54 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 18:33:05 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 18:19:03 +0000 (18:19 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 14:35:42 +0000 (14:35 +0000)]
[libre-riscv-dev] [Bug 297] nmutil "flatten" function already exists
Jacob Lifshay [Fri, 1 May 2020 14:32:10 +0000 (07:32 -0700)]
[libre-riscv-dev] sum-addressed decoder
bugzilla-daemon [Fri, 1 May 2020 13:33:18 +0000 (13:33 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 1 May 2020 13:31:54 +0000 (13:31 +0000)]
[libre-riscv-dev] [Bug 297] New: nmutil "flatten" function already exists
bugzilla-daemon [Fri, 1 May 2020 13:27:55 +0000 (13:27 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Luke Kenneth Casson Leighton [Fri, 1 May 2020 13:22:33 +0000 (14:22 +0100)]
Re: [libre-riscv-dev] sun opensparc t2
Luke Kenneth Casson Leighton [Fri, 1 May 2020 11:24:24 +0000 (12:24 +0100)]
Re: [libre-riscv-dev] load/store execution queue idea
bugzilla-daemon [Fri, 1 May 2020 05:03:14 +0000 (05:03 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 03:02:55 +0000 (03:02 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
Jacob Lifshay [Fri, 1 May 2020 02:53:59 +0000 (19:53 -0700)]
[libre-riscv-dev] load/store execution queue idea
bugzilla-daemon [Fri, 1 May 2020 02:10:10 +0000 (02:10 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 02:10:01 +0000 (02:10 +0000)]
[libre-riscv-dev] [Bug 296] idea: cyclic buffer between FUs and register file
bugzilla-daemon [Fri, 1 May 2020 02:09:45 +0000 (02:09 +0000)]
[libre-riscv-dev] [Bug 296] New: idea: cyclic buffer between FUs and register file
Jacob Lifshay [Thu, 30 Apr 2020 22:50:10 +0000 (15:50 -0700)]
[libre-riscv-dev] sun opensparc t2
bugzilla-daemon [Thu, 30 Apr 2020 22:44:32 +0000 (22:44 +0000)]
[libre-riscv-dev] [Bug 295] pay attention to these insights
bugzilla-daemon [Thu, 30 Apr 2020 21:52:16 +0000 (21:52 +0000)]
[libre-riscv-dev] [Bug 295] New: pay attention to these insights
bugzilla-daemon [Wed, 29 Apr 2020 21:42:57 +0000 (21:42 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 29 Apr 2020 21:39:48 +0000 (21:39 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
Luke Kenneth Casson Leighton [Wed, 29 Apr 2020 15:10:10 +0000 (16:10 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Wed, 29 Apr 2020 11:16:25 +0000 (11:16 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 29 Apr 2020 11:16:25 +0000 (11:16 +0000)]
[libre-riscv-dev] [Bug 257] Implement demo Load/Store queueing algorithm
bugzilla-daemon [Wed, 29 Apr 2020 08:59:42 +0000 (08:59 +0000)]
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning
bugzilla-daemon [Wed, 29 Apr 2020 08:59:42 +0000 (08:59 +0000)]
[libre-riscv-dev] [Bug 171] partitioned comparison operators
bugzilla-daemon [Wed, 29 Apr 2020 08:56:51 +0000 (08:56 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Wed, 29 Apr 2020 08:56:51 +0000 (08:56 +0000)]
[libre-riscv-dev] [Bug 162] Formally Verify the FSGNJ module
bugzilla-daemon [Wed, 29 Apr 2020 08:55:06 +0000 (08:55 +0000)]
[libre-riscv-dev] [Bug 294] New: usage statistics needed for POWER9 architecture
whygee [Tue, 28 Apr 2020 19:37:07 +0000 (21:37 +0200)]
[libre-riscv-dev] HTTaP and Design for Test (was Re: circuitjs)
whygee [Tue, 28 Apr 2020 19:10:35 +0000 (21:10 +0200)]
Re: [libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 16:30:18 +0000 (17:30 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:35:20 +0000 (16:35 +0100)]
Re: [libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:28:43 +0000 (16:28 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Tue, 28 Apr 2020 15:10:57 +0000 (08:10 -0700)]
Re: [libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:03:07 +0000 (16:03 +0100)]
Re: [libre-riscv-dev] circuitjs
bugzilla-daemon [Tue, 28 Apr 2020 14:56:28 +0000 (14:56 +0000)]
[libre-riscv-dev] [Bug 293] evaluate an online circuit-editor (with simulator preferably)
Jacob Lifshay [Tue, 28 Apr 2020 14:53:54 +0000 (07:53 -0700)]
[libre-riscv-dev] circuitjs
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:43:29 +0000 (15:43 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
Jacob Lifshay [Tue, 28 Apr 2020 14:38:15 +0000 (07:38 -0700)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Tue, 28 Apr 2020 14:27:42 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 293] New: evaluate an online circuit-editor (with simulator preferably)
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:26:29 +0000 (15:26 +0100)]
Re: [libre-riscv-dev] memory interface diagram woes
whygee [Tue, 28 Apr 2020 13:33:23 +0000 (15:33 +0200)]
Re: [libre-riscv-dev] memory interface diagram woes
bugzilla-daemon [Mon, 27 Apr 2020 20:44:55 +0000 (20:44 +0000)]
[libre-riscv-dev] [Bug 165] Formally verify the FPCMP (FEQ, FLE, FLT) module
bugzilla-daemon [Mon, 27 Apr 2020 20:29:51 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:45:09 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:45:08 +0000 (20:45 +0000)]
[libre-riscv-dev] [Bug 163] Formally Verify the FPMAX module
bugzilla-daemon [Mon, 27 Apr 2020 20:44:56 +0000 (20:44 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:43:56 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 196] Formal correctness proof needed for the IEEE754 FPU
bugzilla-daemon [Mon, 27 Apr 2020 20:43:23 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 163] Formally Verify the FPMAX module
bugzilla-daemon [Mon, 27 Apr 2020 20:43:11 +0000 (20:43 +0000)]
[libre-riscv-dev] [Bug 165] Formally verify the FPCMP (FEQ, FLE, FLT) module
bugzilla-daemon [Mon, 27 Apr 2020 20:41:57 +0000 (20:41 +0000)]
[libre-riscv-dev] [Bug 162] Formally Verify the FSGNJ module
bugzilla-daemon [Mon, 27 Apr 2020 20:38:34 +0000 (20:38 +0000)]
[libre-riscv-dev] [Bug 211] formal proof of PowerDecoder stage2 needed
bugzilla-daemon [Mon, 27 Apr 2020 20:38:26 +0000 (20:38 +0000)]
[libre-riscv-dev] [Bug 198] Formal correctness proofs are needed for low-level libraries in LibreSOC
bugzilla-daemon [Mon, 27 Apr 2020 20:29:51 +0000 (20:29 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Mon, 27 Apr 2020 20:28:06 +0000 (20:28 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:27:49 +0000 (20:27 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Mon, 27 Apr 2020 20:26:50 +0000 (20:26 +0000)]
[libre-riscv-dev] [Bug 269] auto-conversion / parser of POWER ISA Spec v3.0B
bugzilla-daemon [Mon, 27 Apr 2020 20:25:12 +0000 (20:25 +0000)]
[libre-riscv-dev] [Bug 272] functions needed in POWER simulator which match 3.0B spec
bugzilla-daemon [Mon, 27 Apr 2020 20:23:05 +0000 (20:23 +0000)]
[libre-riscv-dev] [Bug 189] Create partitioned right shift using the existing partitioned left shift
bugzilla-daemon [Mon, 27 Apr 2020 20:22:52 +0000 (20:22 +0000)]
[libre-riscv-dev] [Bug 171] partitioned comparison operators
bugzilla-daemon [Mon, 27 Apr 2020 20:22:40 +0000 (20:22 +0000)]
[libre-riscv-dev] [Bug 172] partitioned signal add/sub/neg
bugzilla-daemon [Mon, 27 Apr 2020 20:18:38 +0000 (20:18 +0000)]
[libre-riscv-dev] [Bug 173] dynamic partitioned "shift"
bugzilla-daemon [Mon, 27 Apr 2020 20:18:21 +0000 (20:18 +0000)]
[libre-riscv-dev] [Bug 132] SIMD-like nmigen signal for partitioning
projects / libre-riscv-dev.git / log