Fix spelling in pmgen/README.md

Improve igloo2 exmaple

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #842 from litghost/merge_upstream

Changes required for VPR place and route in synth_xilinx

Merge pull request #850 from daveshah1/ecp5_warn_conflict

ecp5: Demote conflicting FF init values to a warning

Add missing newline

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #851 from kprasadvnsi/master

Added examples/anlogic/

Merge pull request #852 from ucb-bar/firrtlfixes

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails

Use "write_edif -pvector bra" for Xilinx EDIF files

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".

Added examples/anlogic/

Revert BRAM WRITE_MODE changes.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

ecp5: Demote conflicting FF init values to a warning

Signed-off-by: David Shah <dave@ds0.me>

Improve igloo2 example

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update igloo2 example to Libero v12.0

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #848 from YosysHQ/clifford/fix763

Fix error for wire decl in always block, fixes 763

Merge pull request #849 from YosysHQ/clifford/dynports

Only run derive on blackbox modules when ports have dynamic size

Only run derive on blackbox modules when ports have dynamic size

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix error for wire decl in always block, fixes #763

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix $global_clock handling vs autowire

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #847 from YosysHQ/clifford/fix785

Fix $readmem[hb] for mem2reg memories, fixes #785

Fix $readmem[hb] for mem2reg memories, fixes #785

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #843 from YosysHQ/clifford/mem2regconstidx

Use mem2reg on memories that only have constant-index write ports

Merge pull request #845 from YosysHQ/clifford/travisnomacos

Disable macOS builds in Travis

Disable macOS builds in Travis

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Try again for passes/pmgen/ice40_dsp_pm.h rule

Tested on both in-tree and out-of-tree builds

Revert FF models to include IS_x_INVERTED parameters.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Use singular for disabling of DRAM or BRAM inference.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Minor improvements in README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Use mem2reg on memories that only have constant-index write ports

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix "write_edif -gndvccy"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Modify arguments to match existing style.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Changes required for VPR place and route synth_xilinx.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #841 from mmicko/master

Fix ECP5 cells_sim for iverilog

Fix ECP5 cells_sim for iverilog

Improve "read" error msg

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

Hotfix for "make test"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #837 from YosysHQ/clifford/fix835

Fix multiple issues in wreduce FF handling, fixes #835

Fix multiple issues in wreduce FF handling, fixes #835

Signed-off-by: Clifford Wolf <clifford@clifford.at>

ice40: use 2 bits for READ/WRITE MODE for SB_RAM map

EBLIF output .param will only use necessary 2 bits

Signed-off-by: Elms <elms@freshred.net>

Merge pull request #834 from YosysHQ/clifford/siminit

Add "write_verilog -siminit"

Add "write_verilog -siminit"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Reduce amount of trailing whitespace in code base

Fix pmgen for in-tree builds

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #794 from daveshah1/ecp5improve

ECP5 Improvements

Merge pull request #827 from ucb-bar/firrtlfixes

Fix FIRRTL to Verilog process instance subfield assignment.

Fix pmgen for out-of-tree build

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #833 from YosysHQ/clifford/fix831

Fix smt2 code generation for partially initialized memory words, fixe…

Fix smt2 code generation for partially initialized memowy words, fixes #831

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #832 from YosysHQ/supercover

Add "supercover" pass

Improvements in "supercover" pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "supercover" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>

techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module

Clean up some whitepsace outliers

Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)

ecp5: Compatibility with Migen AsyncResetSynchronizer

Signed-off-by: David Shah <davey1576@gmail.com>

Minor changes ontop of 71bcc4c: Remove hierarchy warning that is redundant to -check

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #812 from ucb-bar/arrayhierarchyfixes

Define basic_cell_type() function and use it to derive the cell type …

Cleanups in ARST handling in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #824 from litghost/fix_reduce_on_ff

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Fix handling of defparam for when default_nettype is none

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Check if Verific was built with DB_PRESERVE_INITIAL_VALUE

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.

Fix WREDUCE on FF not fixing ARST_VALUE parameter.

Adds test case that fails without code change.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #819 from YosysHQ/clifford/optd

Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior

Merge pull request #820 from YosysHQ/clifford/fix810

Fix #810 and fix #814

Merge pull request #740 from daveshah1/improve_dress

Improve ABC netname preservation

Fix Travis

It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Hotfix for 4c82ddf

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #822 from litghost/expand_setundef

Add -params mode to force undef parameters in selected cells.

Add -params mode to force undef parameters in selected cells.

Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>

Merge pull request #818 from YosysHQ/clifford/dffsrfix

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Merge pull request #786 from YosysHQ/pmgen

Pattern Matcher Generator and iCE40 DSP Mapper

Fix typo in passes/pmgen/README.md

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #821 from eddiehung/dff_init

Revert "Add -B option to autotest.sh to append to backend_opts"

Fixes related to handling of autowires and upto-ranges, fixes #814

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Revert "Add -B option to autotest.sh to append to backend_opts"

This reverts commit 281f2aadcab01465f83a3f3a697eec42503e9f8b.

Fix handling of expression width in $past, fixes #810

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix segfault in printing of some internal error messages

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Rename "yosys -U" to "yosys -P" to avoid confusion about "undefine"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix opt_rmdff handling of $_DFFSR_???_ and $_DLATCHSR_???_, fixes #816

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Bugfix in ice40_dsp

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #817 from eddiehung/dff_init

Cleanup #805

Remove simple_defparam tests

Add ice40 test_dsp_map test case generator

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add "synth_ice40 -dsp"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add FF support to wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve iCE40 SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Detect and reject cases that do not map well to iCE40 DSPs (yet)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix normal (non-array) hierarchy -auto-top.
Add simple test.

Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

ecp5: Add DDRDLLA

Signed-off-by: David Shah <davey1576@gmail.com>

ecp5: Add DELAYF/DELAYG blackboxes

Signed-off-by: David Shah <davey1576@gmail.com>

Add first draft of functional SB_MAC16 model

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Instead of INIT param on cells, use initial statement with hier ref as
per @cliffordwolf

Revert "Add INIT parameter to all ff/latch cells"

This reverts commit 742b4e01b498ae2e735d40565f43607d69a015d8.

Merge https://github.com/YosysHQ/yosys into dff_init

Add actual DSP inference to ice40_dsp pass

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of github.com:YosysHQ/yosys into pmgen