gem5.git
8 years agotest: Make the memtest and memcheck tests functional only
Andreas Sandberg [Thu, 22 Sep 2016 09:49:09 +0000 (10:49 +0100)]
test: Make the memtest and memcheck tests functional only

The memtest and memcheck are not designed to test timing. Make them
functional only to make ref diffs less noisy in the future.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agotests: Make remaining switcheroo tests functional only
Andreas Sandberg [Thu, 22 Sep 2016 09:49:08 +0000 (10:49 +0100)]
tests: Make remaining switcheroo tests functional only

The switcheroo tests only really serve to check functional
correctness. Checking for stat differences in them just increases the
size of reference diffs.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoext: update SST test config
Curtis Dunham [Tue, 20 Sep 2016 14:51:24 +0000 (15:51 +0100)]
ext: update SST test config

Align configuration with new SST change [1] requiring units for
memHierarchy's backend.mem_size parameter.

[1] https://github.com/sstsimulator/sst-elements/commit/c901abb4e79644ff18f5222c94f5dae012772e1e

Change-Id: I19fa09bec8aa453dc52d154598a4ebb20ea304d8

8 years agogpu-compute: fix typo in GPUDispatcher
Tony Gutierrez [Fri, 16 Sep 2016 18:47:19 +0000 (14:47 -0400)]
gpu-compute: fix typo in GPUDispatcher

8 years agohsail: Fix disassembly of load instruction with 3 destination operands
Alexandru Dutu [Fri, 16 Sep 2016 16:36:20 +0000 (12:36 -0400)]
hsail: Fix disassembly of load instruction with 3 destination operands

8 years agogpu-compute: Adding context serialization methods to Wavefront
Alexandru Dutu [Fri, 16 Sep 2016 16:32:36 +0000 (12:32 -0400)]
gpu-compute: Adding context serialization methods to Wavefront
This patch adds methods to serialize the context of a particular wavefront
to the simulated system memory. Context serialization is used when a wavefront
is preempeted (i.e. context switch).

8 years agogpu-compute: Refactoring Wavefront::dynWaveId
Alexandru Dutu [Fri, 16 Sep 2016 16:31:46 +0000 (12:31 -0400)]
gpu-compute: Refactoring Wavefront::dynWaveId

8 years agogpu-compute: Adding vector register file debug messages
Alexandru Dutu [Fri, 16 Sep 2016 16:30:05 +0000 (12:30 -0400)]
gpu-compute: Adding vector register file debug messages
This patch introduces DPRINTFs for reading and writing to and from the vector
register file.

8 years agogpu-compute: Changing reconvergenceStack type
Alexandru Dutu [Fri, 16 Sep 2016 16:29:01 +0000 (12:29 -0400)]
gpu-compute: Changing reconvergenceStack type
std::stack has no iterators, therefore the reconvergence stack can't be
iterated without poping elements off. We will be using std::list instead to be
able to iterate for saving and restoring purposes.

8 years agogpu-compute: Adding ioctl for HW context size
Alexandru Dutu [Fri, 16 Sep 2016 16:27:56 +0000 (12:27 -0400)]
gpu-compute: Adding ioctl for HW context size
Adding runtime support for determining the memory required by a SIMD engine
when executing a particular wavefront.

8 years agogpu-compute: Wavefront refactoring
Alexandru Dutu [Fri, 16 Sep 2016 16:26:52 +0000 (12:26 -0400)]
gpu-compute: Wavefront refactoring
Renaming members of the Wavefront class in accordance with the style guide.

8 years agogpu-compute: Remove WFContext
Alexandru Dutu [Fri, 16 Sep 2016 16:26:03 +0000 (12:26 -0400)]
gpu-compute: Remove WFContext
WFContext struct is currently unused and it has been rendered not useful in
saving and restoring the context of a Wavefront. Wavefront class should be
sufficient for that purpose and the runtime can figure out the memory size
it will need to allocate for a Wavefront through an IOCTL.

8 years agotests, arm: Make switcheroo and checkpoint tests functional
Andreas Sandberg [Fri, 16 Sep 2016 08:14:31 +0000 (09:14 +0100)]
tests, arm: Make switcheroo and checkpoint tests functional

Switcheroo and checkpoint tests should generally be considered to be
successful if they run to completion.  Remove all reference output
files from the switcheroo and checkopint tests to make them purely
functional.

Change-Id: I70b47853bd662b7a33716d9e0d2154b16077f9dc
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agotests: Add support for functional only tests
Andreas Sandberg [Fri, 16 Sep 2016 08:04:20 +0000 (09:04 +0100)]
tests: Add support for functional only tests

Modify the ClassicTest class to only emit a stat verification test
unit if there is a reference stat file. This makes it possible to
design tests that don't care about stat changes.

To generate purely functional tests, we need to be able to create
empty test reference directories. This does not work well with many
revision control systems. As a workaround, add a file named EMPTY to
the list of ignored files in the test harness. This file can be used
as a placeholder in otherwise empty test directories.

Change-Id: I583c8c4e55479f0d48fa99d0b0d1eac9221e6652
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agobase: eliminate ipython warning
Curtis Dunham [Thu, 15 Sep 2016 17:21:38 +0000 (18:21 +0100)]
base: eliminate ipython warning

Change-Id: I3e282baeb969b6bb9534813a2f433d68246c0669
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: Add m5_fail support for aarch64
Ricardo Alves [Thu, 15 Sep 2016 17:21:24 +0000 (18:21 +0100)]
arm: Add m5_fail support for aarch64

Change-Id: Id2acbc09772be310a0eb9e33295afab07e08a4fa
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agocpu: Support exit when any one Trace CPU completes replay
Radhika Jagtap [Thu, 15 Sep 2016 17:01:20 +0000 (18:01 +0100)]
cpu: Support exit when any one Trace CPU completes replay

This change adds a Trace CPU param to exit simulation early,
i.e. when the first (any one) trace execution is complete. With
this change the user gets a choice to configure exit as either
when the last CPU finishes (default) or first CPU finishes
replay. Configuring an early exit enables simulating and
measuring stats strictly when memory-system resources are being
stressed by all Trace CPUs.

Change-Id: I3998045fdcc5cd343e1ca92d18dd7f7ecdba8f1d
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
8 years agocpu: Adjust for trace offset and fix stats
Radhika Jagtap [Thu, 15 Sep 2016 17:01:16 +0000 (18:01 +0100)]
cpu: Adjust for trace offset and fix stats

This change subtracts the time offset present in the trace from
all the event times when nodes and request are sent so that the
replay starts immediately when the simulation starts. This makes
the stats accurate when the time offset in traces is large, for
example when traces are generated in the middle of a workload
execution. It also solves the problem of unnecessary DRAM
refresh events that would keep occuring during the large time
offset before even a single request is replayed into the system.

Change-Id: Ie0898842615def867ffd5c219948386d952af7f7
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
8 years agocpu: Add frequency scaling to the Trace CPU
Radhika Jagtap [Thu, 15 Sep 2016 17:01:09 +0000 (18:01 +0100)]
cpu: Add frequency scaling to the Trace CPU

This change adds a simple feature to scale the frequency of
the Trace CPU.

The compute delays in the input traces provide timing. This
change adds a freqency multiplier parameter to the Trace CPU
set to 1.0 by default. The compute delay is manipulated to
effectively achieve the  frequency at which the nodes become
ready and thus scale the frequency of the Trace CPU.

Change-Id: Iaabbd57806941ad56094fcddbeb38fcee1172431
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
8 years agoarm, config: Fixups for the example big.LITTLE(tm) configuration
Gabor Dozsa [Thu, 15 Sep 2016 17:00:59 +0000 (18:00 +0100)]
arm, config: Fixups for the example big.LITTLE(tm) configuration

This patch refactors the configuration file to use a more
object-oriented design.

Change-Id: I44ac2d063c2b5901f385544fb6ce3f259459cb05
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
8 years agokvm: Support timing accesses for KVM cpu
Michael LeBeane [Wed, 14 Sep 2016 03:20:03 +0000 (23:20 -0400)]
kvm: Support timing accesses for KVM cpu
This patch enables timing accesses for KVM cpu.  A new state,
RunningMMIOPending, is added to indicate that there are outstanding timing
requests generated by KVM in the system.  KVM's tick() is disabled and the
simulation does not enter into KVM until all outstanding timing requests have
completed.  The main motivation for this is to allow KVM CPU to perform MMIO
in Ruby, since Ruby does not support atomic accesses.

8 years agox86: Force strict ordering for memory mapped m5ops
Michael LeBeane [Wed, 14 Sep 2016 03:18:34 +0000 (23:18 -0400)]
x86: Force strict ordering for memory mapped m5ops
Normal MMAPPED_IPR requests are allowed to execute speculatively under the
assumption that they have no side effects.  The special case of m5ops that are
treated like MMAPPED_IPR should not be allowed to execute speculatively, since
they can have side-effects.  Adding the STRICT_ORDER flag to these requests
blocks execution until the associated instruction hits the ROB head.

8 years agosim: Refactor quiesce and remove FS asserts
Michael LeBeane [Wed, 14 Sep 2016 03:17:42 +0000 (23:17 -0400)]
sim: Refactor quiesce and remove FS asserts
The quiesce family of magic ops can be simplified by the inclusion of
quiesceTick() and quiesce() functions on ThreadContext.  This patch also
gets rid of the FS guards, since suspending a CPU is also a valid
operation for SE mode.

8 years agoconfig: move dist-gem5 options to common config
Michael LeBeane [Wed, 14 Sep 2016 03:16:06 +0000 (23:16 -0400)]
config: move dist-gem5 options to common config
dist-gem5 should not be restricted to FullSystem mode.

8 years agodev: Add a DmaCallback class to DmaDevice
Michael LeBeane [Wed, 14 Sep 2016 03:14:24 +0000 (23:14 -0400)]
dev: Add a DmaCallback class to DmaDevice
This patch introduces the DmaCallback helper class, which registers a callback
to fire after a sequence of (potentially non-contiguous) DMA transfers on a
DmaPort completes.

8 years agosim, syscall_emul: Add mmap to EmulatedDriver
Michael LeBeane [Wed, 14 Sep 2016 03:12:46 +0000 (23:12 -0400)]
sim, syscall_emul: Add mmap to EmulatedDriver
Add support for calling mmap on an EmulatedDriver file descriptor.

8 years agogpu-compute: Fix bug with return in cfg
Michael LeBeane [Wed, 14 Sep 2016 03:11:20 +0000 (23:11 -0400)]
gpu-compute: Fix bug with return in cfg
Connecting basic blocks would stop too early in kernels where ret was not the
last instruction.  This patch allows basic blocks after the ret instruction
to be properly connected.

8 years agodev: Exit correctly in dist-gem5
Michael LeBeane [Wed, 14 Sep 2016 03:08:34 +0000 (23:08 -0400)]
dev: Exit correctly in dist-gem5
The receiver thread in dist_iface is allowed to directly exit the simulation.
This can cause exit to be called twice if the main thread simultaneously wants
to exit the simulation.  Therefore, have the receiver thread enqueue a request
to exit on the primary event queue for the main simulation thread to handle.

8 years agomisc: Remove FullSystem check for networking components
Michael LeBeane [Wed, 14 Sep 2016 03:06:32 +0000 (23:06 -0400)]
misc: Remove FullSystem check for networking components
Ethernet devices are currently only hooked up if running in FS mode.  Much of
the Ethernet networking code is generic and can be used to build non-Ethernet
device models.  Some of these device models do not require a complex driver
stack and can be built to use an EmulatedDriver in SE mode. This patch enables
etherent interfaces to properly connect regardless of whether the simulation
is in FS or SE mode.

8 years agobase: Output all AddrRange parameters to config.ini
Matt Poremba [Wed, 14 Sep 2016 03:06:18 +0000 (23:06 -0400)]
base: Output all AddrRange parameters to config.ini

Currently only 'start' and 'end' of AddrRange are printed in config.ini.
This causes address ranges to be overlapping when loading a c++-only
config with interleaved addresses using CxxConfigManger. This patch adds
prints for the interleave and XOR bits to config.ini such that address
ranges are properly setup with cxx config.

8 years agodev, arm: Add a customizable NoMali GPU model
Andreas Sandberg [Tue, 6 Sep 2016 09:22:38 +0000 (10:22 +0100)]
dev, arm: Add a customizable NoMali GPU model

Add a customizable NoMali GPU model and an example Mali T760
configuration. Unlike the normal NoMali model (NoMaliGpu), the
NoMaliCustopmGpu model exposes all the important GPU ID registers to
Python. This makes it possible to implement custom GPU configurations
by without changing the underlying NoMali library.

Change-Id: I4fdba05844c3589893aa1a4c11dc376ec33d4e9e
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agoext: eliminate warnings in SST connector
Curtis Dunham [Fri, 2 Sep 2016 13:58:15 +0000 (14:58 +0100)]
ext: eliminate warnings in SST connector

Now compiles completely clean.

8 years agocommit 15c633eea52f21dae8cb3a195823b3cdec7be491
Curtis Dunham [Wed, 24 Aug 2016 13:20:53 +0000 (14:20 +0100)]
commit 15c633eea52f21dae8cb3a195823b3cdec7be491
Author: Curtis Dunham <Curtis.Dunham@arm.com>
    ext: update SST connector for SST 6.0

8 years agoconfig: KVM acceleration for apu_se.py
David Hashe [Mon, 22 Aug 2016 15:43:44 +0000 (11:43 -0400)]
config: KVM acceleration for apu_se.py

Add support for using KVM to accelerate APU simulations. The intended use
case is to fast-forward through runtime initialization until the first
kernel launch.

8 years agotests: Add example of using KVM acceleration with an app
David Hashe [Mon, 22 Aug 2016 15:41:37 +0000 (11:41 -0400)]
tests: Add example of using KVM acceleration with an app

Add #ifdef's to gpu-hello.cpp demonstrating how to annotate an application
for KVM acceleration.

8 years agocpu, mem, sim: Change how KVM maps memory
David Hashe [Mon, 22 Aug 2016 15:41:05 +0000 (11:41 -0400)]
cpu, mem, sim: Change how KVM maps memory

Only map memories into the KVM guest address space that are
marked as usable by KVM. Create BackingStoreEntry class
containing flags for is_conf_reported, in_addr_map, and
kvm_map.

8 years agodev: Revert 0a316996de76 [dev, sim: Added missing override...]
Andreas Sandberg [Tue, 16 Aug 2016 09:59:15 +0000 (10:59 +0100)]
dev: Revert 0a316996de76 [dev, sim: Added missing override...]

This changeset reverts the changset "dev, sim: Added missing override
keywords to fix CLANG compilation (OSX)" which was incorrectly rebased.

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agocpu: Add missing override in Minor's exec context
Andreas Sandberg [Mon, 15 Aug 2016 11:00:37 +0000 (12:00 +0100)]
cpu: Add missing override in Minor's exec context

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agocpu: Fixed clang errors. Added 'override' keyword for virtual functions.
Reiley Jeapaul [Mon, 15 Aug 2016 11:00:36 +0000 (12:00 +0100)]
cpu: Fixed clang errors. Added 'override' keyword for virtual functions.

Change-Id: Ic37311443ca11ee6d95bceffea599e054e7aa110
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agomem: Print an MSHR without triggering any assertions
Nikos Nikoleris [Mon, 15 Aug 2016 11:00:36 +0000 (12:00 +0100)]
mem: Print an MSHR without triggering any assertions

Previously printing an mshr would trigger an assertion if the MSHR was
not in service or if the targets list was empty. This patch changes
the print function to bypasses the accessor functions for
postInvalidate and postDowngrade and avoid the relevant assertions. It
also checks if the targets list is empty before calling print on it.

Change-Id: Ic18bee6cb088f63976112eba40e89501237cfe62
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agodev, sim: Added missing override keywords to fix CLANG compilation (OSX)
Matteo Andreozzi [Mon, 15 Aug 2016 11:00:35 +0000 (12:00 +0100)]
dev, sim: Added missing override keywords to fix CLANG compilation (OSX)

Change-Id: Ice5fa11e77d06576eaa42149f5fa340a769d8b01
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agocpu, arch: fix the type used for the request flags
Nikos Nikoleris [Mon, 15 Aug 2016 11:00:35 +0000 (12:00 +0100)]
cpu, arch: fix the type used for the request flags

Change-Id: I183b9942929c873c3272ce6d1abd4ebc472c7132
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agotests: remove EIO tests
Steve Reinhardt [Sun, 14 Aug 2016 03:07:28 +0000 (23:07 -0400)]
tests: remove EIO tests

An email sent to gem5-users and gem5-dev asking if anyone was
still using EIO traces got no responses, so it seems like it's
not worth maintaining this any longer.

8 years agostats: Update to match classic memory changes
Andreas Sandberg [Fri, 12 Aug 2016 13:12:59 +0000 (14:12 +0100)]
stats: Update to match classic memory changes

8 years agomem: Add support for secure packets in the snoop filter
Nikos Nikoleris [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Add support for secure packets in the snoop filter

Secure and non-secure data can coexist in the cache and therefore the
snoop filter should treat differently packets with secure and non
secure accesses. This patch uses the lower bits of the line address to
keep track of whether the packet is addressing secure memory or not.

Change-Id: I54a5e614dad566a5083582bede86c86896f2c2c1
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
8 years agomem: Add snoop filter to SystemXBar by default
Andreas Hansson [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Add snoop filter to SystemXBar by default

This patch changes the default behaviour of the SystemXBar, adding a
snoop filter. With the recent updates to the snoop filter allocation
behaviour this change no longer causes problems for the regressions
without caches.

Change-Id: Ibe0cd437b71b2ede9002384126553679acc69cc1
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
8 years agomem: Use FromCache attribute in snoop filter allocation
Andreas Hansson [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Use FromCache attribute in snoop filter allocation

This patch improves the snoop filter allocation decisions by not only
looking at whether a port is snooping or not, but also if the packet
actually came from a cache. The issue with only looking at isSnooping
is that the CPU ports, for example, are snooping, but not actually
caching. Previously we ended up incorrectly allocating entries in
systems without caches (such as the atomic and timing quick
regressions). Eventually these misguided allocations caused the snoop
filter to panic due to an excessive size.

On the request path we now include the fromCache check on the packet
itself, and for responses we check if we actually have a snoop-filter
entry.

Change-Id: Idd2dbc4f00c7e07d331e9a02658aee30d0350d7e
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
8 years agomem: Update mostly exclusive policy even further
Andreas Hansson [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Update mostly exclusive policy even further

This patch takes yet another step in maintaining the clusivity, in
that it allows a mostly-inclusive cache to hold on to blocks even when
responding to a ReadExReq or UpgradeReq. Previously the cache simply
invalidated these blocks, but there is no strict need to do so.

The most important part of this patch is that we simply mark the block
clean when satisfying the upstream request where the cache is allowed
to keep the block. The only tricky part of the patch is in the memory
management of deferred snoops, where we need to distinguish the cases
where only the packet was copied (we expected to respond), and the
cases where we created an entirely new packet and request (we kept it
only to replay later).

The code in satisfyRequest is definitely ready for some refactoring
after this.

Change-Id: I201ddc7b2582eaa46fb8cff0c7ad09e02d64b0fc
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
8 years agomem: Update mostly exclusive cache policy to cover more cases
Andreas Hansson [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Update mostly exclusive cache policy to cover more cases

This patch changes how the mostly exclusive policy is enforced to
ensure that we drop blocks when we should. As part of this change, the
actual invalidation due to the clusivity enforcement is moved outside
the hit handling, to a separate method maintainClusivity. For the
timing mode that means we can deal with all MSHR targets before taking
any action and possibly dropping the block. The method
satisfyCpuSideRequest is also renamed satisfyRequest as part of this
change (since we only ever see requests from the cpu-side port).

Change-Id: If6f3d1e0c3e7be9a67b72a55e4fc2ec4a90fd3d2
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
8 years agomem: Add a FromCache packet attribute
Andreas Hansson [Fri, 12 Aug 2016 13:11:45 +0000 (14:11 +0100)]
mem: Add a FromCache packet attribute

This patch adds a FromCache attribute to the packet, and updates a
number of the existing request commands to reflect that the request
originates from a cache. The attribute simplifies checking if a
requests came from a cache or not, and this is used by both the cache
and snoop filter in follow-on patches.

Change-Id: Ib0a7a080bbe4d6036ddd84b46fd45bc7eb41cd8f
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Tony Gutierrez <anthony.gutierrez@amd.com>
Reviewed-by: Steve Reinhardt <stever@gmail.com>
8 years agoarm, config: Exit with fatal error if using Ruby
Andreas Sandberg [Wed, 10 Aug 2016 15:40:14 +0000 (16:40 +0100)]
arm, config: Exit with fatal error if using Ruby

Ruby on ARM is currently very experimental. Fail with a fatal error
that explains this to make sure users are aware of the limitations (it
doesn't actually work yet!).

Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm, config: Add initial support for Ruby
Andreas Sandberg [Wed, 10 Aug 2016 15:26:34 +0000 (16:26 +0100)]
arm, config: Add initial support for Ruby

Add initial support for creating an ARM system with a Ruby-based
memory system. This support is currently experimental and limited to
the new VExpress_GEM5_V1 platform.

Change-Id: I36baeb68b0d891e34ea46aafe17b5e55217b4bfa
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
8 years agoarm, dev: Add support for listing DMA ports in new platforms
Andreas Sandberg [Wed, 10 Aug 2016 14:27:26 +0000 (15:27 +0100)]
arm, dev: Add support for listing DMA ports in new platforms

When using a Ruby memory system, the Ruby configuration scripts expect
to get a list of DMA ports to create the necessary DMA sequencers. Add
support in the utility functions that wire up devices to append DMA
ports to a list instead of connecting them to the IO bus. These
functions are currently only used by the VExpress_GEM5_V1 platform.

Change-Id: I46059e46b0f69e7be5f267e396811bd3caa3ed63
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
8 years agoruby: Implement support for functional accesses to PIO ranges
Andreas Sandberg [Wed, 10 Aug 2016 14:27:13 +0000 (15:27 +0100)]
ruby: Implement support for functional accesses to PIO ranges

There are cases where we want to put boot ROMs on the PIO bus. Ruby
currently doesn't support functional accesses to such memories since
functional accesses are always assumed to go to physical memory. Add
the required support for routing functional accesses to the PIO bus.

Change-Id: Ia5b0fcbe87b9642bfd6ff98a55f71909d1a804e3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
Reviewed-by: Michael LeBeane <michael.lebeane@amd.com>
8 years agoarm: Don't report the boot ROM as a memory in config tables
Andreas Sandberg [Wed, 10 Aug 2016 13:49:11 +0000 (14:49 +0100)]
arm: Don't report the boot ROM as a memory in config tables

The boot ROM shouldn't be used as a memory by the kernel. Memories
have a flag to indicate this which is set for some platforms. Update
all platforms to consistently set this flag to indicate that the boot
ROM shouldn't be reported as normal memory.

Change-Id: I2bf0273e99d2a668e4e8d59f535c1910c745aa7b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Brad Beckmann <brad.beckmann@amd.com>
--HG--
extra : amend_source : c2cbda38636ea37cbe9ae6977a06b923eab5ba56

8 years agosim: fix issues with pwrite(); don't enable fstatfs
Tony Gutierrez [Fri, 5 Aug 2016 21:15:19 +0000 (17:15 -0400)]
sim: fix issues with pwrite(); don't enable fstatfs

this patch fixes issues with changeset 11593

use the host's pwrite() syscall for pwrite64Func(),
as opposed to pwrite64(), because pwrite64() does
not work well on all distros.

undo the enabling of fstatfs, as we will add this
in a separate pate.

8 years agox86, sim: add some syscalls to X86
Tony Gutierrez [Thu, 4 Aug 2016 16:32:21 +0000 (12:32 -0400)]
x86, sim: add some syscalls to X86

this patch adds an implementation for the pwrite64 syscall and
enables it for x86_64, and enables fstatfs for x86_64.

8 years agostyle: Make the style fixers safe
Jason Lowe-Power [Wed, 3 Aug 2016 16:10:46 +0000 (11:10 -0500)]
style: Make the style fixers safe

Adds a wrapper to the fix functions of the verifiers. This wrapper first
copies the original file to a backup file, then performs the fix. If an
error occurs, the backup file is used to restore the original file.

Also fixed a line-length error in verifiers.py

8 years agoarm: s/ctx_id/ctx/ the GIC
Curtis Dunham [Tue, 2 Aug 2016 12:35:47 +0000 (13:35 +0100)]
arm: s/ctx_id/ctx/ the GIC

Factored out of the larger banked register change.

Change-Id: I947dbdb9c00b4678bea9d4f77b913b7014208690
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: bank GIC registers per CPU
Curtis Dunham [Tue, 2 Aug 2016 12:35:45 +0000 (13:35 +0100)]
arm: bank GIC registers per CPU

Updated according to GICv2 documentation.

Change-Id: I5d926d1abf665eecc43ff0f7d6e561e1ee1c390a
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agostats: update references
Curtis Dunham [Tue, 2 Aug 2016 10:34:32 +0000 (11:34 +0100)]
stats: update references

8 years agoarm: refactor page table walking
Curtis Dunham [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: refactor page table walking

Introduce and use a lookup table.

Using fetchDescriptor() rather than DMA cleanly handles nested paging.

Change-Id: I69ec762f176bd752ba1040890e731826b58d15a6

8 years agoarm: warn not fail on use of missing miscreg CNTHCTL_EL2
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: warn not fail on use of missing miscreg CNTHCTL_EL2

During host bootup, KVM reads/writes to CNTHCTL_EL2. Because this
miscreg has not been implemented, the simulation would end there. This
patch causes the simulation to warn about the read/write instead of fail.

Change-Id: If034bfd0818a9a5e50c5fe86609e945258c96fa3

8 years agoarm: Check TLB stage 2 permissions in AArch64
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Check TLB stage 2 permissions in AArch64

This fixes a bug where stage 2 lookups used the AArch32
permissions rules even if we were executing in AArch64 mode.

Change-Id: Ia40758f0599667ca7ca15268bd3bf051342c24c1

8 years agoarm: correctly assign faulting IPA's to HPFAR_EL2
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: correctly assign faulting IPA's to HPFAR_EL2

This patch corrects IPA reporting if the translation faults in a
stage 2 lookup.

Change-Id: I0b914527f8a9f98a5e980a131cf9d03e5584b4e9

8 years agoarm: Add TLBI instruction for stage 2 IPA's
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Add TLBI instruction for stage 2 IPA's

This patch adds support for stage 2 TLBI instructions
such as TLBI IPAS2E1_Xt.

Change-Id: I0cd5e8055b0c1003e03439aa5183252f50ea0a88

8 years agoarm: Fix stage 2 memory attribute checking in AArch64
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Fix stage 2 memory attribute checking in AArch64

Change-Id: I14c93a5460550051a12129e792a9a9bd522a145c

8 years agoarm: Fix trapping to Hypervisor during MSR/MRS read/write
Dylan Johnson [Tue, 2 Aug 2016 09:38:03 +0000 (10:38 +0100)]
arm: Fix trapping to Hypervisor during MSR/MRS read/write

This patch restricts trapping to hypervisor only if we are in the
correct exception level for the trap to happen.

Change-Id: I0a382b6a572ef835ea36d2702b8a81b633bd3df0

8 years agoarm: Fix secure state checking in various places
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix secure state checking in various places

Faults that could potentially be routed to the hypervisor checked
whether or not they were in a secure state without checking if security
was enabled or not. This caused faults not to be routed correctly. This
patch causes secure state checking to first ask if security is enabled.

Change-Id: I179e9b181b27f552734c9bab2b18d05ac579a119

8 years agoarm: Fix stage 2 determination in table walker
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix stage 2 determination in table walker

We recompute if we are doing a stage 2 walk inside of the table walker
but we have already figured it out in the tlb. Pass the information in
to the walk instead of recomputing it.

Change-Id: I39637ce99309b2ddbc30344d45ac9ebf6a203401

8 years agoarm: Refactor aarch64 table walk logic to remove redundancy
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Refactor aarch64 table walk logic to remove redundancy

The functional case is already handled within the fetchDescriptor()
function. We can thus use that function for both atomic and functional
mode when we start the table walk.

Change-Id: Iacaed28cd9024d259fd37a58150efd00ff94d86e

8 years agoarm: Add check to fault routing for hypervisor/virtualization
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Add check to fault routing for hypervisor/virtualization

This patch adds the option for faults to be routed to the hypervisor
using the pre-existing routeToHyp() functions that are present in each
fault type.

Change-Id: I9735512c094457636b9870456a5be5432288e004

8 years agoarm: Fix EL perceived at TLB for address translation instructions
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Fix EL perceived at TLB for address translation instructions

During address translation instructions (such as AT S1E1R_Xt) the exception
level can be different than the current exception level. This patch fixes
how the TLB determines what EL to use during these instructions.

Change-Id: Ia9ce229404de9e284bc1f7479fd2c580efd55f8f

8 years agoarm: Add AArch64 hypervisor call instruction 'hvc'
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: Add AArch64 hypervisor call instruction 'hvc'

This patch adds the AArch64 instruction hvc which raises an exception
from EL1 into EL2. The host OS uses this instruction to world switch
into the guest.

Change-Id: I930ee43f4f0abd4b35a68eb2a72e44e3ea6570be

8 years agoarm: add stage2 translation support
Dylan Johnson [Tue, 2 Aug 2016 09:38:02 +0000 (10:38 +0100)]
arm: add stage2 translation support

Change-Id: I8f7c09c7ec3a97149ebebf4b21471b244e6cecc1

8 years agoarm: enable EL2 support
Curtis Dunham [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: enable EL2 support

Change-Id: I59fa4fae98c33d9e5c2185382e1411911d27d341

8 years agoarm: invalidate TLB miscreg cache on modification of HSCTLR
Dylan Johnson [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: invalidate TLB miscreg cache on modification of HSCTLR

Change-Id: I5212c91c56435fe008950ed99feacc6921609226

8 years agoarm: change instruction classes to catch hyp traps
Dylan Johnson [Tue, 2 Aug 2016 09:38:01 +0000 (10:38 +0100)]
arm: change instruction classes to catch hyp traps

Change-Id: I122918d0e3dfd01ae1a4ca4f19240a069115c8b7

8 years agotests: Add regex-based ignore rules for ref files
Andreas Sandberg [Fri, 22 Jul 2016 14:24:20 +0000 (15:24 +0100)]
tests: Add regex-based ignore rules for ref files

There are cases where we need to ignore files with specific extensions
(e.g., when Mercurial litters the file system with patch
rejects). Implement this functionality using a helper class
(FileIgnoreList) that supports both regular expressions and basic
string comparisons.

Change-Id: I34549754bd2e10ed230ffb2dc057403349f8fa78
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agostats: update references
Curtis Dunham [Thu, 21 Jul 2016 16:19:18 +0000 (17:19 +0100)]
stats: update references

8 years agoarm, config: Add an example ARM big.LITTLE(tm) configuration script
Gabor Dozsa [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
arm, config: Add an example ARM big.LITTLE(tm) configuration script

An ARM big.LITTLE system consists of two cpu clusters: the big
CPUs are typically complex out-of-order cores and the little
CPUs are simpler in-order ones. The fs_bigLITTLE.py script
can run a full system simulation with various number of big
and little cores and cache hierarchy. The commit also includes
two example device tree files for booting Linux on the
bigLITTLE system.

Change-Id: I6396fb3b2d8f27049ccae49d8666d643b66c088b
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agocpu: Fix Minor SMT WFI/drain interaction issues
Mitch Hayenga [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
cpu: Fix Minor SMT WFI/drain interaction issues

The behavior of WFI is to cause minor to cease evaluating
pipeline logic until an interrupt is observed, however
a user may wish to drain the system while a core is sleeping
due to a WFI.  This patch makes WFI drain.  If an actual
drain occurs during a WFI, the CPU is already drained and will
immediately be ready for swapping, checkpointing, etc.  This
should not negatively impact performance as WFI instructions
are 'stream-changing' (treated like unpredicted branches), so
all remaining instructions are wrong-path and will be squashed
rapidly.

Change-Id: I63833d5acb53d8dde78f9f0c9611de0ece385e45

8 years agocpu: Add SMT support to MinorCPU
Mitch Hayenga [Thu, 21 Jul 2016 16:19:16 +0000 (17:19 +0100)]
cpu: Add SMT support to MinorCPU

This patch adds SMT support to the MinorCPU.  Currently
RoundRobin or Random thread scheduling are supported.

Change-Id: I91faf39ff881af5918cca05051829fc6261f20e3

8 years agoisa: Modify get/check interrupt routines
Mitch Hayenga [Thu, 21 Jul 2016 16:19:15 +0000 (17:19 +0100)]
isa: Modify get/check interrupt routines

Make it so that getInterrupt *always* returns an interrupt if
checkInterrupts() returns true.  This fixes/simplifies handling
of interrupts on the SMT FS CPUs (currently minor).

8 years agobase: Add total() to Vector2D stat
David Guillen Fandos [Thu, 21 Jul 2016 16:19:15 +0000 (17:19 +0100)]
base: Add total() to Vector2D stat

This patch adds a total() function to the Vector2D
stat type. Similar to other stats such as Scalar or
Vector it is useful to be able to read the total for
a given stat.

8 years agomem: Add snoop traffic statistic
David Guillen Fandos [Thu, 21 Jul 2016 16:19:14 +0000 (17:19 +0100)]
mem: Add snoop traffic statistic

8 years agoconfig: Allow SPARC FS image to be specified on the command line
Jakub Jermar [Tue, 19 Jul 2016 14:52:46 +0000 (09:52 -0500)]
config: Allow SPARC FS image to be specified on the command line

At the moment the SPARC FS machine configuration comes with a hardcoded
value for using the Solaris 10 disk image from the OpenSPARC tarball. The
--disk-image option is completely ignored for SPARC. This simple patch
modifies the behavior so that --disk-image option is both taken into
account and also required. This makes it possible to easily change SPARC FS
images without having to modify the configuration files.

8 years agodev, dist: Fixed a scheduling bug in the etherswitch
Mohammad Alian [Tue, 19 Jul 2016 14:48:56 +0000 (09:48 -0500)]
dev, dist: Fixed a scheduling bug in the etherswitch

This patch fixes a bug in etherswitch. When a packet gets inserted
in the output fifo, the txEvent has to always be reschedule,
not only when an event is already scheduled. This can raise
the assertion in the reschedule function.

8 years agobase: Fix inverted check in ELF .text size warning
Andreas Sandberg [Mon, 11 Jul 2016 15:30:35 +0000 (16:30 +0100)]
base: Fix inverted check in ELF .text size warning

8 years agoarm: Don't consult the TLB test iface for functional translations
Andreas Sandberg [Mon, 11 Jul 2016 09:39:56 +0000 (10:39 +0100)]
arm: Don't consult the TLB test iface for functional translations

Don't consult the TLB test interface for PA's returned by functional
translations by the AT instruction. We implement this by chaning the
ISA code to synthesize 0-length functional reads for the TLB lookup.
The TLB then bypasses the final PA check in the tester if the size is
zero.

Change-Id: I2487b7f829cea88c37e229e9fc7a4543aced961b
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agobase: Convert ELF .text size check assertion to a warning
Andreas Sandberg [Mon, 11 Jul 2016 09:39:30 +0000 (10:39 +0100)]
base: Convert ELF .text size check assertion to a warning

The ELF loader currently has an assertion that checks if the size of a
loaded .text secion is non-zero. This is useful in the general case as
an empty text section normally indicates that there is something
strange with the ELF file. However, asserting isn't very useful. This
changeset converts the assert into a warning that tells the user that
something strange is happening.

Change-Id: I313e17847b50a0eca00f6bd00a54c610d626c0f0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agomem: Remove stale argument from a DPRINTF in the cache code
Nikos Nikoleris [Mon, 11 Jul 2016 09:39:22 +0000 (10:39 +0100)]
mem: Remove stale argument from a DPRINTF in the cache code

Change-Id: I70dd11c23b45dfc606ef08233d2e50fcc0817505
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agomisc: merge with sytle checker fix
Jason Lowe-Power [Fri, 1 Jul 2016 15:37:57 +0000 (10:37 -0500)]
misc: merge with sytle checker fix

Oops.

8 years agoruby: Fix double statistic registration in garnet
Matthew Poremba [Fri, 1 Jul 2016 15:31:37 +0000 (10:31 -0500)]
ruby: Fix double statistic registration in garnet

Currently garnet will not run due to double statistic registration of new
stats in ClockedObject. This occurs because a temporary array named 'cls'
is being added as a child to garnet internal and external link SimObjects.
This patch simply renames the temporary array which prevents it from
being added as a child object and avoids the assertion that a statistic
was already registered.

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agoext: Update DRAMPower
Matthias Jung [Fri, 1 Jul 2016 15:31:36 +0000 (10:31 -0500)]
ext: Update DRAMPower

Sync DRAMPower to external tool

This patch syncs the DRAMPower library of gem5 to the external
one on github (https://github.com/ravenrd/DRAMPower) of which
I am a maintainer.

The version used is the commit:
902a00a1797c48a9df97ec88868f20e847680ae6
from 07.  May.  2016.

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agomisc: SystemC Elastic Trace Player Example.
Matthias Jung [Fri, 1 Jul 2016 15:31:33 +0000 (10:31 -0500)]
misc: SystemC Elastic Trace Player Example.

This patch adds an example configuration for elastic trace playing into the
SystemC world, similar to the already existing traffic generator example in
/util/tlm.

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agomisc: fix a compile error due to incompability with SystemC 2.3.1
Christian Menard [Fri, 1 Jul 2016 14:50:18 +0000 (09:50 -0500)]
misc: fix a compile error due to incompability with SystemC 2.3.1

This patch fixes an ambigous call compile error

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agomem: tester for new HMC configuration
Abdul Mutaal Ahmad [Fri, 1 Jul 2016 14:48:43 +0000 (09:48 -0500)]
mem: tester for new HMC configuration

This patch provides the example test script to configure different HMC
architecture and run traffic through traffic generator.

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agomem: different HMC configuration
Abdul Mutaal Ahmad [Fri, 1 Jul 2016 14:45:21 +0000 (09:45 -0500)]
mem: different HMC configuration

In this new hmc configuration we have used the existing components in gem5
mainly [SerialLink] [NoncoherentXbar]& [DRAMCtrl] to define 3 different
architecture for HMC.

Highlights

1- It explores 3 different HMC architectures

2- It creates 4-HMC crossbars and attaches 16 vault controllers with it.
This  will connect vaults to serial links

3- From the previous version, HMCController with round robin funtionality
is being removed and all the serial links are being accessible directly
from user ports

4- Latency incorporated by HMCController (in previous version) is being
added to SerialLink

Committed by Jason Lowe-Power <jason@lowepower.com>

8 years agostyle: Fix incorrect references style verifiers
Andreas Sandberg [Fri, 1 Jul 2016 14:35:52 +0000 (15:35 +0100)]
style: Fix incorrect references style verifiers

The style checker for spacing around control statements (ControlSpace)
and the whitespace checker (Whitespace) didn't refer to some of their
configuration variables correctly. This changeset fixes those issues.

Reported-by: Jason Lowe-Power <power.jg@gmail.com>
--HG--
extra : amend_source : 05d82d27d4c42aacd78b514d3ca35ca5744164bb