Miodrag Milanović [Fri, 4 Mar 2022 09:41:02 +0000 (10:41 +0100)]
Merge pull request #3220 from YosysHQ/claire/simstuff
Add writing of aiw files to "sim" command
github-actions[bot] [Thu, 3 Mar 2022 01:08:21 +0000 (01:08 +0000)]
Bump version
Miodrag Milanovic [Wed, 2 Mar 2022 15:02:13 +0000 (16:02 +0100)]
Add option to ignore X only signals in output
Miodrag Milanovic [Wed, 2 Mar 2022 14:23:07 +0000 (15:23 +0100)]
Write simulation files after simulation is performed
Miodrag Milanovic [Wed, 2 Mar 2022 13:26:15 +0000 (14:26 +0100)]
Update CHANGELOG
Claire Xen [Wed, 2 Mar 2022 12:52:18 +0000 (13:52 +0100)]
Merge pull request #3224 from YosysHQ/micko/refactor
Micko/refactor
Miodrag Milanovic [Wed, 2 Mar 2022 08:39:22 +0000 (09:39 +0100)]
Cleanup
github-actions[bot] [Tue, 1 Mar 2022 01:12:24 +0000 (01:12 +0000)]
Bump version
Miodrag Milanovic [Mon, 28 Feb 2022 17:22:39 +0000 (18:22 +0100)]
Refactor sim output writers
Miodrag Milanovic [Mon, 28 Feb 2022 10:40:06 +0000 (11:40 +0100)]
Quick fix
Claire Xenia Wolf [Mon, 28 Feb 2022 09:50:08 +0000 (10:50 +0100)]
Add writing of aiw files to "sim" command
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Claire Xenia Wolf [Mon, 28 Feb 2022 09:41:44 +0000 (10:41 +0100)]
Hotfix in AIGER witness reader state machine
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Miodrag Milanović [Mon, 28 Feb 2022 07:19:54 +0000 (08:19 +0100)]
Merge pull request #3216 from YosysHQ/claire/simstuff
Co-simulation improvements and fixes
Miodrag Milanovic [Sun, 27 Feb 2022 15:37:40 +0000 (16:37 +0100)]
Support extended aiw format
Miodrag Milanovic [Fri, 25 Feb 2022 15:15:32 +0000 (16:15 +0100)]
Fix for last clock edge data
Claire Xenia Wolf [Fri, 25 Feb 2022 14:50:46 +0000 (15:50 +0100)]
Experimental sim changes
github-actions[bot] [Fri, 25 Feb 2022 01:04:22 +0000 (01:04 +0000)]
Bump version
YRabbit [Thu, 24 Feb 2022 02:33:55 +0000 (12:33 +1000)]
gowin: Remove unnecessary attributes
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
YRabbit [Wed, 23 Feb 2022 06:11:47 +0000 (16:11 +1000)]
gowin: Add support for true differential output
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Claire Xen [Tue, 22 Feb 2022 15:22:06 +0000 (16:22 +0100)]
Merge pull request #3211 from YosysHQ/micko/witness
Add support for AIGER witness files in "sim" command
Claire Xen [Tue, 22 Feb 2022 14:26:22 +0000 (15:26 +0100)]
Merge pull request #3197 from YosysHQ/claire/smtbmcfix
Add a bit of flexibilty re AIG witness trace length to smtbmc.py
github-actions[bot] [Tue, 22 Feb 2022 00:59:35 +0000 (00:59 +0000)]
Bump version
Miodrag Milanović [Mon, 21 Feb 2022 16:57:44 +0000 (17:57 +0100)]
Merge pull request #3203 from YosysHQ/micko/sim_ff
Simulation for various FF types
Marcelina Kościelnicka [Mon, 21 Feb 2022 15:30:42 +0000 (16:30 +0100)]
ecp5: Do not use specify in generate in cells_sim.v.
Miodrag Milanovic [Mon, 21 Feb 2022 15:36:12 +0000 (16:36 +0100)]
Fix handling of ce_over_srst
Claire Xenia Wolf [Fri, 18 Feb 2022 15:27:41 +0000 (16:27 +0100)]
Fix cycle 0 in aiger witness co-simulation
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Miodrag Milanovic [Fri, 18 Feb 2022 14:06:49 +0000 (15:06 +0100)]
Changed error message
Miodrag Milanovic [Fri, 18 Feb 2022 14:04:02 +0000 (15:04 +0100)]
Added AIGER witness file co simulation
Miodrag Milanovic [Fri, 18 Feb 2022 08:17:36 +0000 (09:17 +0100)]
simplify logic of handling flip-flops and latches
Miodrag Milanovic [Thu, 17 Feb 2022 16:18:36 +0000 (17:18 +0100)]
Review cleanup
Miodrag Milanovic [Wed, 16 Feb 2022 12:58:51 +0000 (13:58 +0100)]
test dlatchsr and adlatch
Miodrag Milanovic [Tue, 15 Feb 2022 08:35:53 +0000 (09:35 +0100)]
Added test cases
Miodrag Milanovic [Tue, 15 Feb 2022 08:30:42 +0000 (09:30 +0100)]
Add support for various ff/latch cells simulation
github-actions[bot] [Wed, 16 Feb 2022 01:01:23 +0000 (01:01 +0000)]
Bump version
Miodrag Milanović [Tue, 15 Feb 2022 19:51:54 +0000 (20:51 +0100)]
Merge pull request #3204 from YosysHQ/claire/update-abc
Bump ABC version
Miodrag Milanovic [Tue, 15 Feb 2022 17:44:05 +0000 (18:44 +0100)]
Bump ABC version
github-actions[bot] [Tue, 15 Feb 2022 01:05:31 +0000 (01:05 +0000)]
Bump version
Zachary Snow [Fri, 11 Feb 2022 21:57:31 +0000 (22:57 +0100)]
verilog: support for time scale delay values
Kamil Rakoczy [Mon, 14 Feb 2022 13:34:20 +0000 (14:34 +0100)]
Fix access to whole sub-structs (#3086)
* Add support for accessing whole struct
* Update tests
Signed-off-by: Kamil Rakoczy <krakoczy@antmicro.com>
github-actions[bot] [Sun, 13 Feb 2022 01:02:04 +0000 (01:02 +0000)]
Bump version
Marcelina Kościelnicka [Sat, 12 Feb 2022 10:35:10 +0000 (11:35 +0100)]
gowin: Add remaining block RAM blackboxes.
github-actions[bot] [Sat, 12 Feb 2022 01:01:05 +0000 (01:01 +0000)]
Bump version
Zachary Snow [Tue, 18 Jan 2022 06:18:12 +0000 (23:18 -0700)]
verilog: fix dynamic dynamic range asgn elab
Zachary Snow [Wed, 12 Jan 2022 06:51:08 +0000 (23:51 -0700)]
verilog: fix const func eval with upto variables
Claire Xen [Fri, 11 Feb 2022 16:30:32 +0000 (17:30 +0100)]
Merge pull request #2376 from nmoroze/clk2ff-better-names
clk2fflogic: nice names for autogenerated signals
Claire Xenia Wolf [Fri, 11 Feb 2022 16:24:49 +0000 (17:24 +0100)]
Add a bit of flexibilty re trace length when processing aiger witnesses in smtbmc.py
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Miodrag Milanović [Fri, 11 Feb 2022 15:43:35 +0000 (16:43 +0100)]
Merge pull request #3164 from zachjs/fix-ast-warn
fix dumpAst() compilation warning
Claire Xen [Fri, 11 Feb 2022 15:03:12 +0000 (16:03 +0100)]
Merge branch 'master' into clk2ff-better-names
Claire Xen [Fri, 11 Feb 2022 14:51:24 +0000 (15:51 +0100)]
Merge pull request #2019 from boqwxp/glift
Add `glift` command for creating gate-level information flow tracking models and optimization problems
github-actions[bot] [Thu, 10 Feb 2022 00:58:51 +0000 (00:58 +0000)]
Bump version
Miodrag Milanović [Wed, 9 Feb 2022 11:41:26 +0000 (12:41 +0100)]
Merge pull request #3193 from YosysHQ/micko/verific_f
Add ability to override verilog mode for verific -f command
Miodrag Milanovic [Wed, 9 Feb 2022 08:19:25 +0000 (09:19 +0100)]
Add ability to override verilog mode for verific -f command
Marcelina Kościelnicka [Wed, 9 Feb 2022 05:13:34 +0000 (06:13 +0100)]
gowin: Fix LUT RAM inference, add more models.
Marcelina Kościelnicka [Wed, 9 Feb 2022 04:35:05 +0000 (05:35 +0100)]
ecp5: Fix DPR16X4 sim model.
github-actions[bot] [Tue, 8 Feb 2022 00:59:03 +0000 (00:59 +0000)]
Bump version
Miodrag Milanovic [Mon, 7 Feb 2022 16:10:50 +0000 (17:10 +0100)]
Next dev cycle
Miodrag Milanovic [Mon, 7 Feb 2022 16:08:39 +0000 (17:08 +0100)]
Release version 0.14
Miodrag Milanovic [Mon, 7 Feb 2022 16:07:48 +0000 (17:07 +0100)]
Update CHANGELOG and manual
Miodrag Milanović [Mon, 7 Feb 2022 15:36:43 +0000 (16:36 +0100)]
Merge pull request #3185 from YosysHQ/micko/co_sim
Add co-simulation in sim pass
github-actions[bot] [Mon, 7 Feb 2022 00:56:31 +0000 (00:56 +0000)]
Bump version
Marcelina Kościelnicka [Sun, 6 Feb 2022 11:48:44 +0000 (12:48 +0100)]
nexus: Fix arith_map CO signal.
Fixes #3187.
Miodrag Milanovic [Fri, 4 Feb 2022 10:11:36 +0000 (11:11 +0100)]
Error detection for co-simulation
Miodrag Milanovic [Fri, 4 Feb 2022 09:01:06 +0000 (10:01 +0100)]
bug fix and cleanups
github-actions[bot] [Thu, 3 Feb 2022 00:54:22 +0000 (00:54 +0000)]
Bump version
Miodrag Milanović [Wed, 2 Feb 2022 15:22:53 +0000 (16:22 +0100)]
Merge pull request #3183 from YosysHQ/micko/nto1mux
Use bmux for NTO1MUX
Miodrag Milanovic [Wed, 2 Feb 2022 15:16:08 +0000 (16:16 +0100)]
Use bmux for NTO1MUX
Miodrag Milanovic [Wed, 2 Feb 2022 12:22:44 +0000 (13:22 +0100)]
Add test cases for co-simulation
Miodrag Milanović [Wed, 2 Feb 2022 11:19:17 +0000 (12:19 +0100)]
Merge pull request #3182 from yrabbit/wip-doc2
Correct a typo in the manual
YRabbit [Wed, 2 Feb 2022 11:14:38 +0000 (21:14 +1000)]
Correct a typo in the manual
Signed-off-by: YRabbit <rabbit@yrabbit.cyou>
Miodrag Milanovic [Wed, 2 Feb 2022 10:46:06 +0000 (11:46 +0100)]
Fix Visual Studio build
Miodrag Milanovic [Wed, 2 Feb 2022 09:15:22 +0000 (10:15 +0100)]
respect hide_internal flag
Miodrag Milanovic [Wed, 2 Feb 2022 09:08:23 +0000 (10:08 +0100)]
unify cycles counting and cleanup
Miodrag Milanovic [Wed, 2 Feb 2022 08:37:32 +0000 (09:37 +0100)]
added stimulus mode and param check
Scott Thibault [Wed, 2 Feb 2022 01:30:31 +0000 (20:30 -0500)]
Update comment
Scott Thibault [Tue, 1 Feb 2022 22:55:09 +0000 (17:55 -0500)]
Fix unextend method for signed constants
Miodrag Milanovic [Mon, 31 Jan 2022 16:41:50 +0000 (17:41 +0100)]
error when no signal found
Miodrag Milanović [Mon, 31 Jan 2022 15:11:00 +0000 (16:11 +0100)]
Merge pull request #3176 from higuoxing/fix-ref-manual
Fix the help message of synth_quicklogic command.
Miodrag Milanovic [Mon, 31 Jan 2022 12:45:28 +0000 (13:45 +0100)]
Cleanup
Miodrag Milanovic [Mon, 31 Jan 2022 12:41:02 +0000 (13:41 +0100)]
Compare bits when not all are defined
Miodrag Milanovic [Mon, 31 Jan 2022 11:00:15 +0000 (12:00 +0100)]
Cleanup
Miodrag Milanovic [Mon, 31 Jan 2022 10:41:52 +0000 (11:41 +0100)]
message update
Miodrag Milanovic [Mon, 31 Jan 2022 09:52:47 +0000 (10:52 +0100)]
Display simulation time data
Miodrag Milanovic [Mon, 31 Jan 2022 08:38:25 +0000 (09:38 +0100)]
Use edges when explicit
Miodrag Milanovic [Mon, 31 Jan 2022 08:19:34 +0000 (09:19 +0100)]
Updating initial state and checks
Miodrag Milanovic [Mon, 31 Jan 2022 07:56:29 +0000 (08:56 +0100)]
Fix scope
github-actions[bot] [Mon, 31 Jan 2022 00:54:31 +0000 (00:54 +0000)]
Bump version
Marcelina Kościelnicka [Sun, 30 Jan 2022 19:48:50 +0000 (20:48 +0100)]
verilog backend: Emit a `wire` for ports as well.
Fixes #3177.
Xing GUO [Sun, 30 Jan 2022 14:10:05 +0000 (22:10 +0800)]
Fix the help message of synth_quicklogic.
Marcelina Kościelnicka [Sat, 29 Jan 2022 00:01:21 +0000 (01:01 +0100)]
opt_reduce: Add $bmux and $demux optimization patterns.
github-actions[bot] [Sat, 29 Jan 2022 02:48:50 +0000 (02:48 +0000)]
Bump version
Marcelina Kościelnicka [Mon, 24 Jan 2022 15:02:29 +0000 (16:02 +0100)]
Add $bmux and $demux cells.
Miodrag Milanovic [Fri, 28 Jan 2022 18:41:43 +0000 (19:41 +0100)]
check if stop before start
Miodrag Milanovic [Fri, 28 Jan 2022 14:59:13 +0000 (15:59 +0100)]
set initial state, only flip-flops
Miodrag Milanovic [Fri, 28 Jan 2022 13:20:16 +0000 (14:20 +0100)]
ignore not found private signals
Miodrag Milanovic [Fri, 28 Jan 2022 13:10:39 +0000 (14:10 +0100)]
preserve VCD mangled names
Miodrag Milanovic [Fri, 28 Jan 2022 12:53:27 +0000 (13:53 +0100)]
detect edges even when x
Miodrag Milanovic [Fri, 28 Jan 2022 12:24:38 +0000 (13:24 +0100)]
recursive check
Miodrag Milanovic [Fri, 28 Jan 2022 11:54:16 +0000 (12:54 +0100)]
cleanup
Miodrag Milanovic [Fri, 28 Jan 2022 11:50:41 +0000 (12:50 +0100)]
Do actual compare
Miodrag Milanovic [Fri, 28 Jan 2022 11:15:14 +0000 (12:15 +0100)]
Fix for limit_range_end when not writing vcd
projects / yosys.git / log