Eddie Hung [Mon, 30 Dec 2019 22:35:52 +0000 (14:35 -0800)]
Remove unused
Eddie Hung [Fri, 27 Dec 2019 20:03:19 +0000 (12:03 -0800)]
Do not offset FD* box timings due to -46ps Tsu
Eddie Hung [Mon, 30 Dec 2019 22:33:05 +0000 (14:33 -0800)]
Call "proc" if processes inside whiteboxes
Eddie Hung [Mon, 30 Dec 2019 22:31:42 +0000 (14:31 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Mon, 30 Dec 2019 22:24:58 +0000 (14:24 -0800)]
Add CHANGELOG entry, add abc9_{flop,keep} attr to README.md
Eddie Hung [Mon, 30 Dec 2019 22:19:29 +0000 (14:19 -0800)]
Tidy up abc9_map.v
Eddie Hung [Mon, 30 Dec 2019 22:13:16 +0000 (14:13 -0800)]
Add "synth_xilinx -dff" option, cleanup abc9
Eddie Hung [Mon, 30 Dec 2019 20:26:39 +0000 (12:26 -0800)]
Grammar
Miodrag Milanović [Mon, 30 Dec 2019 19:34:31 +0000 (20:34 +0100)]
Merge pull request #1589 from YosysHQ/iopad_default
Make iopad option default for all xilinx flows
Eddie Hung [Mon, 30 Dec 2019 18:01:02 +0000 (10:01 -0800)]
Merge pull request #1599 from YosysHQ/eddie/retry_1588
Retry #1588 -- "write_xaiger: only instantiate each whitebox cell type once"
Eddie Hung [Mon, 30 Dec 2019 18:00:47 +0000 (10:00 -0800)]
Merge pull request #1600 from YosysHQ/eddie/cleanup_ecp5
Nitpick cleanup for ecp5
Miodrag Milanovic [Sat, 28 Dec 2019 15:43:19 +0000 (16:43 +0100)]
Fix new tests
Miodrag Milanovic [Sat, 28 Dec 2019 15:23:31 +0000 (16:23 +0100)]
Merge remote-tracking branch 'origin/master' into iopad_default
Miodrag Milanovic [Sat, 28 Dec 2019 15:22:24 +0000 (16:22 +0100)]
Make test without iopads
Miodrag Milanovic [Sat, 28 Dec 2019 15:12:45 +0000 (16:12 +0100)]
Revert "Fix xilinx tests, when iopads are default"
This reverts commit
477e43d921d204c6bc6403109fea6506802c948c.
Eddie Hung [Sat, 28 Dec 2019 10:15:11 +0000 (02:15 -0800)]
Update resource count
Eddie Hung [Sat, 28 Dec 2019 00:57:08 +0000 (16:57 -0800)]
Nitpick cleanup for ecp5
Eddie Hung [Sat, 28 Dec 2019 00:44:57 +0000 (16:44 -0800)]
Add #1598 testcase
Eddie Hung [Sat, 28 Dec 2019 00:44:18 +0000 (16:44 -0800)]
write_xaiger: inherit port ordering from original module
Eddie Hung [Sat, 28 Dec 2019 00:05:58 +0000 (16:05 -0800)]
Revert "Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup"
This reverts commit
92654f73ea92ee9e390c8ab50d8cb51c47a7ffa9, reversing
changes made to
3e14ff16676884a1f65cf0eeb0ca9cb1958b8804.
Eddie Hung [Fri, 27 Dec 2019 23:37:26 +0000 (15:37 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Fri, 27 Dec 2019 23:35:19 +0000 (15:35 -0800)]
write_xaiger: simplify c{i,o}_bits
David Shah [Fri, 27 Dec 2019 23:31:51 +0000 (23:31 +0000)]
Merge pull request #1598 from YosysHQ/revert-1588-eddie/xaiger_cleanup
Revert "write_xaiger: only instantiate each whitebox cell type once"
David Shah [Fri, 27 Dec 2019 23:25:20 +0000 (23:25 +0000)]
Revert "write_xaiger: only instantiate each whitebox cell type once"
Eddie Hung [Fri, 27 Dec 2019 23:18:55 +0000 (15:18 -0800)]
Really fix it!
Eddie Hung [Fri, 27 Dec 2019 19:30:18 +0000 (11:30 -0800)]
write_xaiger: fix arrival times for non boxes
Miodrag Milanovic [Wed, 25 Dec 2019 19:38:48 +0000 (20:38 +0100)]
fixed invalid char
Marcin Kościelnicki [Sun, 22 Dec 2019 00:08:56 +0000 (01:08 +0100)]
iopadmap: Emit tristate buffers with const OE for some edge cases.
Marcin Kościelnicki [Wed, 25 Dec 2019 15:18:44 +0000 (16:18 +0100)]
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki [Wed, 25 Dec 2019 14:39:40 +0000 (15:39 +0100)]
Minor nit fixes
Eddie Hung [Mon, 23 Dec 2019 22:58:06 +0000 (14:58 -0800)]
Add DSP cascade tests
Eddie Hung [Mon, 23 Dec 2019 22:40:59 +0000 (14:40 -0800)]
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
Eddie Hung [Mon, 23 Dec 2019 22:22:13 +0000 (14:22 -0800)]
Fix CEA/CEB check
Eddie Hung [Mon, 23 Dec 2019 21:41:26 +0000 (13:41 -0800)]
Fix checking CE[AB] and for direct connections
Eddie Hung [Mon, 23 Dec 2019 20:38:18 +0000 (12:38 -0800)]
Support unregistered cascades for A and B inputs
Eddie Hung [Mon, 23 Dec 2019 19:42:46 +0000 (11:42 -0800)]
Add DSP48A* PCOUT -> PCIN cascade support
Marcin Kościelnicki [Sun, 22 Dec 2019 14:30:04 +0000 (14:30 +0000)]
xilinx: Test our DSP48A/DSP48A1 simulation models.
Eddie Hung [Mon, 23 Dec 2019 16:36:20 +0000 (08:36 -0800)]
Disable clock domain partitioning in Yosys pass, let ABC do it
Eddie Hung [Mon, 23 Dec 2019 16:35:53 +0000 (08:35 -0800)]
write_xaiger to opt instead of just clean whiteboxes
Marcin Kościelnicki [Sun, 22 Dec 2019 19:43:39 +0000 (20:43 +0100)]
xilinx_dsp: Initial DSP48A/DSP48A1 support.
Miodrag Milanovic [Sat, 21 Dec 2019 19:23:23 +0000 (20:23 +0100)]
Addressed review comments
Miodrag Milanovic [Sat, 21 Dec 2019 12:21:45 +0000 (13:21 +0100)]
iopad no op for compatibility with old scripts
Miodrag Milanovic [Sat, 21 Dec 2019 12:18:44 +0000 (13:18 +0100)]
Fix xilinx tests, when iopads are default
Miodrag Milanovic [Sat, 21 Dec 2019 10:56:41 +0000 (11:56 +0100)]
Make iopad option default for all xilinx flows
Eddie Hung [Fri, 20 Dec 2019 22:56:08 +0000 (14:56 -0800)]
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
write_xaiger: only instantiate each whitebox cell type once
Eddie Hung [Fri, 20 Dec 2019 22:07:23 +0000 (14:07 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Fri, 20 Dec 2019 22:06:59 +0000 (14:06 -0800)]
Add abc9_arrival times for RAM{32,64}M
Eddie Hung [Fri, 20 Dec 2019 21:56:13 +0000 (13:56 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Thu, 19 Dec 2019 19:24:39 +0000 (11:24 -0800)]
Add RAM{32,64}M to abc9_map.v
Eddie Hung [Fri, 20 Dec 2019 21:38:32 +0000 (13:38 -0800)]
Put specify/endspecify inside ``
Eddie Hung [Fri, 20 Dec 2019 21:09:00 +0000 (13:09 -0800)]
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Interpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung [Fri, 20 Dec 2019 21:07:24 +0000 (13:07 -0800)]
write_xaiger: only instantiate each whitebox cell type once
Eddie Hung [Fri, 20 Dec 2019 21:03:48 +0000 (13:03 -0800)]
Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
Revert "Optimise write_xaiger"
Eddie Hung [Fri, 20 Dec 2019 20:05:45 +0000 (12:05 -0800)]
Revert "Optimise write_xaiger"
Graham Edgecombe [Tue, 19 Nov 2019 19:46:15 +0000 (19:46 +0000)]
Fix linking with Python 3.8
The behaviour of python-config --libs has changed in Python 3.8.
For example, compare the output of it with Python 3.7 and 3.8 on an
ArchLinux system:
$ python3.7-config --libs
-lpython3.7m -lcrypt -lpthread -ldl -lutil -lm
$ python3.8-config --libs
-lcrypt -lpthread -ldl -lutil -lm -lm
$
The lack of -lpython in the latter case causes the linker to fail when
attempting to build Yosys against Python 3.8.
Passing the new --embed flag to python-config adds -lpython, just like
earlier versions of Python:
$ python3.8-config --embed --libs
-lpython3.8 -lcrypt -lpthread -ldl -lutil -lm -lm
$
This commit adds code for automatically detecting support for the
--embed flag. If it is supported, it is passed to all python-config
invocations. This fixes building against Python 3.8.
Graham Edgecombe [Tue, 19 Nov 2019 19:45:59 +0000 (19:45 +0000)]
Add PYTHON_CONFIG variable to the Makefile
Eddie Hung [Thu, 19 Dec 2019 19:24:39 +0000 (11:24 -0800)]
Add RAM{32,64}M to abc9_map.v
Eddie Hung [Thu, 19 Dec 2019 19:23:41 +0000 (11:23 -0800)]
Split into $__ABC9_ASYNC[01], do not add cell->type to clkdomain_t
Eddie Hung [Thu, 19 Dec 2019 18:29:40 +0000 (10:29 -0800)]
Merge remote-tracking branch 'origin/master' into xaig_dff
Eddie Hung [Thu, 19 Dec 2019 17:24:27 +0000 (12:24 -0500)]
Merge pull request #1581 from YosysHQ/clifford/fix1565
Fix sim for assignments with lhs<rhs size
Eddie Hung [Thu, 19 Dec 2019 17:24:03 +0000 (12:24 -0500)]
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Optimise write_xaiger
Eddie Hung [Thu, 19 Dec 2019 17:21:33 +0000 (12:21 -0500)]
Merge pull request #1569 from YosysHQ/eddie/fix_1531
verilog: preserve size of $genval$-s in for loops
Eddie Hung [Thu, 19 Dec 2019 17:21:22 +0000 (12:21 -0500)]
Merge pull request #1571 from YosysHQ/eddie/fix_1570
mem_arst.v: do not redeclare ANSI port
Marcin Kościelnicki [Wed, 27 Nov 2019 17:13:00 +0000 (18:13 +0100)]
xilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki [Thu, 19 Dec 2019 07:49:21 +0000 (08:49 +0100)]
xilinx_dffopt: Keep order of LUT inputs.
See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549
Eddie Hung [Wed, 18 Dec 2019 23:14:38 +0000 (15:14 -0800)]
Bump ABC again
Eddie Hung [Wed, 18 Dec 2019 20:21:12 +0000 (12:21 -0800)]
Interpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung [Wed, 18 Dec 2019 20:09:11 +0000 (12:09 -0800)]
Add "scratchpad" to CHANGELOG
Eddie Hung [Wed, 18 Dec 2019 20:08:38 +0000 (12:08 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
David Shah [Wed, 18 Dec 2019 19:42:17 +0000 (19:42 +0000)]
Merge pull request #1563 from YosysHQ/dave/async-prld
ecp5: Add support for mapping PRLD FFs
Eddie Hung [Wed, 18 Dec 2019 18:55:44 +0000 (13:55 -0500)]
Merge pull request #1572 from nakengelhardt/scratchpad_pass
add a command to read/modify scratchpad contents
Eddie Hung [Wed, 18 Dec 2019 17:53:45 +0000 (12:53 -0500)]
Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 14:53:20 +0000 (15:53 +0100)]
tests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 12:42:26 +0000 (13:42 +0100)]
xilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki [Thu, 21 Nov 2019 05:30:06 +0000 (06:30 +0100)]
xilinx: Improve flip-flop handling.
This adds support for infering more kinds of flip-flops:
- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable
Some passes have been moved (and some added) in order for dff2dffs to
work correctly.
This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities). Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.
Clifford Wolf [Wed, 18 Dec 2019 12:06:34 +0000 (13:06 +0100)]
Send people to symbioticeda.com instead of verific.com
Signed-off-by: Clifford Wolf <clifford@clifford.at>
N. Engelhardt [Wed, 18 Dec 2019 11:30:30 +0000 (12:30 +0100)]
use extra_args
Eddie Hung [Wed, 18 Dec 2019 00:11:54 +0000 (16:11 -0800)]
Remove &verify -s
Eddie Hung [Wed, 18 Dec 2019 00:11:37 +0000 (16:11 -0800)]
Bump ABC for upstream fix
Eddie Hung [Wed, 18 Dec 2019 00:10:40 +0000 (16:10 -0800)]
Use pool<> instead of std::set<> to preserver ordering
Eddie Hung [Tue, 17 Dec 2019 23:50:01 +0000 (15:50 -0800)]
aiger frontend to user shorter, $-prefixed, names
Eddie Hung [Tue, 17 Dec 2019 23:44:35 +0000 (15:44 -0800)]
Cleanup xaiger, remove unnecessary complexity with inout
Eddie Hung [Tue, 17 Dec 2019 23:43:21 +0000 (15:43 -0800)]
read_xaiger to cope with optional '\n' after 'c'
Clifford Wolf [Tue, 17 Dec 2019 16:32:48 +0000 (17:32 +0100)]
Fix sim for assignments with lhs<rhs size, fixes #1565
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Tue, 17 Dec 2019 08:25:08 +0000 (00:25 -0800)]
Cleanup
Eddie Hung [Tue, 17 Dec 2019 08:03:03 +0000 (00:03 -0800)]
Do not sigmap
Eddie Hung [Tue, 17 Dec 2019 08:00:07 +0000 (00:00 -0800)]
Revert "Use sigmap signal"
This reverts commit
42f990f3a6b7928841fa0e290fa2688925485907.
Eddie Hung [Tue, 17 Dec 2019 05:48:21 +0000 (21:48 -0800)]
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram
xilinx: add LUTRAM rules for RAM32M, RAM64M
Eddie Hung [Tue, 17 Dec 2019 05:48:02 +0000 (21:48 -0800)]
Merge pull request #1521 from dh73/diego/memattr
Adding support for Xilinx memory attribute 'block' in single port mode.
Eddie Hung [Tue, 17 Dec 2019 02:41:56 +0000 (18:41 -0800)]
abc9 needs a clean afterwards
Eddie Hung [Tue, 17 Dec 2019 01:06:30 +0000 (17:06 -0800)]
Enforce non-existence
Eddie Hung [Tue, 17 Dec 2019 00:48:31 +0000 (16:48 -0800)]
Put $__ABC9_{FF_,ASYNC} into same clock domain as abc9_flop
Eddie Hung [Tue, 17 Dec 2019 00:40:52 +0000 (16:40 -0800)]
Use sigmap signal
Eddie Hung [Mon, 16 Dec 2019 22:48:53 +0000 (14:48 -0800)]
Update doc
Eddie Hung [Mon, 16 Dec 2019 22:39:13 +0000 (14:39 -0800)]
Skip $inout transformation if not a PI
Eddie Hung [Mon, 16 Dec 2019 22:35:35 +0000 (14:35 -0800)]
Revert "write_xaiger: use sigmap bits more consistently"
This reverts commit
6c340112fee1bb8989cbd41923aaa627d77d5110.
Eddie Hung [Mon, 16 Dec 2019 21:57:55 +0000 (13:57 -0800)]
Add another test
Eddie Hung [Mon, 16 Dec 2019 21:56:45 +0000 (13:56 -0800)]
More sloppiness, thanks @dh73 for spotting
Eddie Hung [Mon, 16 Dec 2019 21:31:47 +0000 (13:31 -0800)]
Accidentally commented out tests
Eddie Hung [Mon, 16 Dec 2019 21:31:15 +0000 (13:31 -0800)]
Add unconditional match blocks for force RAM