Clifford Wolf [Tue, 12 Mar 2019 19:12:02 +0000 (20:12 +0100)]
Improve handling of memories used in mem index expressions on LHS of an assignment
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Mar 2019 19:10:55 +0000 (20:10 +0100)]
Remove outdated "blocking assignment to memory" warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 12 Mar 2019 19:09:47 +0000 (20:09 +0100)]
Only set MEM2REG_FL_CONST_LHS/MEM2REG_FL_VAR_LHS for non-init writes, fixes #867
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Mon, 11 Mar 2019 18:58:07 +0000 (11:58 -0700)]
Merge pull request #864 from YosysHQ/svalabelfix
Fix handling of cases that look like sva labels, fixes #862
Clifford Wolf [Mon, 11 Mar 2019 08:08:36 +0000 (01:08 -0700)]
Add ENABLE_GLOB Makefile switch
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 10 Mar 2019 23:27:18 +0000 (16:27 -0700)]
Fix handling of cases that look like sva labels, fixes #862
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 9 Mar 2019 21:24:55 +0000 (13:24 -0800)]
Fix typo in ice40_braminit help msg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 9 Mar 2019 21:24:10 +0000 (13:24 -0800)]
Merge pull request #859 from smunaut/ice40_braminit
iCE40 BRAM primitives init from file
Clifford Wolf [Sat, 9 Mar 2019 21:19:41 +0000 (13:19 -0800)]
Fix signed $shift/$shiftx handling in write_smt2
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 9 Mar 2019 19:52:00 +0000 (11:52 -0800)]
Add $dffsr support to async2sync
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 9 Mar 2019 19:14:57 +0000 (11:14 -0800)]
Merge pull request #858 from YosysHQ/clifford/svalabels
Add support for using SVA labels in yosys-smtbmc console output
Clifford Wolf [Sat, 9 Mar 2019 07:02:56 +0000 (23:02 -0800)]
Merge pull request #861 from YosysHQ/verific_chparam
Add -chparam option to verific command
Clifford Wolf [Sat, 9 Mar 2019 06:53:58 +0000 (22:53 -0800)]
Also add support for labels on sva module items, fixes #699
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Eddie Hung [Sat, 9 Mar 2019 01:56:16 +0000 (01:56 +0000)]
Update help message for -chparam
Eddie Hung [Sat, 9 Mar 2019 01:54:01 +0000 (01:54 +0000)]
Add -chparam option to verific command
Eddie Hung [Sat, 9 Mar 2019 00:43:50 +0000 (00:43 +0000)]
Fix spelling
Clifford Wolf [Fri, 8 Mar 2019 06:44:50 +0000 (22:44 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Fri, 8 Mar 2019 06:44:37 +0000 (22:44 -0800)]
Fix handling of task output ports in clocked always blocks, fixes #857
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Sylvain Munaut [Thu, 7 Mar 2019 23:11:17 +0000 (00:11 +0100)]
ice40: Run ice40_braminit pass by default
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Sylvain Munaut [Thu, 7 Mar 2019 22:48:10 +0000 (23:48 +0100)]
ice40: Add ice40_braminit pass to allow initialization of BRAM from file
This adds a INIT_FILE attribute to the SB_RAM40_4K blocks that will
initialize content from a hex file. Same behavior is imlemented in the
simulation model and in a new pass for actual synthesis
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Thu, 7 Mar 2019 19:34:12 +0000 (11:34 -0800)]
Merge pull request #856 from kprasadvnsi/master
examples/anlogic/ now also output the SVF file.
Clifford Wolf [Thu, 7 Mar 2019 19:31:46 +0000 (11:31 -0800)]
Use SVA label in smt export if available
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 7 Mar 2019 19:17:32 +0000 (11:17 -0800)]
Add support for SVA labels in read_verilog
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 7 Mar 2019 18:52:44 +0000 (10:52 -0800)]
Add hack for handling SVA labels via Verific
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 7 Mar 2019 17:08:26 +0000 (09:08 -0800)]
Add link to SF2 / igloo2 macro library guide
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 7 Mar 2019 00:18:49 +0000 (16:18 -0800)]
Improvements in sf2 cells_sim.v
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Mar 2019 23:47:54 +0000 (15:47 -0800)]
Add sf2 techmap rules for more FF types
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Mar 2019 08:41:02 +0000 (00:41 -0800)]
Refactor SF2 iobuf insertion, Add clkint insertion
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Mar 2019 04:47:07 +0000 (20:47 -0800)]
Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Mar 2019 04:35:48 +0000 (20:35 -0800)]
Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 6 Mar 2019 03:49:39 +0000 (19:49 -0800)]
Improvements in SF2 flow and demo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Kali Prasad [Wed, 6 Mar 2019 04:21:11 +0000 (09:51 +0530)]
examples/anlogic/ now also output the SVF file.
Eddie Hung [Wed, 6 Mar 2019 01:55:29 +0000 (17:55 -0800)]
Fix spelling in pmgen/README.md
Clifford Wolf [Wed, 6 Mar 2019 01:27:58 +0000 (17:27 -0800)]
Improve igloo2 exmaple
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 5 Mar 2019 23:33:19 +0000 (15:33 -0800)]
Merge pull request #842 from litghost/merge_upstream
Changes required for VPR place and route in synth_xilinx
Clifford Wolf [Tue, 5 Mar 2019 23:23:01 +0000 (15:23 -0800)]
Merge pull request #850 from daveshah1/ecp5_warn_conflict
ecp5: Demote conflicting FF init values to a warning
Clifford Wolf [Tue, 5 Mar 2019 23:21:04 +0000 (15:21 -0800)]
Add missing newline
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 5 Mar 2019 23:20:03 +0000 (15:20 -0800)]
Merge pull request #851 from kprasadvnsi/master
Added examples/anlogic/
Clifford Wolf [Tue, 5 Mar 2019 23:19:28 +0000 (15:19 -0800)]
Merge pull request #852 from ucb-bar/firrtlfixes
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Clifford Wolf [Tue, 5 Mar 2019 23:16:13 +0000 (15:16 -0800)]
Use "write_edif -pvector bra" for Xilinx EDIF files
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jim Lawson [Mon, 4 Mar 2019 21:23:58 +0000 (13:23 -0800)]
Ensure fid() calls make_id() for consistency; tests/simple/dff_init.v fails
Mark dff_init.v as expected to fail since it uses "initial value".
Kali Prasad [Mon, 4 Mar 2019 17:56:56 +0000 (23:26 +0530)]
Added examples/anlogic/
Keith Rothman [Mon, 4 Mar 2019 17:22:22 +0000 (09:22 -0800)]
Revert BRAM WRITE_MODE changes.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
David Shah [Mon, 4 Mar 2019 11:18:53 +0000 (11:18 +0000)]
ecp5: Demote conflicting FF init values to a warning
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Mon, 4 Mar 2019 07:54:35 +0000 (23:54 -0800)]
Improve igloo2 example
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 4 Mar 2019 05:35:57 +0000 (21:35 -0800)]
Update igloo2 example to Libero v12.0
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 3 Mar 2019 00:32:58 +0000 (16:32 -0800)]
Merge pull request #848 from YosysHQ/clifford/fix763
Fix error for wire decl in always block, fixes 763
Clifford Wolf [Sun, 3 Mar 2019 00:01:31 +0000 (16:01 -0800)]
Merge pull request #849 from YosysHQ/clifford/dynports
Only run derive on blackbox modules when ports have dynamic size
Clifford Wolf [Sat, 2 Mar 2019 20:36:46 +0000 (12:36 -0800)]
Only run derive on blackbox modules when ports have dynamic size
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 2 Mar 2019 19:40:57 +0000 (11:40 -0800)]
Fix error for wire decl in always block, fixes #763
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 2 Mar 2019 18:38:13 +0000 (10:38 -0800)]
Fix $global_clock handling vs autowire
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 2 Mar 2019 18:27:58 +0000 (10:27 -0800)]
Merge pull request #847 from YosysHQ/clifford/fix785
Fix $readmem[hb] for mem2reg memories, fixes #785
Clifford Wolf [Sat, 2 Mar 2019 17:58:20 +0000 (09:58 -0800)]
Fix $readmem[hb] for mem2reg memories, fixes #785
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 2 Mar 2019 16:40:54 +0000 (08:40 -0800)]
Merge pull request #843 from YosysHQ/clifford/mem2regconstidx
Use mem2reg on memories that only have constant-index write ports
Clifford Wolf [Sat, 2 Mar 2019 16:40:17 +0000 (08:40 -0800)]
Merge pull request #845 from YosysHQ/clifford/travisnomacos
Disable macOS builds in Travis
Clifford Wolf [Sat, 2 Mar 2019 16:29:28 +0000 (08:29 -0800)]
Disable macOS builds in Travis
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Larry Doolittle [Sat, 2 Mar 2019 04:15:20 +0000 (20:15 -0800)]
Try again for passes/pmgen/ice40_dsp_pm.h rule
Tested on both in-tree and out-of-tree builds
Keith Rothman [Fri, 1 Mar 2019 22:41:21 +0000 (14:41 -0800)]
Revert FF models to include IS_x_INVERTED parameters.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Keith Rothman [Fri, 1 Mar 2019 22:35:14 +0000 (14:35 -0800)]
Use singular for disabling of DRAM or BRAM inference.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 1 Mar 2019 22:29:17 +0000 (14:29 -0800)]
Minor improvements in README
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Mar 2019 21:35:09 +0000 (13:35 -0800)]
Use mem2reg on memories that only have constant-index write ports
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Mar 2019 20:59:07 +0000 (12:59 -0800)]
Fix "write_edif -gndvccy"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Keith Rothman [Fri, 1 Mar 2019 20:14:27 +0000 (12:14 -0800)]
Modify arguments to match existing style.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Keith Rothman [Fri, 1 Mar 2019 19:21:07 +0000 (11:21 -0800)]
Changes required for VPR place and route synth_xilinx.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 1 Mar 2019 18:53:23 +0000 (10:53 -0800)]
Merge pull request #841 from mmicko/master
Fix ECP5 cells_sim for iverilog
Miodrag Milanovic [Fri, 1 Mar 2019 18:25:23 +0000 (19:25 +0100)]
Fix ECP5 cells_sim for iverilog
Clifford Wolf [Fri, 1 Mar 2019 04:34:42 +0000 (20:34 -0800)]
Improve "read" error msg
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Mar 2019 04:27:27 +0000 (20:27 -0800)]
Merge pull request #836 from elmsfu/ice40_2bit_ram_rw_mode
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
Clifford Wolf [Fri, 1 Mar 2019 04:26:54 +0000 (20:26 -0800)]
Hotfix for "make test"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 1 Mar 2019 01:40:38 +0000 (17:40 -0800)]
Merge pull request #837 from YosysHQ/clifford/fix835
Fix multiple issues in wreduce FF handling, fixes #835
Clifford Wolf [Fri, 1 Mar 2019 01:24:46 +0000 (17:24 -0800)]
Fix multiple issues in wreduce FF handling, fixes #835
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Elms [Fri, 1 Mar 2019 00:22:24 +0000 (16:22 -0800)]
ice40: use 2 bits for READ/WRITE MODE for SB_RAM map
EBLIF output .param will only use necessary 2 bits
Signed-off-by: Elms <elms@freshred.net>
Clifford Wolf [Thu, 28 Feb 2019 23:03:55 +0000 (15:03 -0800)]
Merge pull request #834 from YosysHQ/clifford/siminit
Add "write_verilog -siminit"
Clifford Wolf [Thu, 28 Feb 2019 22:56:55 +0000 (14:56 -0800)]
Add "write_verilog -siminit"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Larry Doolittle [Tue, 26 Feb 2019 18:28:42 +0000 (10:28 -0800)]
Reduce amount of trailing whitespace in code base
Clifford Wolf [Thu, 28 Feb 2019 22:56:05 +0000 (14:56 -0800)]
Fix pmgen for in-tree builds
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 28 Feb 2019 22:46:56 +0000 (14:46 -0800)]
Merge pull request #794 from daveshah1/ecp5improve
ECP5 Improvements
Clifford Wolf [Thu, 28 Feb 2019 22:45:04 +0000 (14:45 -0800)]
Merge pull request #827 from ucb-bar/firrtlfixes
Fix FIRRTL to Verilog process instance subfield assignment.
Clifford Wolf [Thu, 28 Feb 2019 22:00:58 +0000 (14:00 -0800)]
Fix pmgen for out-of-tree build
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 28 Feb 2019 21:40:27 +0000 (13:40 -0800)]
Merge pull request #833 from YosysHQ/clifford/fix831
Fix smt2 code generation for partially initialized memory words, fixe…
Clifford Wolf [Thu, 28 Feb 2019 20:15:58 +0000 (12:15 -0800)]
Fix smt2 code generation for partially initialized memowy words, fixes #831
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 28 Feb 2019 20:08:01 +0000 (12:08 -0800)]
Merge pull request #832 from YosysHQ/supercover
Add "supercover" pass
Clifford Wolf [Wed, 27 Feb 2019 19:45:13 +0000 (11:45 -0800)]
Improvements in "supercover" pass
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 27 Feb 2019 19:37:08 +0000 (11:37 -0800)]
Add "supercover" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Larry Doolittle [Mon, 25 Feb 2019 06:09:54 +0000 (22:09 -0800)]
techlibs/greenpak4/cells_map.v: Harmonize whitespace within lut module
Larry Doolittle [Mon, 25 Feb 2019 06:08:52 +0000 (22:08 -0800)]
Clean up some whitepsace outliers
Jim Lawson [Tue, 26 Feb 2019 00:18:13 +0000 (16:18 -0800)]
Fix FIRRTL to Verilog process instance subfield assignment.
Don't emit subfield assignments: bits(x, y, z) <= ... - but instead, add them to the reverse-wire-map where they'll be treated at the end of the module.
Enable tests which were disabled due to incorrect treatment of subfields.
Assume the `$firrtl2verilog` variable contains any additional switches to control verilog generation (i.e. `--no-dedup -X mverilog`)
David Shah [Tue, 19 Feb 2019 19:35:10 +0000 (19:35 +0000)]
ecp5: Compatibility with Migen AsyncResetSynchronizer
Signed-off-by: David Shah <davey1576@gmail.com>
Clifford Wolf [Sun, 24 Feb 2019 19:41:36 +0000 (20:41 +0100)]
Minor changes ontop of
71bcc4c: Remove hierarchy warning that is redundant to -check
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 19:39:13 +0000 (11:39 -0800)]
Merge pull request #812 from ucb-bar/arrayhierarchyfixes
Define basic_cell_type() function and use it to derive the cell type …
Clifford Wolf [Sun, 24 Feb 2019 19:34:23 +0000 (20:34 +0100)]
Cleanups in ARST handling in wreduce
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 19:29:14 +0000 (11:29 -0800)]
Merge pull request #824 from litghost/fix_reduce_on_ff
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Clifford Wolf [Sun, 24 Feb 2019 19:09:41 +0000 (20:09 +0100)]
Fix handling of defparam for when default_nettype is none
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 24 Feb 2019 18:51:30 +0000 (19:51 +0100)]
Check if Verific was built with DB_PRESERVE_INITIAL_VALUE
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Jim Lawson [Sat, 23 Feb 2019 00:06:10 +0000 (16:06 -0800)]
Address requested changes - don't require non-$ name.
Suppress warning if name does begin with a `$`.
Fix hierachy tests so they have something to grep.
Announce hierarchy test types.
Keith Rothman [Fri, 22 Feb 2019 18:28:28 +0000 (10:28 -0800)]
Fix WREDUCE on FF not fixing ARST_VALUE parameter.
Adds test case that fails without code change.
Signed-off-by: Keith Rothman <537074+litghost@users.noreply.github.com>
Clifford Wolf [Fri, 22 Feb 2019 05:55:48 +0000 (06:55 +0100)]
Merge pull request #819 from YosysHQ/clifford/optd
Rename "yosys -D" to "yosys -U", add "yosys -D" with expected behavior
Clifford Wolf [Fri, 22 Feb 2019 05:54:48 +0000 (06:54 +0100)]
Merge pull request #820 from YosysHQ/clifford/fix810
Fix #810 and fix #814
Clifford Wolf [Fri, 22 Feb 2019 00:16:34 +0000 (01:16 +0100)]
Merge pull request #740 from daveshah1/improve_dress
Improve ABC netname preservation
Clifford Wolf [Thu, 21 Feb 2019 22:13:14 +0000 (23:13 +0100)]
Fix Travis
It looks like that whole "Fixing Travis's git clone" code was just
there to make the "git describe --tags" work. I simply removed both.
Signed-off-by: Clifford Wolf <clifford@clifford.at>