Sean Cross [Tue, 10 Mar 2020 12:37:55 +0000 (20:37 +0800)]
soc/cores/i2s: fix rst parsing errors
The ModuleDoc-generated documentation for the i2s module produced
slightly invalid output due to ambiguities in how rst assigns headers.
As a result, sections from the i2s document would appear as full
sections.
This cleans up these errors so that it parses properly under sphinx.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Fri, 6 Mar 2020 19:05:27 +0000 (20:05 +0100)]
soc: allow creating SoC without BIOS.
By default the behaviour is unchanged and the SoC will provide a ROM:
./arty.py
Bus Regions: (4)
rom : Origin: 0x00000000, Size: 0x00008000, Mode: R, Cached: True Linker: False
sram : Origin: 0x01000000, Size: 0x00001000, Mode: RW, Cached: True Linker: False
main_ram : Origin: 0x40000000, Size: 0x10000000, Mode: RW, Cached: True Linker: False
csr : Origin: 0x82000000, Size: 0x00010000, Mode: RW, Cached: False Linker: False
The integrated rom can be disabled with:
./arty.py --integrated-rom-size=0
but the SoC builder will check for a user provided rom, and if not provided will complains:
ERROR:SoC:CPU needs rom Region to be defined as Bus or Linker Region.
When a rom is provided, the CPU will use the rom base address as cpu_reset_address.
If the user just wants the CPU to start at a specified address without providing a rom,
the cpu_reset_address parameter can be used:
./arty.py --integrated-rom-size=0 --cpu-reset-address=0x01000000
If the provided reset address is not located in any defined Region, an error will
be produced:
ERROR:SoC:CPU needs reset address 0x00000000 to be in a defined Region.
When no rom is provided, the builder will not build the BIOS.
enjoy-digital [Fri, 6 Mar 2020 18:00:13 +0000 (19:00 +0100)]
Merge pull request #416 from enjoy-digital/csr_svd
Add SVD export capability to Builder (csr_svd parameter) and targets …
Florent Kermarrec [Fri, 6 Mar 2020 13:53:59 +0000 (14:53 +0100)]
integration/builder: rename software methods to _prepare_rom_software/_generate_rom_software/_initialize_rom_software.
Florent Kermarrec [Fri, 6 Mar 2020 13:20:32 +0000 (14:20 +0100)]
integration/builder: generate csr maps before compiling software.
Florent Kermarrec [Fri, 6 Mar 2020 07:36:52 +0000 (08:36 +0100)]
Add SVD export capability to Builder (csr_svd parameter) and targets (--csr-svd argument) and fix svd regression.
This allows generating SVD export files during the build as we are already doing for .csv or .json.
Use with Builder:
builder = Builder(soc, csr_svd="csr.svd")
Use with target:
./arty.py --csr-svd=csr.svd
Florent Kermarrec [Thu, 5 Mar 2020 22:42:16 +0000 (23:42 +0100)]
software/common.mak: fix LTO refactoring issue.
enjoy-digital [Thu, 5 Mar 2020 18:05:02 +0000 (19:05 +0100)]
Merge pull request #412 from antmicro/fix-copyrights
Fix copyrights
Karol Gugala [Thu, 5 Mar 2020 16:44:10 +0000 (17:44 +0100)]
Fix copyrights
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Signed-off-by: Mateusz Holenko <mholenko@antmicro.com>
enjoy-digital [Thu, 5 Mar 2020 14:22:40 +0000 (15:22 +0100)]
Merge pull request #408 from gsomlo/gls-fix-nexys-sdcard
targets/nexys4ddr: fix sdcard clocker initialization
Gabriel Somlo [Wed, 4 Mar 2020 18:38:02 +0000 (13:38 -0500)]
targets/nexys4ddr: fix sdcard clocker initialization
enjoy-digital [Thu, 5 Mar 2020 10:43:02 +0000 (11:43 +0100)]
Merge pull request #410 from antmicro/netv2-edid
platform/netv2: add proper I2C pins for HDMI IN0
Piotr Binkowski [Thu, 5 Mar 2020 10:27:47 +0000 (11:27 +0100)]
platform/netv2: add proper I2C pins for HDMI IN0
Florent Kermarrec [Thu, 5 Mar 2020 10:19:29 +0000 (11:19 +0100)]
targets/ecp5: make sure all BaseSoC/EthernetSoc default to trellis.
Florent Kermarrec [Wed, 4 Mar 2020 17:33:08 +0000 (18:33 +0100)]
bios/sdcard: update sdclk_mmcm_write with LiteSDCard clocker changes.
Florent Kermarrec [Wed, 4 Mar 2020 15:31:41 +0000 (16:31 +0100)]
doc: align to improve readability.
Florent Kermarrec [Wed, 4 Mar 2020 15:27:11 +0000 (16:27 +0100)]
soc/doc: remove soc.get_csr_regions support.
Now that SoC documentation is integrated in LiteX, this is no longer needed.
Florent Kermarrec [Wed, 4 Mar 2020 14:53:18 +0000 (15:53 +0100)]
bios/main: rename flushl2 command to flush_l2_cache, add flush_cpu_dcache command and expose them in help.
Florent Kermarrec [Wed, 4 Mar 2020 14:21:43 +0000 (15:21 +0100)]
README: update quick start guide and add instructions for windows.
Florent Kermarrec [Wed, 4 Mar 2020 11:16:03 +0000 (12:16 +0100)]
README: update
- improve presentation
- add link to #litex freenode channel.
- add example of complex SoC.
- make it directly usable on Wiki.
- only keep one quick start guide.
- add community paragraph and link to Litex-Hub.
Florent Kermarrec [Wed, 4 Mar 2020 09:53:44 +0000 (10:53 +0100)]
doc: remove partial doc imported from litex-buildenv-wiki: we'll create a LiteX wiki and doc.
Florent Kermarrec [Wed, 4 Mar 2020 08:06:27 +0000 (09:06 +0100)]
build: assume vendor tools are in the PATH and remove automatic sourcing, source and toolchain_path parameters.
Automatic sourcing was not consistent between build backends (and only really supported by ISE/Vivado)
and had no real additional value vs the complexity needed to support it. Now just assume required vendor
tools are in the PATH.
This also removes distutils dependency.
Florent Kermarrec [Wed, 4 Mar 2020 07:11:21 +0000 (08:11 +0100)]
software/common: add LTO enable flag and cleanup.
Florent Kermarrec [Tue, 3 Mar 2020 18:04:18 +0000 (19:04 +0100)]
litex_sim: fix with_uart parameter.
Florent Kermarrec [Mon, 2 Mar 2020 08:44:20 +0000 (09:44 +0100)]
targets/nexys4ddr: add default kwargs parameters.
Florent Kermarrec [Mon, 2 Mar 2020 08:31:45 +0000 (09:31 +0100)]
Merge branch 'master' of https://github.com/enjoy-digital/litex
Florent Kermarrec [Mon, 2 Mar 2020 08:31:32 +0000 (09:31 +0100)]
integration/soc_core: change disable parameters to no-xxyy.
enjoy-digital [Mon, 2 Mar 2020 08:30:05 +0000 (09:30 +0100)]
Merge pull request #405 from sajattack/sifive-triple
add riscv-sifive-elf triple
Florent Kermarrec [Mon, 2 Mar 2020 08:07:31 +0000 (09:07 +0100)]
integration/soc: add auto_int type and use it on all int parameters.
Allow passing parameters as int or hex values.
Florent Kermarrec [Mon, 2 Mar 2020 08:01:05 +0000 (09:01 +0100)]
targets/nexys4ddr: use SoCCore and add_sdram to avoid use of specific SoCSDRAM.
Florent Kermarrec [Mon, 2 Mar 2020 07:42:59 +0000 (08:42 +0100)]
integration/soc: add ethphy CSR in target.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:44 +0000 (20:50 +0100)]
targets/nexys4ddr: use soc.add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 19:50:13 +0000 (20:50 +0100)]
integration/soc: add add_ethernet method.
Florent Kermarrec [Sun, 1 Mar 2020 17:58:55 +0000 (18:58 +0100)]
integration/soc: mode litedram imports to add_sdram, remove some separators.
Paul Sajna [Sun, 1 Mar 2020 09:39:03 +0000 (01:39 -0800)]
add riscv-sifive-elf triple
Florent Kermarrec [Sat, 29 Feb 2020 10:07:06 +0000 (11:07 +0100)]
test/test_targets: use uart-name=stub.
Florent Kermarrec [Fri, 28 Feb 2020 21:34:11 +0000 (22:34 +0100)]
soc/uart: add configurable UART FIFO depth.
Florent Kermarrec [Fri, 28 Feb 2020 21:11:51 +0000 (22:11 +0100)]
cores/uart: cleanup
Florent Kermarrec [Fri, 28 Feb 2020 21:03:40 +0000 (22:03 +0100)]
soc/cores/uart/UARTCrossover: reduce fifo_depth to 1.
Florent Kermarrec [Fri, 28 Feb 2020 19:03:47 +0000 (20:03 +0100)]
interconnect/stream/SyncFIFO: allow depth down to 0.
Florent Kermarrec [Fri, 28 Feb 2020 15:33:18 +0000 (16:33 +0100)]
interconnect/axi: remove Record inheritance on AXIInterface/AXILiteInterface.
Florent Kermarrec [Fri, 28 Feb 2020 15:25:09 +0000 (16:25 +0100)]
interconnect/axi: add AXI Stream definition and get_ios/connect_to_pads methods.
Florent Kermarrec [Fri, 28 Feb 2020 12:19:10 +0000 (13:19 +0100)]
interconnect/axi: set default data_width/address_width to 32-bit.
Florent Kermarrec [Fri, 28 Feb 2020 08:48:48 +0000 (09:48 +0100)]
targets: default to trellis toolchain on all ECP5 targets (now able to build all supported targets).
Florent Kermarrec [Fri, 28 Feb 2020 08:10:28 +0000 (09:10 +0100)]
cores/gpio: use separate TSTriple for each bit.
This fixes per bit OE control.
Florent Kermarrec [Fri, 28 Feb 2020 07:32:29 +0000 (08:32 +0100)]
lattice/yosys: don't use quiet operation since logs are useful and for consistency with others build backends.
Florent Kermarrec [Thu, 27 Feb 2020 12:00:35 +0000 (13:00 +0100)]
targets/kc705: use DDRPHY_CMD_DELAY to center write leveling.
Florent Kermarrec [Thu, 27 Feb 2020 11:25:37 +0000 (12:25 +0100)]
software/bios/sdram: allow setting CLK/CMD delay from user design and configure it before write/read leveling.
Setting a manual delay on CLK/CMD vs DQ/DQS is required on some configuration to center the write leveling window:
Before (delay = 0 taps):
Write leveling:
m0: |
11000000000000011111111111| delay: 15
m1: |
00000000000000111111111111| delay: 14
m2: |
11110000000000000111111111| delay: 17
m3: |
11110000000000000011111111| delay: 18
m4: |
11111111110000000000000111| delay: 00
m5: |
11111111110000000000000111| delay: 00
m6: |
11111111111000000000000001| delay: 00
m7: |
11111111111000000000000011| delay: 00
After (delay = 12 taps):
Write leveling:
m0: |
11111111111111000000000000| delay: 00
m1: |
11111111111100000000000001| delay: 00
m2: |
00011111111111110000000000| delay: 03
m3: |
00011111111111110000000000| delay: 03
m4: |
00000000111111111111110000| delay: 08
m5: |
00000000111111111111110000| delay: 08
m6: |
00000000001111111111111000| delay: 10
m7: |
00000000001111111111111000| delay: 10
Florent Kermarrec [Thu, 27 Feb 2020 10:18:14 +0000 (11:18 +0100)]
boards: keep in sync with LiteX-boards
Florent Kermarrec [Wed, 26 Feb 2020 14:13:16 +0000 (15:13 +0100)]
interconnect/axi: remove mode on AXIInterface (not used and breaking LiteDRAM tests)
Florent Kermarrec [Wed, 26 Feb 2020 13:43:01 +0000 (14:43 +0100)]
integration/soc: -x on soc.py
Florent Kermarrec [Tue, 25 Feb 2020 14:56:27 +0000 (15:56 +0100)]
soc/cores/bitbang: fix missing self.comb on miso.
enjoy-digital [Tue, 25 Feb 2020 14:53:13 +0000 (15:53 +0100)]
Merge pull request #402 from antmicro/litex-gen-fix-uart-pins
tools: litex_gen: fix missing UART pins
Florent Kermarrec [Tue, 25 Feb 2020 14:31:27 +0000 (15:31 +0100)]
software: disable LTO with LM32 (not supported by old GCC versions easily available).
enjoy-digital [Tue, 25 Feb 2020 14:32:12 +0000 (15:32 +0100)]
Merge pull request #401 from antmicro/enable-lto
software: enable link time optimization (LTO)
Jan Kowalewski [Tue, 25 Feb 2020 13:24:29 +0000 (14:24 +0100)]
tools: litex_gen: fix missing UART pins
Tim 'mithro' Ansell [Tue, 27 Nov 2018 08:48:44 +0000 (00:48 -0800)]
software: enable link time optimization (LTO)
Co-authored-by: Pawel Czarnecki <pczarnecki@internships.antmicro.com>
enjoy-digital [Mon, 24 Feb 2020 13:49:35 +0000 (14:49 +0100)]
Merge pull request #400 from Xiretza/ecp5-pll-freqfix
Fix ECP5PLL VCO frequency range
Xiretza [Mon, 24 Feb 2020 13:39:44 +0000 (14:39 +0100)]
Fix ECP5PLL VCO frequency range
See https://www.latticesemi.com/view_document?document_id=50461 ("ECP5
and ECP5-5G Family Data Sheet"), section 3.19 "sysCLOCK PLL Timing".
Florent Kermarrec [Mon, 24 Feb 2020 12:37:38 +0000 (13:37 +0100)]
integration/soc: improve presentation of SoCLocHandler's locations.
Florent Kermarrec [Mon, 24 Feb 2020 12:24:32 +0000 (13:24 +0100)]
interconnect/axi: remove bus_name on connect_to_pads
Florent Kermarrec [Mon, 24 Feb 2020 11:49:42 +0000 (12:49 +0100)]
tools/litex_gen: add bus parameter and AXI (Lite) support.
Florent Kermarrec [Mon, 24 Feb 2020 11:48:52 +0000 (12:48 +0100)]
litex_gen/axi: simplify the way the bus is exposed as ios and connected to pads.
Florent Kermarrec [Mon, 24 Feb 2020 10:58:27 +0000 (11:58 +0100)]
litex_gen/wishbone: simplify the way the bus is exposed as ios and connected to pads.
Florent Kermarrec [Mon, 24 Feb 2020 09:25:18 +0000 (10:25 +0100)]
tools: rename litex_extract to litex_gen (use similar name than litedram/liteeth generators) and cleanup/simplify.
enjoy-digital [Mon, 24 Feb 2020 09:01:16 +0000 (10:01 +0100)]
Merge pull request #396 from antmicro/external-wb
Add a script that allows to generate standalone cores
enjoy-digital [Fri, 21 Feb 2020 20:08:22 +0000 (21:08 +0100)]
Merge pull request #397 from gsomlo/gls-csr-volatile
Add 'volatile' qualifier to new CSR accessors
Gabriel Somlo [Thu, 6 Feb 2020 23:30:22 +0000 (18:30 -0500)]
Add 'volatile' qualifier to new CSR accessors
Through their use of the MMPTR() macro, the "classic"
csr_[read|write]simple() accsessors identify the MMIO
subregister with the 'volatile' qualifier.
Adjust the new, csr_[rd|wr]_uint[8|16|32|64]() accessors
to also utilize the 'volatile' qualifier. Since accesses
are implicit (a[i], where a is an 'unsigned long *'),
change 'a' to be a 'volatile unsigned long *' instead.
No difference was noticed in opcodes generated using the
gcc9 risc-v cross-compiler on x86_64 with standard LiteX
cflags (vexriscv and rocket were tested), but since
reports exist that 'volatile' matters on some combinations
of compilers and targets, add the 'volatile' qualifier just
to be on the safe side.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com
Piotr Binkowski [Fri, 21 Feb 2020 13:43:15 +0000 (14:43 +0100)]
tools: add script for extracting wishbone cores
Karol Gugala [Mon, 3 Feb 2020 13:38:24 +0000 (14:38 +0100)]
axi: add to_pads method
Signed-off-by: Karol Gugala <kgugala@antmicro.com>
Jan Kowalewski [Thu, 13 Feb 2020 15:41:11 +0000 (16:41 +0100)]
wishbone: add extracting module signals to the top
Florent Kermarrec [Thu, 20 Feb 2020 18:47:15 +0000 (19:47 +0100)]
doc/socdoc: fix example
Florent Kermarrec [Thu, 20 Feb 2020 17:50:13 +0000 (18:50 +0100)]
cpu/blackparrot: first cleanup pass
Florent Kermarrec [Thu, 20 Feb 2020 15:16:07 +0000 (16:16 +0100)]
integration/soc: set base_address on LiteDRAMWishbone2Native, fix addressing with >= 1GB SDRAMs.
Florent Kermarrec [Thu, 20 Feb 2020 12:46:39 +0000 (13:46 +0100)]
build/sim: add Verilator FST tracing support.
enjoy-digital [Thu, 20 Feb 2020 07:17:54 +0000 (08:17 +0100)]
Merge pull request #390 from gsomlo/gls-add-sdcard
Import LiteSDCard support in to LiteX, using nexys4ddr as the initial test target
Gabriel Somlo [Thu, 20 Feb 2020 01:14:10 +0000 (20:14 -0500)]
targets/nexys4ddr: add optional sdcard support
Add the option to select LiteSDCard support in BaseSoC, via the
'--with-sdcard' command line argument.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Wed, 8 Jan 2020 17:49:52 +0000 (12:49 -0500)]
bios: add litesdcard test routines to boot menu
This is a straightforward import of the sdcard initialization and
testing routines from the LiteSDCard demo example, made available
as mainline LiteX bios boot-prompt commands.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Gabriel Somlo [Thu, 20 Feb 2020 01:10:32 +0000 (20:10 -0500)]
targets/nexys4ddr: add ethernet via method instead of inheritance
Switch adding LiteETH support to BaseSoc via a method instead of
inheritance. This allows further optional peripherals to be added
in the future, via additional methods.
Signed-off-by: Gabriel Somlo <gsomlo@gmail.com>
Florent Kermarrec [Wed, 19 Feb 2020 13:58:55 +0000 (14:58 +0100)]
soc_core: fix missing init on main_ram
enjoy-digital [Tue, 18 Feb 2020 16:54:13 +0000 (17:54 +0100)]
Merge pull request #389 from antmicro/linux_flash_offsets
bios/boot: allow to customize flash offsets of Linux images
Florent Kermarrec [Tue, 18 Feb 2020 15:59:55 +0000 (16:59 +0100)]
cores/cpu: use standard+debug variant when only debug is specified.
Mateusz Holenko [Mon, 17 Feb 2020 15:52:08 +0000 (16:52 +0100)]
bios/boot: allow to customize flash offsets of Linux images
Florent Kermarrec [Tue, 18 Feb 2020 09:15:01 +0000 (10:15 +0100)]
soc/cores/clock: add reset_cycles parameter to S7IDELAYCTRL/USIDELAYCTRL
Florent Kermarrec [Tue, 18 Feb 2020 08:11:40 +0000 (09:11 +0100)]
soc/csr_bus: fix aligned_paging computation (should be done with SoC's Bus data width not bus.alignment)
Florent Kermarrec [Tue, 18 Feb 2020 07:27:59 +0000 (08:27 +0100)]
integration/soc: improve Region logger
Florent Kermarrec [Mon, 17 Feb 2020 18:21:35 +0000 (19:21 +0100)]
bios/boot: update and fix flashboot, improve verbosity
Florent Kermarrec [Mon, 17 Feb 2020 07:36:36 +0000 (08:36 +0100)]
soc: increase supporteds address_width/paging
Florent Kermarrec [Mon, 17 Feb 2020 07:34:10 +0000 (08:34 +0100)]
soc_core: expose CSR paging
Florent Kermarrec [Mon, 17 Feb 2020 07:28:56 +0000 (08:28 +0100)]
soc/csr_bus: improve CSR paging genericity
Florent Kermarrec [Sun, 16 Feb 2020 15:09:06 +0000 (16:09 +0100)]
tools/litex_sim: use new sdram verbosity parameter
Florent Kermarrec [Sun, 16 Feb 2020 11:32:05 +0000 (12:32 +0100)]
integration/soc: add configurable CSR Paging
Florent Kermarrec [Sat, 15 Feb 2020 18:04:47 +0000 (19:04 +0100)]
soc_core: add back identifier
enjoy-digital [Sat, 15 Feb 2020 16:05:50 +0000 (17:05 +0100)]
Merge pull request #387 from BracketMaster/master
litex_sim now working on MacOS and Linux
Yehowshua Immanuel [Fri, 14 Feb 2020 22:53:25 +0000 (17:53 -0500)]
update to work with mac
Florent Kermarrec [Sat, 15 Feb 2020 13:04:44 +0000 (14:04 +0100)]
tools/litex_sim: specify default local/remote-ip addresses.
Florent Kermarrec [Sat, 15 Feb 2020 13:01:46 +0000 (14:01 +0100)]
tools/litex_sim: add ethernet local/remote-ip arguments.
Florent Kermarrec [Fri, 14 Feb 2020 07:08:19 +0000 (08:08 +0100)]
interconnect/stream: cleanup imports/idents
enjoy-digital [Thu, 13 Feb 2020 15:53:12 +0000 (16:53 +0100)]
Merge pull request #386 from antmicro/sdram-timing-checker
tools/litex_sim: add cli options to control SDRAM timing checker
Piotr Binkowski [Thu, 13 Feb 2020 13:45:15 +0000 (14:45 +0100)]
tools/litex_sim: add cli options to control SDRAM timing checker