yosys.git
10 years agoCleanups and improvements in wreduce pass
Clifford Wolf [Tue, 5 Aug 2014 11:11:04 +0000 (13:11 +0200)]
Cleanups and improvements in wreduce pass

10 years agoAdded mux support to wreduce command
Clifford Wolf [Tue, 5 Aug 2014 10:49:53 +0000 (12:49 +0200)]
Added mux support to wreduce command

10 years agoImproved scope resolution of local regs in Verilog+AST frontend
Clifford Wolf [Tue, 5 Aug 2014 10:15:53 +0000 (12:15 +0200)]
Improved scope resolution of local regs in Verilog+AST frontend

10 years agoFixed AST handling of variables declared inside a functions main block
Clifford Wolf [Tue, 5 Aug 2014 06:35:51 +0000 (08:35 +0200)]
Fixed AST handling of variables declared inside a functions main block

10 years agoAdded "show -signed"
Clifford Wolf [Mon, 4 Aug 2014 13:33:51 +0000 (15:33 +0200)]
Added "show -signed"

10 years agoAdded support for non-standard "module mod_name(...);" syntax
Clifford Wolf [Mon, 4 Aug 2014 13:19:24 +0000 (15:19 +0200)]
Added support for non-standard "module mod_name(...);" syntax

10 years agoAdded RTLIL::IdString::in(...)
Clifford Wolf [Mon, 4 Aug 2014 13:08:35 +0000 (15:08 +0200)]
Added RTLIL::IdString::in(...)

10 years agoFixed "share" for memory read ports
Clifford Wolf [Sun, 3 Aug 2014 18:19:50 +0000 (20:19 +0200)]
Fixed "share" for memory read ports

10 years agoAdded "wreduce" to some of the standard test benches
Clifford Wolf [Sun, 3 Aug 2014 18:03:16 +0000 (20:03 +0200)]
Added "wreduce" to some of the standard test benches

10 years agoProgress in "wreduce" pass
Clifford Wolf [Sun, 3 Aug 2014 18:02:42 +0000 (20:02 +0200)]
Progress in "wreduce" pass

10 years agoAdded "wreduce" command (work in progress)
Clifford Wolf [Sun, 3 Aug 2014 13:02:05 +0000 (15:02 +0200)]
Added "wreduce" command (work in progress)

10 years agoAdded query() API to ModIndex
Clifford Wolf [Sun, 3 Aug 2014 13:00:38 +0000 (15:00 +0200)]
Added query() API to ModIndex

10 years agoAdded ID() macro for static IdStrings
Clifford Wolf [Sun, 3 Aug 2014 12:59:13 +0000 (14:59 +0200)]
Added ID() macro for static IdStrings

10 years agoImplemented recursive techmap
Clifford Wolf [Sun, 3 Aug 2014 10:40:43 +0000 (12:40 +0200)]
Implemented recursive techmap

10 years agoFixes in show command (related to new IdString)
Clifford Wolf [Sun, 3 Aug 2014 10:40:23 +0000 (12:40 +0200)]
Fixes in show command (related to new IdString)

10 years agoImplemented simplemap support for "techmap -extern"
Clifford Wolf [Sat, 2 Aug 2014 19:55:13 +0000 (21:55 +0200)]
Implemented simplemap support for "techmap -extern"

10 years agoFixed a va_list corruption in logv_error()
Clifford Wolf [Sat, 2 Aug 2014 19:54:30 +0000 (21:54 +0200)]
Fixed a va_list corruption in logv_error()

10 years agoBe more conservative with printing decimal numbers in verilog backend
Clifford Wolf [Sat, 2 Aug 2014 19:54:02 +0000 (21:54 +0200)]
Be more conservative with printing decimal numbers in verilog backend

10 years agoImproved verilog output for ordinary $mux cells
Clifford Wolf [Sat, 2 Aug 2014 19:10:08 +0000 (21:10 +0200)]
Improved verilog output for ordinary $mux cells

10 years agoBugfix in "techmap -extern"
Clifford Wolf [Sat, 2 Aug 2014 18:54:30 +0000 (20:54 +0200)]
Bugfix in "techmap -extern"

10 years agoRemoved at() method from RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 17:08:02 +0000 (19:08 +0200)]
Removed at() method from RTLIL::IdString

10 years agoNo implicit conversion from IdString to anything else
Clifford Wolf [Sat, 2 Aug 2014 16:58:40 +0000 (18:58 +0200)]
No implicit conversion from IdString to anything else

10 years agoMore bugfixes related to new RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 14:03:18 +0000 (16:03 +0200)]
More bugfixes related to new RTLIL::IdString

10 years agoLimit size of log_signal buffer to 100 elements
Clifford Wolf [Sat, 2 Aug 2014 13:52:21 +0000 (15:52 +0200)]
Limit size of log_signal buffer to 100 elements

10 years agoImprovements in new RTLIL::IdString implementation
Clifford Wolf [Sat, 2 Aug 2014 13:44:10 +0000 (15:44 +0200)]
Improvements in new RTLIL::IdString implementation

10 years agoFixed a performance bug in opt_reduce
Clifford Wolf [Sat, 2 Aug 2014 13:12:16 +0000 (15:12 +0200)]
Fixed a performance bug in opt_reduce

10 years agoImplemented new reference counting RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 13:11:35 +0000 (15:11 +0200)]
Implemented new reference counting RTLIL::IdString

10 years agoFixed memory corruption related to id2cstr()
Clifford Wolf [Sat, 2 Aug 2014 11:34:07 +0000 (13:34 +0200)]
Fixed memory corruption related to id2cstr()

10 years agoMore cleanups related to RTLIL::IdString usage
Clifford Wolf [Sat, 2 Aug 2014 11:11:01 +0000 (13:11 +0200)]
More cleanups related to RTLIL::IdString usage

10 years agoPreparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf [Fri, 1 Aug 2014 22:45:25 +0000 (00:45 +0200)]
Preparations for RTLIL::IdString redesign: cleanup of existing code

10 years agoAdded logfile hash to statistics footer
Clifford Wolf [Fri, 1 Aug 2014 17:43:28 +0000 (19:43 +0200)]
Added logfile hash to statistics footer

10 years agoReplaced sha1 implementation
Clifford Wolf [Fri, 1 Aug 2014 17:01:10 +0000 (19:01 +0200)]
Replaced sha1 implementation

10 years agoAdded per-pass cpu usage statistics
Clifford Wolf [Fri, 1 Aug 2014 16:42:10 +0000 (18:42 +0200)]
Added per-pass cpu usage statistics

10 years agoAdded ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf [Fri, 1 Aug 2014 14:53:15 +0000 (16:53 +0200)]
Added ModIndex helper class, some changes to RTLIL::Monitor

10 years agoPacked SigBit::data and SigBit::offset in a union
Clifford Wolf [Fri, 1 Aug 2014 13:25:42 +0000 (15:25 +0200)]
Packed SigBit::data and SigBit::offset in a union

10 years agoConsolidated hana test benches into fewer files
Clifford Wolf [Fri, 1 Aug 2014 01:57:37 +0000 (03:57 +0200)]
Consolidated hana test benches into fewer files

for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
    ${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;

..etc..

10 years agoAdded "test_autotb -n <num_iter>" option
Clifford Wolf [Fri, 1 Aug 2014 01:55:51 +0000 (03:55 +0200)]
Added "test_autotb -n <num_iter>" option

10 years agoRenamed modwalker.h to modtools.h
Clifford Wolf [Thu, 31 Jul 2014 21:30:18 +0000 (23:30 +0200)]
Renamed modwalker.h to modtools.h

10 years agoVarious cleanups in Makefile, Renamed default configurations
Clifford Wolf [Thu, 31 Jul 2014 21:14:17 +0000 (23:14 +0200)]
Various cleanups in Makefile, Renamed default configurations

10 years agoAdded compiler + compiler version + compiler flags to version string
Clifford Wolf [Thu, 31 Jul 2014 21:07:00 +0000 (23:07 +0200)]
Added compiler + compiler version + compiler flags to version string

10 years agoFixed build of verific bindings
Clifford Wolf [Thu, 31 Jul 2014 14:45:23 +0000 (16:45 +0200)]
Fixed build of verific bindings

10 years agoRenamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf [Thu, 31 Jul 2014 14:38:54 +0000 (16:38 +0200)]
Renamed port access function on RTLIL::Cell, added param access functions

10 years agoAdded "trace" command
Clifford Wolf [Thu, 31 Jul 2014 13:02:16 +0000 (15:02 +0200)]
Added "trace" command

10 years agoAdded RTLIL::Monitor
Clifford Wolf [Thu, 31 Jul 2014 12:34:12 +0000 (14:34 +0200)]
Added RTLIL::Monitor

10 years agoAdded module->design and cell->module, wire->module pointers
Clifford Wolf [Thu, 31 Jul 2014 12:11:39 +0000 (14:11 +0200)]
Added module->design and cell->module, wire->module pointers

10 years agoMoved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf [Thu, 31 Jul 2014 11:19:47 +0000 (13:19 +0200)]
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace

10 years agoRenamed "stdcells.v" to "techmap.v"
Clifford Wolf [Thu, 31 Jul 2014 00:32:00 +0000 (02:32 +0200)]
Renamed "stdcells.v" to "techmap.v"

10 years agoAdded "techmap -assert"
Clifford Wolf [Thu, 31 Jul 2014 00:21:41 +0000 (02:21 +0200)]
Added "techmap -assert"

10 years agoReorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf [Thu, 31 Jul 2014 00:21:06 +0000 (02:21 +0200)]
Reorganized stdcells.v (no actual code change, just moved and indented stuff)

10 years agoAdded "yosys -A"
Clifford Wolf [Wed, 30 Jul 2014 23:05:27 +0000 (01:05 +0200)]
Added "yosys -A"

10 years agoAdded "yosys -Q"
Clifford Wolf [Wed, 30 Jul 2014 22:53:21 +0000 (00:53 +0200)]
Added "yosys -Q"

10 years agoAdded techmap CONSTMAP feature
Clifford Wolf [Wed, 30 Jul 2014 20:04:30 +0000 (22:04 +0200)]
Added techmap CONSTMAP feature

10 years agoFixed counting verilog line numbers for "// synopsys translate_off" sections
Clifford Wolf [Wed, 30 Jul 2014 18:18:48 +0000 (20:18 +0200)]
Fixed counting verilog line numbers for "// synopsys translate_off" sections

10 years agoAdded write_file command
Clifford Wolf [Wed, 30 Jul 2014 17:59:29 +0000 (19:59 +0200)]
Added write_file command

10 years agoAdded "make -j{N}" support to "make test"
Clifford Wolf [Wed, 30 Jul 2014 17:21:52 +0000 (19:21 +0200)]
Added "make -j{N}" support to "make test"

10 years agoImprovements in test_cell
Clifford Wolf [Wed, 30 Jul 2014 13:59:38 +0000 (15:59 +0200)]
Improvements in test_cell

10 years agoNew techmap default rules for $shr $sshr $shl $sshl
Clifford Wolf [Wed, 30 Jul 2014 13:59:05 +0000 (15:59 +0200)]
New techmap default rules for $shr $sshr $shl $sshl

10 years agoUsing native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
Clifford Wolf [Wed, 30 Jul 2014 15:18:31 +0000 (17:18 +0200)]
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models

10 years agoAdded native support for shift operations to ezSAT
Clifford Wolf [Wed, 30 Jul 2014 15:17:31 +0000 (17:17 +0200)]
Added native support for shift operations to ezSAT

10 years agoAdded "log_dump_val_worker(char *v)"
Clifford Wolf [Wed, 30 Jul 2014 13:58:21 +0000 (15:58 +0200)]
Added "log_dump_val_worker(char *v)"

10 years agoAdded CodingStyle document
Clifford Wolf [Wed, 30 Jul 2014 12:10:49 +0000 (14:10 +0200)]
Added CodingStyle document

10 years agoAdded "kernel/yosys.h" and "kernel/yosys.cc"
Clifford Wolf [Wed, 30 Jul 2014 12:10:15 +0000 (14:10 +0200)]
Added "kernel/yosys.h" and "kernel/yosys.cc"

10 years agoAdded "test_cell" command
Clifford Wolf [Tue, 29 Jul 2014 20:05:00 +0000 (22:05 +0200)]
Added "test_cell" command

10 years agoRenamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf [Tue, 29 Jul 2014 19:12:50 +0000 (21:12 +0200)]
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/

10 years agoFixed Verilog pre-processor for files with no trailing newline
Clifford Wolf [Tue, 29 Jul 2014 18:14:25 +0000 (20:14 +0200)]
Fixed Verilog pre-processor for files with no trailing newline

10 years agoBugfix in simlib.v for iverilog
Clifford Wolf [Tue, 29 Jul 2014 17:23:31 +0000 (19:23 +0200)]
Bugfix in simlib.v for iverilog

10 years agoAllow "hierarchy -generate" for $__ cells
Clifford Wolf [Tue, 29 Jul 2014 14:33:56 +0000 (16:33 +0200)]
Allow "hierarchy -generate" for $__ cells

10 years agoAdded "techmap -map %{design-name}"
Clifford Wolf [Tue, 29 Jul 2014 14:06:27 +0000 (16:06 +0200)]
Added "techmap -map %{design-name}"

10 years agoAdded $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf [Tue, 29 Jul 2014 12:42:33 +0000 (14:42 +0200)]
Added $shift and $shiftx cell types (needed for correct part select behavior)

10 years agoRemoved left over debug code
Clifford Wolf [Mon, 28 Jul 2014 17:38:30 +0000 (19:38 +0200)]
Removed left over debug code

10 years agoFixed part selects of parameters
Clifford Wolf [Mon, 28 Jul 2014 14:45:26 +0000 (16:45 +0200)]
Fixed part selects of parameters

10 years agoSet results of out-of-bounds static bit/part select to undef
Clifford Wolf [Mon, 28 Jul 2014 14:09:50 +0000 (16:09 +0200)]
Set results of out-of-bounds static bit/part select to undef

10 years agoFixed RTLIL code generator for part select of parameter
Clifford Wolf [Mon, 28 Jul 2014 13:31:19 +0000 (15:31 +0200)]
Fixed RTLIL code generator for part select of parameter

10 years agoFixed width detection for part selects
Clifford Wolf [Mon, 28 Jul 2014 13:19:34 +0000 (15:19 +0200)]
Fixed width detection for part selects

10 years agoAdded support for "upto" wires to Verilog front- and back-end
Clifford Wolf [Mon, 28 Jul 2014 12:25:03 +0000 (14:25 +0200)]
Added support for "upto" wires to Verilog front- and back-end

10 years agoAdded wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf [Mon, 28 Jul 2014 10:12:13 +0000 (12:12 +0200)]
Added wire->upto flag for signals such as "wire [0:7] x;"

10 years agoUsing log_assert() instead of assert()
Clifford Wolf [Mon, 28 Jul 2014 09:08:55 +0000 (11:08 +0200)]
Using log_assert() instead of assert()

10 years agoAdded std::initializer_list<> constructor to SigSpec
Clifford Wolf [Mon, 28 Jul 2014 08:52:58 +0000 (10:52 +0200)]
Added std::initializer_list<> constructor to SigSpec

10 years agoAdded cover() to all SigSpec constructors
Clifford Wolf [Mon, 28 Jul 2014 08:52:30 +0000 (10:52 +0200)]
Added cover() to all SigSpec constructors

10 years agoFixed signdness detection of expressions with bit- and part-selects
Clifford Wolf [Mon, 28 Jul 2014 08:10:08 +0000 (10:10 +0200)]
Fixed signdness detection of expressions with bit- and part-selects

10 years agoImprovements in tests/vloghtb
Clifford Wolf [Mon, 28 Jul 2014 07:15:40 +0000 (09:15 +0200)]
Improvements in tests/vloghtb

10 years agoAdded techmap -extern
Clifford Wolf [Sun, 27 Jul 2014 19:13:23 +0000 (21:13 +0200)]
Added techmap -extern

10 years agoAdded proper Design->addModule interface
Clifford Wolf [Sun, 27 Jul 2014 19:12:09 +0000 (21:12 +0200)]
Added proper Design->addModule interface

10 years agoAdded topological sorting to techmap
Clifford Wolf [Sun, 27 Jul 2014 14:19:24 +0000 (16:19 +0200)]
Added topological sorting to techmap

10 years agoAdded SigPool::check(bit)
Clifford Wolf [Sun, 27 Jul 2014 13:38:02 +0000 (15:38 +0200)]
Added SigPool::check(bit)

10 years agoSmall improvements in PerformanceTimer API
Clifford Wolf [Sun, 27 Jul 2014 13:14:02 +0000 (15:14 +0200)]
Small improvements in PerformanceTimer API

10 years agoFixed bug in opt_clean
Clifford Wolf [Sun, 27 Jul 2014 13:13:29 +0000 (15:13 +0200)]
Fixed bug in opt_clean

10 years agoImproved performance of opt_const on large modules
Clifford Wolf [Sun, 27 Jul 2014 12:50:25 +0000 (14:50 +0200)]
Improved performance of opt_const on large modules

10 years agoAdded RTLIL::SigSpec::remove_const() handling of packed SigSpecs
Clifford Wolf [Sun, 27 Jul 2014 12:47:48 +0000 (14:47 +0200)]
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs

10 years agoAdded RTLIL::SigSpecConstIterator
Clifford Wolf [Sun, 27 Jul 2014 12:47:23 +0000 (14:47 +0200)]
Added RTLIL::SigSpecConstIterator

10 years agoFixed a bug in opt_clean and some RTLIL API usage cleanups
Clifford Wolf [Sun, 27 Jul 2014 11:19:05 +0000 (13:19 +0200)]
Fixed a bug in opt_clean and some RTLIL API usage cleanups

10 years agoAdded log_cmd_error_expection
Clifford Wolf [Sun, 27 Jul 2014 10:04:12 +0000 (12:04 +0200)]
Added log_cmd_error_expection

10 years agoFixed verific bindings for new RTLIL api
Clifford Wolf [Sun, 27 Jul 2014 10:00:28 +0000 (12:00 +0200)]
Fixed verific bindings for new RTLIL api

10 years agoFixed ilang parser for new RTLIL API
Clifford Wolf [Sun, 27 Jul 2014 09:56:35 +0000 (11:56 +0200)]
Fixed ilang parser for new RTLIL API

10 years agoUsing new obj iterator API in a few places
Clifford Wolf [Sun, 27 Jul 2014 08:41:42 +0000 (10:41 +0200)]
Using new obj iterator API in a few places

10 years agoAdded RTLIL::Module::wire(id) and cell(id) lookup functions
Clifford Wolf [Sun, 27 Jul 2014 09:03:56 +0000 (11:03 +0200)]
Added RTLIL::Module::wire(id) and cell(id) lookup functions

10 years agoAdded RTLIL::Design::modules()
Clifford Wolf [Sun, 27 Jul 2014 08:40:31 +0000 (10:40 +0200)]
Added RTLIL::Design::modules()

10 years agoRefactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf [Sun, 27 Jul 2014 08:18:00 +0000 (10:18 +0200)]
Refactoring: Renamed RTLIL::Design::modules to modules_

10 years agoAdded conversion from ObjRange to std::vector and std::set
Clifford Wolf [Sun, 27 Jul 2014 08:41:06 +0000 (10:41 +0200)]
Added conversion from ObjRange to std::vector and std::set

10 years agoAdded RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf [Sun, 27 Jul 2014 08:13:22 +0000 (10:13 +0200)]
Added RTLIL::ObjIterator and RTLIL::ObjRange