gem5.git
7 years agosim,kvm,arm: fix typos
Curtis Dunham [Tue, 14 Feb 2017 21:09:18 +0000 (15:09 -0600)]
sim,kvm,arm: fix typos

Change-Id: Ifc65d42eebfd109c1c622c82c3c3b3e523819e85
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 years agomem: Update DRAM configuration names
Wendy Elsasser [Tue, 14 Feb 2017 21:09:18 +0000 (15:09 -0600)]
mem: Update DRAM configuration names

Names of DRAM configurations were updated to reflect both
the channel and device data width.

Previous naming format was:
<DEVICE_TYPE>_<DATA_RATE>_<CHANNEL_WIDTH>

The following nomenclature is now used:
<DEVICE_TYPE>_<DATA_RATE>_<n>x<w>
where n = The number of devices per rank on the channel
      x = Device width

Total channel width can be calculated by n*w

Example:
A 64-bit DDR4, 2400 channel consisting of 4-bit devices:
n = 16
w = 4
The resulting configuration name is:
DDR4_2400_16x4

Updated scripts to match new naming convention.

Added unique configurations for DDR4 for:
1) 16x4
2) 8x8
3) 4x16

Change-Id: Ibd7f763b7248835c624309143cb9fc29d56a69d1
Reviewed-by: Radhika Jagtap <radhika.jagtap@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
7 years agotests: check for gem5 binary before tests
Curtis Dunham [Tue, 14 Feb 2017 21:09:18 +0000 (15:09 -0600)]
tests: check for gem5 binary before tests

Provides a helpful error when tests.py is invoked without the gem5 binary.

Before:
Running 0 tests

After:
gem5 binary 'quick/...' not an executable file

Change-Id: I1566802206c9e21ca89bd03e91db22844168a085
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 years agosim: allow forward dependencies in checkpoint upgraders
Curtis Dunham [Tue, 14 Feb 2017 21:09:18 +0000 (15:09 -0600)]
sim: allow forward dependencies in checkpoint upgraders

The notion of forward dependencies is just expressing the same
dependency but at the other end of the dependency edge, i.e. at
the dependee rather than the depender.  As there is no more
'power' here, it's strictly a convenience feature for handling
dependencies with tags that are not in the upstream repository.

Change-Id: Ic7c68de6aff4094aaa12de62cdf690a5dc65ccb5
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 years agosim: add support for checkpoint downgrading
Curtis Dunham [Tue, 14 Feb 2017 21:09:18 +0000 (15:09 -0600)]
sim: add support for checkpoint downgrading

This commit supports the use case of transitioning tags and their
associated checkpoint rewrites out of use for whatever reason.  Just
replace the upgrader() method with a downgrader() method that performs
the appropriate inverse operation.

The tag name is still used, but only in this negative, 'zombie' state,
as it will be removed from the tags in the checkpoint and gem5 binary.

Change-Id: If9d26cccfe8449e026762b1a72f0c2ae5a9cf2d7
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
7 years agoriscv: Remove ECALL tests from insttest
Alec Roelke [Mon, 13 Feb 2017 20:26:05 +0000 (14:26 -0600)]
riscv: Remove ECALL tests from insttest

The system calls tested in rv64i.cpp in RISC-V's insttest suite have
different behavior depending on the operating system and file system they
are run on. This patch ignores the output of those tests and only
ensures that the instructions in RV64I complete successfully.

[Change deletion of ECALL test to block comment.]
[Restore ECALL test but remove test output to test only for completion
without error.]
[Update patch description and again try to push EMPTY files for rv64i
tests.]

7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]
Christian Menard [Mon, 13 Feb 2017 20:25:16 +0000 (14:25 -0600)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [6/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Update the README

7 years agoruby: fix round robin arbiter in garnet2.0
Tushar Krishna [Sun, 12 Feb 2017 20:00:03 +0000 (15:00 -0500)]
ruby: fix round robin arbiter in garnet2.0
The rr arbiter pointer in garnet was getting updated on every request,
even if there is no grant. This was leading to a huge variance in wait
time at a router at high injection rates.
This patch corrects it to update upon a grant.

7 years agomem: fix printing of 1st cache tags line
Bjoern A. Zeeb [Sat, 11 Feb 2017 16:11:48 +0000 (11:11 -0500)]
mem: fix printing of 1st cache tags line

Rather than having the 1st line on the Log line and every other line on its
own, add a new line to have a common format for all of them.  Makes parsing
a lot easier.

Reviewed at http://reviews.gem5.org/r/3808/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agox86: Fix implicit stack addressing in 64-bit mode
Jason Lowe-Power [Fri, 10 Feb 2017 16:19:34 +0000 (11:19 -0500)]
x86: Fix implicit stack addressing in 64-bit mode

When in 64-bit mode, if the stack is accessed implicitly by an instruction
the alternate address prefix should be ignored if present.

This patch adds an extra flag to the ldstop which signifies when the
address override should be ignored. Then, for all of the affected
instructions, this patch adds two options to the ld and st opcode to use
the current stack addressing mode for all addresses and to ignore the
AddressSizeFlagBit.  Finally, this patch updates the x86 TLB to not
truncate the address if it is in 64-bit mode and the IgnoreAddrSizeFlagBit
is set.

This fixes a problem when calling __libc_start_main with a binary that is
linked with a recent version of ld. This version of ld uses the address
override prefix (0x67) on the call instruction instead of a nop.

Note: This has not been tested in compatibility mode and only the call
instruction with the address override prefix has been tested.

See [1] page 9 (pdf page 45)

For instructions that are affected see [1] page 519 (pdf page 555).

[1] http://support.amd.com/TechDocs/24594.pdf

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Update #!env calls for python to explicit version
Jason Lowe-Power [Fri, 10 Feb 2017 15:00:18 +0000 (10:00 -0500)]
misc: Update #!env calls for python to explicit version

In some newer Linux distributions, env python default to Python 3.0. This
patch explicitly uses "python2" instead of just "python" for all scripts
that use #!

Reported-by: Sanchayan Maity <maitysanchayan@gmail.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Add Python.h header to pyevents.hh
Jason Lowe-Power [Fri, 10 Feb 2017 15:00:18 +0000 (10:00 -0500)]
misc: Add Python.h header to pyevents.hh

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]
Christian Menard [Fri, 10 Feb 2017 00:15:51 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [10/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
  * Add callbacks for the Gem5SimControl that are called at before and
  * after simulate()

Reviewed at http://reviews.gem5.org/r/3799/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]
Christian Menard [Fri, 10 Feb 2017 00:15:48 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [9/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
  * Pay for the header delay that the gem5 XBar annotates to packets.

Reviewed at http://reviews.gem5.org/r/3798/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]
Christian Menard [Fri, 10 Feb 2017 00:15:46 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [8/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
  * bugfix: The BEGIN_RESP also needs to be handled when END_REQ was
  * skipped
    and '&trans == blockingRequest && phase == tlm::BEGIN_RESP'
evaluates to true.

Reviewed at http://reviews.gem5.org/r/3797/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]
Christian Menard [Fri, 10 Feb 2017 00:15:43 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [7/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Implement 'pipe through' for gem5 Packets (see explanation below)

Basically, this patch ensures that all transactions that originated in the
gem5 world are converted back to the original packet when entering the gem5
world.  So far, this only worked for packets that are responded to by a
SyctemC component (e.g. when a gem5 CPU sends a request to a SystemC
memory). By implementing the 'pipe through' this patch ensures, that
packets that are responded to by a gem5 component (e.g. when a gem5 CPU
sends a request to a gem5 memory via a SystemC interconnect) are handled
properly.

Reviewed at http://reviews.gem5.org/r/3796/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]
Christian Menard [Fri, 10 Feb 2017 00:15:41 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

Changeset 11798:3a490c57058d
---------------------------
misc: Clean up and complete the gem5<->SystemC-TLM bridge [5/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Introduce transactor modules that represent the gem5 ports in the
 * SystemC world.
 * Update the SimControl module and let it keep track of the gem5 ports.

Reviewed at http://reviews.gem5.org/r/3775/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [4/10]
Christian Menard [Fri, 10 Feb 2017 00:15:38 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [4/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Move common code of the example to a common directory.  Move the cli
 * parsing from the SimControl module to a separate example object.  Add
 * comments describing the Gem5SimControl module.

Testing Done: Examples compile and run.

Reviewed at http://reviews.gem5.org/r/3695/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]
Christian Menard [Fri, 10 Feb 2017 00:15:35 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [3/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Simplify the Slave Port by using a simple_initiator_socket.

Testing Done: Example applications are still running.

Reviewed at http://reviews.gem5.org/r/3686/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]
Christian Menard [Fri, 10 Feb 2017 00:15:33 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [2/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Add the Master Port.  Add an example application that isslustrates its
 * use.

Testing Done: A simple example application consisting of a TLM traffic
generator and a gem5 memory is part of the patch.

Reviewed at http://reviews.gem5.org/r/3528/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]
Christian Menard [Fri, 10 Feb 2017 00:15:30 +0000 (19:15 -0500)]
misc: Clean up and complete the gem5<->SystemC-TLM bridge [1/10]

The current TLM bridge only provides a Slave Port that allows the gem5
world to send request to the SystemC world. This patch series refractors
and cleans up the existing code, and adds a Master Port that allows the
SystemC world to send requests to the gem5 world.

This patch:
 * Restructure the existing sources in preparation of the addition of the
 * new
   Master Port.
 * Refractor names to allow for distinction of the slave and master port.
 * Replace the Makefile by a SConstruct.

Testing Done: The examples provided in util/tlm (now
util/tlm/examples/slave_port) still compile and run error free.

Reviewed at http://reviews.gem5.org/r/3527/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: add a MasterId to the ExternalPort
Christian Menard [Fri, 10 Feb 2017 00:14:58 +0000 (19:14 -0500)]
misc: add a MasterId to the ExternalPort

The Request constructor requires a MasterID. However, an external
transactor has no chance of getting a MasterID as it does not have a
pointer to the System. This patch adds a MasterID to ExternalMaster to
allow external modules to easily genrerate new Requests.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: fix includes in util/systemc
Christian Menard [Fri, 10 Feb 2017 00:11:29 +0000 (19:11 -0500)]
misc: fix includes in util/systemc

This fixes compilation errors with clang on OS X.

Reviewed at http://reviews.gem5.org/r/3807/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Fix order of object construction in the CxxConfigManager
Christian Menard [Fri, 10 Feb 2017 00:11:23 +0000 (19:11 -0500)]
misc: Fix order of object construction in the CxxConfigManager

The CxxConfigManager schould create objects by traversing the object tree
starting from the root object. However, currently objects are created in
aplphabetical order, which only works if the root object alphabetically
comes before any system object (e.g. 'root' < 'system'. Otherwise (e.g.
'a_system' < 'root'), object construction may fail. The reason for this
behaviour is, that the call to findObject() in the sorting code also
constructs the object if it is not yet existent. Then findTraversalOrder()
calls findObject("root") and subseqeuently calls findObject() on all the
children, and so on. However, the call to findTraversalOrder() is
redundant, since all objects are already created in alphabetical order.
This patch simply removes the alphabetical ordering, leading to the objects
being created starting from 'root'.

Reviewed at http://reviews.gem5.org/r/3778/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Implement the Base SystemC Module as an sc_channel.
Christian Menard [Fri, 10 Feb 2017 00:10:25 +0000 (19:10 -0500)]
misc: Implement the Base SystemC Module as an sc_channel.

Implementing the Module as an sc_channel allows derived classes to provide
SystemC interfaces. Other SystemC modules can connect to these interfaces.
This meachanism can be used to control gem5 and acces gem5 components from
within arbitrary SystemC moduels. Since sc_channel is derived from
sc_module, this patch does not break compatibility with existing code.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agosim: fix build breakage in process.cc after brandon@11801
Bjoern A. Zeeb [Fri, 10 Feb 2017 00:03:58 +0000 (19:03 -0500)]
sim: fix build breakage in process.cc after brandon@11801

Seeing build breakage after brandon@11801:

 [     CXX] X86/sim/process.cc -> .o build/X86/sim/process.cc:137:64:
error: field '_pid' is uninitialized when used here
[-Werror,-Wuninitialized] static_cast<PageTableBase *>(new
ArchPageTable(name(), _pid, system)) : ^ build/X86/sim/process.cc:138:64:
error: field '_pid' is uninitialized when used here
[-Werror,-Wuninitialized] static_cast<PageTableBase *>(new
FuncPageTable(name(), _pid))), ^ 2 errors generated.

Testing Done: Compiles now on FreeBSD 10 with clang.

Reviewed at http://reviews.gem5.org/r/3804/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agosim: Patch to fix the statfs build
Bjoern A. Zeeb [Fri, 10 Feb 2017 00:03:55 +0000 (19:03 -0500)]
sim: Patch to fix the statfs build

See developers mailing list.  Trying to unbreak statfs.

Testing Done:
Builds on FreeBSD now.

Reviewed at http://reviews.gem5.org/r/3803/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agoscons: make build better on FreeBSD
Bjoern A. Zeeb [Fri, 10 Feb 2017 00:00:00 +0000 (19:00 -0500)]
scons: make build better on FreeBSD

Various changes we found needed to build gem5 successfully on
FreeBSD.

Reviewed at http://reviews.gem5.org/r/3378/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agodev: net/i8254xGBe add two more wakeup registers to ignore
Bjoern A. Zeeb [Thu, 9 Feb 2017 23:59:55 +0000 (18:59 -0500)]
dev: net/i8254xGBe add two more wakeup registers to ignore

There are drivers writing to WUFC uncondtionally of anything.  In order to
not panic gem5 in these cases, ignore writes to WUFC and WUS as we do for
WUC.  Similarly return 0 (default reset value) on reads.

Testing Done: Booted in FS with such a driver revision which would
previously panic and now boots fine.

Reviewed at http://reviews.gem5.org/r/3791/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agoarm: AArch64 report cache size correctly when reading CTR_EL0
Bjoern A. Zeeb [Thu, 9 Feb 2017 23:54:28 +0000 (18:54 -0500)]
arm: AArch64 report cache size correctly when reading CTR_EL0

Trying to read MISCREG_CTR_EL0 on AArch64 returned 0 as is was not
implmemented.  With that an operating system relying on the cache line
sizes reported in order to manage the caches would (a) panic given the
returned value 0 is not valid (high bit is RES1) or (b) worst case would
assume a cache line size of 4 doing a tremendous amount of extra
instruction work (including fetching).  Return the same values as for ARMv7
as the fields seem to be the same, or RES0/1 seem to be reported
accordingly for AArch64

In collaboration with:  Andrew Turner

Testing Done: Checked on FreeBSD boots with extra printfs;  also observed a
reduction of a factor of about 10 in instruction fetches for a simple
micro-test.

Reviewed at http://reviews.gem5.org/r/3667/

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agostyle: Force Python.h to be included before main header
Andreas Sandberg [Tue, 7 Feb 2017 15:28:33 +0000 (15:28 +0000)]
style: Force Python.h to be included before main header

Python's header files set various compiler macros (e.g.,
_XOPEN_SOURCE) unconditionally. This triggers preprocessor warnings
that end up being treated as errors. The Python integration manual [1]
strongly recommends that Python.h is included before any system
header. The style guide used to mandate that Python.h is included
first in any file that needs it. This requirement was changed to
always include a source file's main header first, which ended up
triggering these errors.

This change updates the style checker to always include Python.h
before the main header file.

[1] https://docs.python.org/2/extending/extending.html

Change-Id: Id6a4f7fc64a336a8fd26691a0ca682abeb1d1579
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Pierre-Yves PĂ©neau <pierre-yves.peneau@lirmm.fr>
7 years agoproto: Fix warnings for protoc v3
Nikos Nikoleris [Fri, 27 Jan 2017 21:07:20 +0000 (15:07 -0600)]
proto: Fix warnings for protoc v3

protoc v3 introduces a new syntax for proto files and warns when the
syntax is not explicitly stated.

protoc relies on the fact that undefined preprocessor symbols are
explanded to 0 but since we use -Wundef they end up generating
warnings.

Change-Id: If07abeb54e932469c8f2c4d38634a97fdae40f77
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agoriscv: Fix crash when syscall argument reg index is too high
Alec Roelke [Fri, 27 Jan 2017 21:05:01 +0000 (15:05 -0600)]
riscv: Fix crash when syscall argument reg index is too high

By default, doSyscall gets the values of six registers to be used for
system call arguments.  RISC-V, by convention, only has four.  Because
RISC-V's implementation of these indices is as arrays of integers rather
than as base indices plus offsets, trying to get the fifth argument
register's value will cause a crash.  This patch fixes that by returning 0
for any index higher than 3.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Add support for switching multiple cores in SystemC
Paul Rosenfeld [Fri, 27 Jan 2017 21:03:17 +0000 (15:03 -0600)]
misc: Add support for switching multiple cores in SystemC

This patch adds a '-n' flag to the gem5 SystemC driver which allows
multiple CPUs to be switched out to a new CPU. Primarily this involves
appending CPU numbers to the objects searched for in the config
manager if there are multiple CPUs in the system.

Note that an equivalent change should be made to the util/cxx_config driver,
but I wanted to get input on this first before making the same change over
there

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomem: Refactor CommMonitor stats, add basic atomic mode stats
Rahul Thakur [Fri, 27 Jan 2017 20:58:16 +0000 (14:58 -0600)]
mem: Refactor CommMonitor stats, add basic atomic mode stats

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomem: Add memory footprint probe
Rahul Thakur [Fri, 27 Jan 2017 20:58:15 +0000 (14:58 -0600)]
mem: Add memory footprint probe

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agopython: Move native wrappers to the _m5 namespace
Andreas Sandberg [Fri, 27 Jan 2017 12:40:01 +0000 (12:40 +0000)]
python: Move native wrappers to the _m5 namespace

Swig wrappers for native objects currently share the _m5.internal name
space with Python code. This is undesirable if we ever want to switch
from Swig to some other framework for native binding (e.g., PyBind11
or Boost::Python). This changeset moves all of such wrappers to the
_m5 namespace, which is now reserved for native code.

Change-Id: I2d2bc12dbc05b57b7c5a75f072e08124413d77f3
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
8 years agosyscall_emul: [patch 4/22] remove redundant M5_pid field from process
Brandon Potter [Wed, 9 Nov 2016 20:27:40 +0000 (14:27 -0600)]
syscall_emul: [patch 4/22] remove redundant M5_pid field from process

8 years agostyle: [patch 3/22] reduce include dependencies in some headers
Brandon Potter [Wed, 9 Nov 2016 20:27:40 +0000 (14:27 -0600)]
style: [patch 3/22] reduce include dependencies in some headers

Used cppclean to help identify useless includes and removed them. This
involved erroneously included headers, but also cases where forward
declarations could have been used rather than a full include.

7 years agosyscall_emul: #ifdef new system calls to allow builds on OSX and BSD
Brandon Potter [Fri, 20 Jan 2017 19:12:58 +0000 (14:12 -0500)]
syscall_emul: #ifdef new system calls to allow builds on OSX and BSD

7 years agoruby: guard usage of GPUCoalescer code in Profiler
Tony Gutierrez [Thu, 19 Jan 2017 16:59:34 +0000 (11:59 -0500)]
ruby: guard usage of GPUCoalescer code in Profiler

the GPUCoalescer code is used in the ruby profiler regardless of
whether or not the coalescer code has been compiled, which can
lead to link/run time errors. here we add #ifdefs to guard the
usage of GPUCoalescer code. eventually we should refactor this
code to use probe points.

7 years agoruby: Check MessageBuffer space in garnet NetworkInterface
Matthew Poremba [Thu, 19 Jan 2017 16:59:10 +0000 (11:59 -0500)]
ruby: Check MessageBuffer space in garnet NetworkInterface

Garnet's NetworkInterface does not consider the size of MessageBuffers when
ejecting a Message from the network. Add a size check for the MessageBuffer
and only enqueue if space is available. If space is not available, the
message if placed in a queue and the credit is held. A callback from the
MessageBuffer is implemented to wake the NetworkInterface. If there are
messages in the stalled queue, they are processed first, in a FIFO manner
and if succesfully ejected, the credit is finally sent back upstream. The
maximum size of the stall queue is equal to the number of valid VNETs
with MessageBuffers attached.

7 years agoruby: Add occupancy stats to MessageBuffers
Matthew Poremba [Thu, 19 Jan 2017 16:58:59 +0000 (11:58 -0500)]
ruby: Add occupancy stats to MessageBuffers

This patch is an updated version of /r/3297.

"The most important statistic for measuring memory hierarchy performance is
throughput, which is affected by independent variables, buffer sizing and
communication latency. It is difficult/impossible to debug performance issues
through series buffers without knowing which are the bottlenecks. For finite
buffers, this patch adds statistics for the average number of messages in the
buffer, the occupancy of the buffer slots, and number of message stalls."

7 years agoruby: Check all VNETs for injection in garnet NetworkInterface
Matthew Poremba [Thu, 19 Jan 2017 16:58:49 +0000 (11:58 -0500)]
ruby: Check all VNETs for injection in garnet NetworkInterface

The NetworkInterface wakeup currently iterates over all VNETs and breaks the
loop if a VNET is unable to allocate a VC. This can cause a deadlock if a
lower numbered VNET is unable to allocate a VC while a higher numbered VNET
has idle VCs. This seems like a bug as Garnet 1.0 uses a while loop over an
if-statement, suggesting the break was intended for this while loop. This
patch removes the break statement, which allows up to one message to be
dequeued from a VNET and injected into the network.

8 years agosyscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc
Brandon Potter [Wed, 9 Nov 2016 20:27:40 +0000 (14:27 -0600)]
syscall_emul: [patch 2/22] move SyscallDesc into its own .hh and .cc

The class was crammed into syscall_emul.hh which has tons of forward
declarations and template definitions. To clean it up a bit, moved the
class into separate files and commented the class with doxygen style
comments. Also, provided some encapsulation by adding some accessors and
a mutator.

The syscallreturn.hh file was renamed syscall_return.hh to make it consistent
with other similarly named files in the src/sim directory.

The DPRINTF_SYSCALL macro was moved into its own header file with the
include the Base and Verbose flags as well.

--HG--
rename : src/sim/syscallreturn.hh => src/sim/syscall_return.hh

8 years agostyle: [patch 1/22] use /r/3648/ to reorganize includes
Brandon Potter [Wed, 9 Nov 2016 20:27:37 +0000 (14:27 -0600)]
style: [patch 1/22] use /r/3648/ to reorganize includes

7 years agomisc: fixes deprecated sc_time function for SystemC 2.3.1
Matthias Jung [Mon, 9 Jan 2017 15:34:36 +0000 (09:34 -0600)]
misc: fixes deprecated sc_time function for SystemC 2.3.1

The non-standard sc_time constructors

- sc_time( uint64, bool scale )
- sc_time( double, bool scale )

have been deprecated in SystemC 2.3.1 and a warning is issued when being
used. Insted the new 'sc_time::from_value' function is used to omit the
warning message.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agomisc: Documentation Update
Matthias Jung [Mon, 9 Jan 2017 15:33:42 +0000 (09:33 -0600)]
misc: Documentation Update

Updates for READMEs of /util/cxx_config, /util/systemc, /util/tlm.
Some minor corrections, mostly with respect to MAC/OSX

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
7 years agoconfig: Fix missing include in fs.py
Matthias Jung [Mon, 9 Jan 2017 15:32:13 +0000 (09:32 -0600)]
config: Fix missing include in fs.py

Bugfix for Elastic Traces

This patch fixes the bug when elastic traces are used:

    build/ARM/gem5.opt \
    configs/example/fs.py \
    --cpu-type=arm_detailed \
    --num-cpu=1 \
    --mem-type=SimpleMemory \
    --mem-size=512MB \
    --mem-channels=1 \
    --caches \
    --elastic-trace-en \
    --data-trace-file=data.proto.gz \
    --inst-trace-file=inst.proto.gz \
    --machine-type=VExpress_EMM \
    --dtb-filename=vexpress.aarch32.ll_20131205.0-gem5.1cpu.dtb \
    --kernel=vmlinux.aarch32.ll_20131205.0-gem5 \
    --disk-image=linux-aarch32-ael.img

NameError: global name 'CpuConfig' is not defined

Signed-off by: Jason Lowe-Power <jason@lowepower.com>

7 years agosim: Remove declaration of unused CountedDrainEvent
Andreas Sandberg [Tue, 3 Jan 2017 17:31:39 +0000 (17:31 +0000)]
sim: Remove declaration of unused CountedDrainEvent

The CountedDrainEvent event was used to keep track of objects that
required additional simulation to drain. It was removed as a part of
the great drain rewrite, but the declaration remained.

Change-Id: I767a3213669040d3f27e2afafa2e4a5bb997e325
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
7 years agopython: Don't use Swig to cast stats
Andreas Sandberg [Tue, 3 Jan 2017 12:03:45 +0000 (12:03 +0000)]
python: Don't use Swig to cast stats

Call the stat visitor from the stat itself rather than casting stats
in Python. This reduces the number of ways visitors are called.

Change-Id: Ic4d0b7b32e3ab9897b9a34cd22d353f4da62d738
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Joe Gross <joseph.gross@amd.com>
7 years agosim: Remove redundant export_method_cxx_predecls
Andreas Sandberg [Tue, 3 Jan 2017 12:03:06 +0000 (12:03 +0000)]
sim: Remove redundant export_method_cxx_predecls

The headers declared in export_method_cxx_predecls are redundant since a
SimObject's main header is automatically included.

Change-Id: Ied9e84630b36960e54efe91d16f8c66fba7e0da0
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Joe Gross <joseph.gross@amd.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
7 years agoutil: Add maintainer tools to create upstream patches
Andreas Sandberg [Tue, 3 Jan 2017 11:31:46 +0000 (11:31 +0000)]
util: Add maintainer tools to create upstream patches

This changeset adds a maintainer script, create_patches.sh, that can
be used to prepare for upstream from a git repository. The script can
be used to generate patches in Mercurial or git format. The commit
messages in the exported patches are all filtered, see
upstream_msg_filter.sed, to ensure that irrelevant meta data isn't
included in the upstream commit.

Kudos to Curtis Dunham and Nikos Nikoleris for reviews and usability
enhancements for earlier versions of this patch.

Change-Id: Ia4cd089a32834b5e046ef58c0a173ca285b77bca
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
8 years agosim: Fix SE mode checkpoint restore file handling
Joel Hestness [Fri, 23 Dec 2016 14:43:18 +0000 (08:43 -0600)]
sim: Fix SE mode checkpoint restore file handling

When restoring from a checkpoint, the simulation used to use file handles from
the checkpoint. This disallows multiple separate restore simulations from using
separate input and output files and directories, and plays havoc when the
checkpointed file locations may have changed. Add handling to allow the command
line specified files to be used as input/output for the restored simulation
(Note: this is the similar functionality to FS mode for output and error).

8 years agocpu: implement an L-TAGE branch predictor
Arthur Perais [Wed, 21 Dec 2016 21:25:13 +0000 (15:25 -0600)]
cpu: implement an L-TAGE branch predictor

This patch implements an L-TAGE predictor, based on AndrĂ© Seznec's code
available from CBP-2
(http://hpca23.cse.tamu.edu/taco/camino/cbp2/cbp-src/realistic-seznec.h).

Signed-off-by Jason Lowe-Power <jason@lowepower.com>

8 years agocpu: disallow speculative update of branch predictor tables (o3)
Arthur Perais [Wed, 21 Dec 2016 21:07:16 +0000 (15:07 -0600)]
cpu: disallow speculative update of branch predictor tables (o3)

The Minor and o3 cpu models share the branch prediction
code. Minor relies on the BPredUnit::squash() function
to update the branch predictor tables on a branch mispre-
diction. This is fine because Minor executes in-order, so
the update is on the correct path. However, this causes the
branch predictor to be updated on out-of-order branch
mispredictions when using the o3 model, which should not
be the case.

This patch guards against speculative update of the branch
prediction tables. On a branch misprediction, BPredUnit::squash()
calls BpredUnit::update(..., squashed = true). The underlying
branch predictor tests against the value of squashed. If it is
true, it restores any speculatively updated internal state
it might have (e.g., global/local branch history), then returns.
If false, it updates its prediction tables. Previously, exist-
ing predictors did not test against the "squashed" parameter.

To accomodate for this change, the Minor model must now call
BPredUnit::squash() then BPredUnit::update(..., squashed = false)
on branch mispredictions. Before, calling BpredUnit::squash()
performed the prediction tables update.

The effect is a slight MPKI improvement when using the o3
model. A further patch should perform the same modifications
for the indirect target predictor and BTB (less critical).

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
8 years agocpu: correct comments in tournament branch predictor
Arthur Perais [Wed, 21 Dec 2016 21:06:13 +0000 (15:06 -0600)]
cpu: correct comments in tournament branch predictor

The tournament predictor is presented as doing speculative
update of the global history and non-speculative update
of the local history used to generate the branch prediction.
However, the code does speculative update of both histories.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
8 years agocpu: Resolve targets of predicted 'taken' decode for O3
Arthur Perais [Wed, 21 Dec 2016 21:05:24 +0000 (15:05 -0600)]
cpu: Resolve targets of predicted 'taken' decode for O3

The target of taken conditional direct branches does not
need to be resolved in IEW: the target can be computed at
decode, usually using the decoded instruction word and the PC.

The higher-than-necessary penalty is taken only on conditional
branches that are predicted taken but miss in the BTB. Thus,
this is mostly inconsequential on IPC if the BTB is big/associative
enough (fewer capacity/conflict misses). Nonetheless, what gem5
simulates is not representative of how conditional branch targets
can be handled.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
8 years agocpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3
Arthur Perais [Wed, 21 Dec 2016 21:04:06 +0000 (15:04 -0600)]
cpu: Clarify meaning of cachePorts variable in lsq_unit.hh of O3

cachePorts currently constrains the number of store packets written to the
D-Cache each cycle), but loads currently affect this variable. This leads
to unexpected congestion (e.g., setting cachePorts to a realistic 1 will
in fact allow a store to WB only if no loads have accessed the D-Cache
this cycle). In the absence of arbitration, this patch decouples how many
loads can be done per cycle from how many stores can be done per cycle.

Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
8 years agoruby: Make MessageBuffers actually finite sized
Joel Hestness [Tue, 20 Dec 2016 17:38:24 +0000 (11:38 -0600)]
ruby: Make MessageBuffers actually finite sized

When Ruby controllers stall messages in MessageBuffers, the buffer moves those
messages off the priority heap and into a per-address stall map. When buffers
are finite-sized, the test areNSlotsAvailable() only checks the size of the
priority heap, but ignores the stall map, so the map is allowed to grow
unbounded if the controller stalls numerous messages. This patch fixes the
problem by tracking the stall map size and testing the total number of messages
in the buffer appropriately.

8 years agoruby: fix typo in DMASequencer::ackCallback()
Tony Gutierrez [Tue, 20 Dec 2016 16:53:36 +0000 (11:53 -0500)]
ruby: fix typo in DMASequencer::ackCallback()

8 years agoruby: fix issue with unused var in DMASequencer
Tony Gutierrez [Tue, 20 Dec 2016 16:47:30 +0000 (11:47 -0500)]
ruby: fix issue with unused var in DMASequencer

the iterator declared in DMASequencer::ackCallback() is only used in an
assert, this causes clang to fail when building fast. here we move
the find call on the request table directly into the assert.

8 years agodist, dev: fix etherswitch upgrade script
Curtis Dunham [Mon, 19 Dec 2016 18:12:28 +0000 (12:12 -0600)]
dist, dev: fix etherswitch upgrade script

The aforementioned upgrader in [1] assumes every option in [system]
has a delimiting '.', and also seems to do its rewriting work a bit too
unconditionally.  Most checkpoints in the wild don't have this device,
in which case this script should be a safe no-op.

[1] 2aa4d7b  dist, dev: Fixed the packet ordering in etherswitch

Change-Id: Icfd0350985109df1628eb9ab864cda42c54060a8
Reviewed-by: Gabor Dozsa <gabor.dozsa@arm.com>
8 years agostats: update references
Curtis Dunham [Mon, 19 Dec 2016 17:03:28 +0000 (11:03 -0600)]
stats: update references

8 years agoarm: provide correct timer availability in ID_PFR1 register
Curtis Dunham [Mon, 19 Dec 2016 17:03:28 +0000 (11:03 -0600)]
arm: provide correct timer availability in ID_PFR1 register

Change-Id: Id4cd839c12b70616017a5830e3f9bbb59b0f97ba
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: compute ID_AA64PFR{0,1}_EL1 registers
Curtis Dunham [Mon, 19 Dec 2016 17:03:28 +0000 (11:03 -0600)]
arm: compute ID_AA64PFR{0,1}_EL1 registers

Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.

Change-Id: If9774b6610a29568b80ae4866107b9a6a5b5be0f
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: compute ID_PFR{0,1} registers
Curtis Dunham [Mon, 19 Dec 2016 17:03:27 +0000 (11:03 -0600)]
arm: compute ID_PFR{0,1} registers

Compute the proper values of the aforementioned registers from
the system configuration rather than configuring the values themselves.

Change-Id: Ie7685b5d8b5f2dd9d6380b4af74f16d596b2bfd1
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: miscreg refactoring
Curtis Dunham [Mon, 19 Dec 2016 17:03:27 +0000 (11:03 -0600)]
arm: miscreg refactoring

Change-Id: I4e9e8f264a4a4239dd135a6c7a1c8da213b6d345
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: audit SCTLR
Curtis Dunham [Mon, 19 Dec 2016 17:03:27 +0000 (11:03 -0600)]
arm: audit SCTLR

Change-Id: I814f1431a5f754f75721c9ac51171f860a714d24
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: remove SCTLR.FI
Curtis Dunham [Mon, 19 Dec 2016 17:03:27 +0000 (11:03 -0600)]
arm: remove SCTLR.FI

Removed from ARMARM.

Change-Id: Ie8f28e4fa6e1b46dfd9c8c4b379e5b42fe25421d
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm: update AArch{64,32} register mappings
Curtis Dunham [Mon, 19 Dec 2016 17:03:27 +0000 (11:03 -0600)]
arm: update AArch{64,32} register mappings

Change-Id: Idaaaeb3f7b1a0bdbf18d8e2d46686c78bb411317
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agomem: Make the BaseXBar public to not confuse Python wrappers
Andreas Sandberg [Mon, 19 Dec 2016 16:25:40 +0000 (16:25 +0000)]
mem: Make the BaseXBar public to not confuse Python wrappers

The Python wrappers generally assume that destructors are public. Make
the BaseXBar destructor public to avoid confusing the Python wrapper.

Change-Id: If958802409c0be74e875dd6e279742abfdb3ede1
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agopython: Export periodicStatDump
Andreas Sandberg [Mon, 19 Dec 2016 16:25:39 +0000 (16:25 +0000)]
python: Export periodicStatDump

Some configuration scripts need periodic stat dumps. One of the ways
this can be achieved is by using the pariodicStatDump helper
function. This function was previously only exported in the internal
name space. Export it as a normal function in m5.stat instead.

Change-Id: Ic88bf1fd33042a62ab436d5944d8ed778264ac98
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
8 years agodev: Include DmaDevice in NULL builds
Andreas Sandberg [Mon, 19 Dec 2016 16:25:38 +0000 (16:25 +0000)]
dev: Include DmaDevice in NULL builds

Builds for the NULL ISA include Device.py, which contains the Python
declaration of DmaDevice, but don't include the actual C++
implementation. Add dma_device.cc to the NULL build to the Python and
C++ worlds consistent again.

Change-Id: I47a57181a1f4d5a7276467678bf16fbc7f161681
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
8 years agopython: Fix incorrect header in the DmaDevice wrapper
Andreas Sandberg [Mon, 19 Dec 2016 16:25:38 +0000 (16:25 +0000)]
python: Fix incorrect header in the DmaDevice wrapper

The header declared in the DmaDevice wrapper doesn't actually contain
the DmaDevice class. This can potentially lead to incorrect type cases
in Swig.

Change-Id: If2266d4180d1d6fd13359a81067068854c5e96fe
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Sascha Bischoff <sascha.bischoff@arm.com>
8 years agosim: Remove redundant buildEnv import
Andreas Sandberg [Mon, 19 Dec 2016 16:25:37 +0000 (16:25 +0000)]
sim: Remove redundant buildEnv import

Change-Id: Id6bdbc0c988aa92b96e292cabc913e6b974f14bb
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-by: Curtis Dunham <curtis.dunham@arm.com>
8 years agoruby: Detect garnet network-level deadlock.
Jieming Yin [Thu, 15 Dec 2016 21:59:17 +0000 (16:59 -0500)]
ruby: Detect garnet network-level deadlock.

This patch detects garnet network deadlock by monitoring
network interfaces. If a network interface continuously
fails to allocate virtual channels for a message, a
possible deadlock is detected.

8 years agobase: remove header file to prevent a macro name collision
Brandon Potter [Wed, 9 Nov 2016 20:27:37 +0000 (14:27 -0600)]
base: remove header file to prevent a macro name collision

8 years agosyscall_emul: implement fallocate
Brandon Potter [Thu, 15 Dec 2016 18:16:25 +0000 (13:16 -0500)]
syscall_emul: implement fallocate

8 years agosyscall_emul: add support for x86 statfs system calls
Brandon Potter [Thu, 15 Dec 2016 18:16:03 +0000 (13:16 -0500)]
syscall_emul: add support for x86 statfs system calls

8 years agosyscall_emul: extend sysinfo system call to include mem_unit
Brandon Potter [Thu, 15 Dec 2016 18:14:41 +0000 (13:14 -0500)]
syscall_emul: extend sysinfo system call to include mem_unit

8 years agodev: Fix race conditions at terminating dist-gem5 simulations
Gabor Dozsa [Tue, 6 Dec 2016 17:33:06 +0000 (17:33 +0000)]
dev: Fix race conditions at terminating dist-gem5 simulations

Two problems may arise when a distributed gem5 simulation terminates:
(i) simulation thread(s) may get stuck in an incomplete synchronisation
event which prohibits processing  the simulation exit event; and (ii) a
stale receiver thread may try to access objects that have already been
deleted while exiting gem5. This patch terminates receive threads properly
and aborts the processing of any incomplete synchronisation event.

Change-Id: I72337aa12c7926cece00309640d478b61e55a429
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoarm, config: Add missing IOCache in bL config
Gabor Dozsa [Tue, 6 Dec 2016 17:10:36 +0000 (17:10 +0000)]
arm, config: Add missing IOCache in bL config

This patch adds an IOCache to the example bigLITTLE
configuration. An IOCache is required for correct DMA
transfers when we have caches in the system.

Change-Id: Ifeddc1b360aacbb16b1393f361dd98873c834012
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
8 years agoruby: Remove RubyMemoryControl and associated files
Andreas Hansson [Mon, 5 Dec 2016 21:49:07 +0000 (16:49 -0500)]
ruby: Remove RubyMemoryControl and associated files

This patch removes the deprecated RubyMemoryControl. The DRAMCtrl
module should be used instead.

8 years agostats: Update stats to reflect cache changes
Andreas Hansson [Mon, 5 Dec 2016 21:48:34 +0000 (16:48 -0500)]
stats: Update stats to reflect cache changes

8 years agoconfig: Add an option to generate a random topology in memcheck
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:31 +0000 (16:48 -0500)]
config: Add an option to generate a random topology in memcheck

This change adds the option to use the memcheck with random memory
hierarchies at the moment limited to a maximum depth of 3 allowing
testing with uncommon topologies.

Change-Id: Id2c2fe82a8175d9a67eb4cd7f3d2e2720a809b60
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agoconfig: Add whole line accesses to improve memchecker's coverage
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:30 +0000 (16:48 -0500)]
config: Add whole line accesses to improve memchecker's coverage

Change-Id: Ie1a047139e350ce7400f3a20be644eaff1e21428
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agomem: Respond to InvalidateReq when the block is (pending) dirty
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:29 +0000 (16:48 -0500)]
mem: Respond to InvalidateReq when the block is (pending) dirty

Previously when an InvalidateReq snooped a cache with a dirty block or
a pending modified MSHR, it would invalidate the block or set the
postInv flag. The cache would not send an InvalidateResp. though,
causing memory order violations. This patches changes this behavior,
making the cache with the dirty block or pending modified MSHR the
ordering point.

Change-Id: Ib4c31012f4f6693ffb137cd77258b160fbc239ca
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agomem: Invalidate a blk when servicing the 1st invalidating target
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:28 +0000 (16:48 -0500)]
mem: Invalidate a blk when servicing the 1st invalidating target

Previously an MSHR with one or more invalidating targets would first
service all targets in the MSHR TargetList and then invalidate the
block. As a result any service snooping targets would lookup in the
cache and incorrectly find the block. This patch forces the
invalidation to happen when the first invalidating target is
encountered.

Change-Id: I9df15de24e1d351cd96f5a2c424d9a03d81c2cce
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agomem: Allow non invalidating snoops on an InvalidateReq MSHR
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:27 +0000 (16:48 -0500)]
mem: Allow non invalidating snoops on an InvalidateReq MSHR

This patch changes an assertion that previously assumed that a non
invalidating snoop request should never be serviced by an
InvalidateReq MSHR. The MSHR serves as the ordering point for the
snooping packet. When the InvalidateResp reaches the cache the
snooping packet snoops the caches above to find the requested
block. One or more of the caches above will have the block since
earlier it has seen a WriteLineReq.

Change-Id: I0c147c8b5d5019e18bd34adf9af0fccfe431ae07
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agomem: Don't use hasSharers in the snoopFilter for memory responses
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:26 +0000 (16:48 -0500)]
mem: Don't use hasSharers in the snoopFilter for memory responses

When the snoopFilter receives a response, it updates its state using
the hasSharers flag (indicates whether there are more than one copies
of the block in the caches above). The hasSharers flag of the packet
was previously populated when the request was traversing and snooping
the caches looking for the block.
1) When the response is coming from the memory-side port, its order
with respect to other responses is not necessarily preserved (e.g., a
request that arrived second to the xbar can get its response first). As
a result the snoopFilter might process responses out of order updating
its residency information using the non valid hasSharers flag which was
populated much earlier.
2) When the response is from an on-chip, the MSHRs preserve a well
defined order and the hasSharers flag should contain valid
information.

This patch changes the snoopFilter by avoiding the hasSharers flag
when the response is from the memory-side port.

Change-Id: Ib2d22a5b7bf3eccac64445127d2ea20ee74bb25b
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Always use InvalidateReq to service WriteLineReq misses
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:25 +0000 (16:48 -0500)]
mem: Always use InvalidateReq to service WriteLineReq misses

Previously, a WriteLineReq that missed in a cache would send out an
InvalidateReq if the block lookup failed or an UpgradeReq if the
block lookup succeeded but the block had sharers. This changes ensures
that a WriteLineReq always sends an InvalidateReq to invalidate all
copies of the block and satisfy the WriteLineReq.

Change-Id: I207ff5b267663abf02bc0b08aeadde69ad81be61
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
8 years agomem: Assert that the responderHadWritable is set only once
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:24 +0000 (16:48 -0500)]
mem: Assert that the responderHadWritable is set only once

Change-Id: Ie3beeef25331f84a0a5bcc17f7a791f4a829695b
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Ensure InvalidateReq is considered isForward by MSHRs
Andreas Hansson [Mon, 5 Dec 2016 21:48:23 +0000 (16:48 -0500)]
mem: Ensure InvalidateReq is considered isForward by MSHRs

This patch fixes an issue where an MSHR would incorrectly be perceived
to provide data to targets arriving after an InvalidateReq. To address
this the InvalidateReq is now treated as isForward, much like an
UpgradeReq that did not hit in the cache.

Change-Id: Ia878444d949539b5c33fd19f3e12b0b8a872275e
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Make packet debug printing more uniform
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:21 +0000 (16:48 -0500)]
mem: Make packet debug printing more uniform

Previously DPRINTFs printing information about a packet would use ad hoc
formats. This patch changes all DPRINTFs to use the print function
defined by the packet class, making the packet printing format more
uniform and easier to change.

Change-Id: Idd436a9758d4bf70c86a574d524648b2a2580970
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agocpu: Change traffic generators to use different values for writes
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:20 +0000 (16:48 -0500)]
cpu: Change traffic generators to use different values for writes

Previously all traffic generators would use the same value for write
requests. With this change traffic generators use their master id as
the payload of write requests making them more useful for the
memchecker.

Change-Id: Id1a6b8f02853789b108ef6003f4c32ab929bb123
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Service only the 1st FromCPU MSHR target on ReadRespWithInv
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:19 +0000 (16:48 -0500)]
mem: Service only the 1st FromCPU MSHR target on ReadRespWithInv

A response to a ReadReq can either be a ReadResp or a
ReadRespWithInvalidate. As we add targets to an MSHR for a ReadReq we
assume that the response will be a ReadResp. When the response is
invalidating (ReadRespWithInvalidate) servicing more than one targets
can potentially violate the memory ordering. This change fixes the way
we handle a ReadRespWithInvalidate. When a cache receives a
ReadRespWithInvalidate we service only the first FromCPU target and
all the FromSnoop targets from the MSHR target list. The rest of the
FromCPU targets are deferred and serviced by a new request.

Change-Id: I75c30c268851987ee5f8644acb46f440b4eeeec2
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Keep track of allocOnFill in the TargetList
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:18 +0000 (16:48 -0500)]
mem: Keep track of allocOnFill in the TargetList

Previously the information of whether a response was allocating or not
was a property of the MSHR. This change makes this flag a property of
the TargetList. Differernt TargetLists, e.g. the targets and the
deferred targets lists might have different values. Additionally, the
information about whether each of the target expects an allocating
response is stored inside the TargetList container. This allows for
repopulating the flag in case some of the targets are removed.

Change-Id: If3ec2516992f42a6d9da907009ffe3ab8d0d2021
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agomem: Add support for repopulating the flags of an MSHR TargetList
Nikos Nikoleris [Mon, 5 Dec 2016 21:48:17 +0000 (16:48 -0500)]
mem: Add support for repopulating the flags of an MSHR TargetList

This patch adds support for repopulating the flags of an MSHR
TargetList. The added functionality makes it possible to remove
targets from a TargetList without leaving it in an inconsistent state.

Change-Id: I3f7a8e97bfd3e2e49bebad056d11bbfb087aad91
Reviewed-by: Andreas Hansson <andreas.hansson@arm.com>
Reviewed-by: Stephan Diestelhorst <stephan.diestelhorst@arm.com>
8 years agohsail: disable asserts to allow immediate operands i.e. 0 with loads
Brandon Potter [Fri, 2 Dec 2016 23:01:58 +0000 (18:01 -0500)]
hsail: disable asserts to allow immediate operands i.e. 0 with loads