Sebastien Bourdeauducq [Sun, 18 Mar 2012 21:12:46 +0000 (22:12 +0100)]
corelogic/fsm: typo
Sebastien Bourdeauducq [Sat, 17 Mar 2012 23:09:40 +0000 (00:09 +0100)]
corelogic/fsm: delayed enters
Sebastien Bourdeauducq [Fri, 16 Mar 2012 15:54:47 +0000 (16:54 +0100)]
corelogic/roundrobin: CE switching
Sebastien Bourdeauducq [Thu, 15 Mar 2012 19:25:44 +0000 (20:25 +0100)]
corelogic: convert timeline to function and move to misc
Sebastien Bourdeauducq [Wed, 14 Mar 2012 15:19:29 +0000 (16:19 +0100)]
bus/asmibus/hub: require finalization before get_slots
Sebastien Bourdeauducq [Wed, 14 Mar 2012 11:19:42 +0000 (12:19 +0100)]
fhdl: export log2_int
Alain Péteut [Sat, 10 Mar 2012 19:01:14 +0000 (20:01 +0100)]
setup.py: simplify
Signed-off-by: Alain Péteut <alain.peteut@yahoo.com>
Sebastien Bourdeauducq [Sat, 10 Mar 2012 18:38:39 +0000 (19:38 +0100)]
doc: more examples and comments
Sebastien Bourdeauducq [Sat, 10 Mar 2012 16:59:42 +0000 (17:59 +0100)]
doc: cosmetic changes (thanks sh4rm4 for reporting typos)
Sebastien Bourdeauducq [Fri, 9 Mar 2012 20:57:50 +0000 (21:57 +0100)]
doc: use script font
Sebastien Bourdeauducq [Fri, 9 Mar 2012 20:17:21 +0000 (21:17 +0100)]
doc: simulation
Sebastien Bourdeauducq [Fri, 9 Mar 2012 17:26:00 +0000 (18:26 +0100)]
doc: cosmetic changes (thanks rofl0r for reporting typos)
Sebastien Bourdeauducq [Fri, 9 Mar 2012 16:16:33 +0000 (17:16 +0100)]
doc: add logo
Sebastien Bourdeauducq [Fri, 9 Mar 2012 16:08:38 +0000 (17:08 +0100)]
doc: switch to sphinx
Sebastien Bourdeauducq [Thu, 8 Mar 2012 19:49:36 +0000 (20:49 +0100)]
examples: FIR filter simulation
Sebastien Bourdeauducq [Thu, 8 Mar 2012 19:49:24 +0000 (20:49 +0100)]
fhdl: handle negative constants correctly
Sebastien Bourdeauducq [Thu, 8 Mar 2012 17:17:56 +0000 (18:17 +0100)]
examples: remove outdated wb_intercon simulation
Sebastien Bourdeauducq [Thu, 8 Mar 2012 17:14:40 +0000 (18:14 +0100)]
vpi: support extra include directories
Sebastien Bourdeauducq [Thu, 8 Mar 2012 17:14:19 +0000 (18:14 +0100)]
gitignore: update
Sebastien Bourdeauducq [Thu, 8 Mar 2012 17:14:06 +0000 (18:14 +0100)]
bus: generic transaction model
Sebastien Bourdeauducq [Thu, 8 Mar 2012 16:27:59 +0000 (17:27 +0100)]
vpi: patch for Icarus Verilog
Sebastien Bourdeauducq [Thu, 8 Mar 2012 14:55:02 +0000 (15:55 +0100)]
examples: small cleanup
Sebastien Bourdeauducq [Thu, 8 Mar 2012 14:34:08 +0000 (15:34 +0100)]
sim: fix zero encoding
Sebastien Bourdeauducq [Thu, 8 Mar 2012 14:27:35 +0000 (15:27 +0100)]
sim: fix message debug formatting
Sebastien Bourdeauducq [Tue, 6 Mar 2012 18:43:59 +0000 (19:43 +0100)]
sim: make initialization cycle optional (selectable by function attribute)
Sebastien Bourdeauducq [Tue, 6 Mar 2012 18:29:39 +0000 (19:29 +0100)]
sim: memory access
Sebastien Bourdeauducq [Tue, 6 Mar 2012 17:33:44 +0000 (18:33 +0100)]
fhdl: register memory objects with namespace
Sebastien Bourdeauducq [Tue, 6 Mar 2012 15:46:18 +0000 (16:46 +0100)]
sim: support for signed numbers
Sebastien Bourdeauducq [Tue, 6 Mar 2012 15:45:44 +0000 (16:45 +0100)]
fhdl/verilog: fix signed constant conversion
Sebastien Bourdeauducq [Tue, 6 Mar 2012 14:51:09 +0000 (15:51 +0100)]
vpi: install target
Sebastien Bourdeauducq [Tue, 6 Mar 2012 14:26:04 +0000 (15:26 +0100)]
sim: VCD generation
Sebastien Bourdeauducq [Tue, 6 Mar 2012 14:00:02 +0000 (15:00 +0100)]
sim: clean startup/shutdown
Sebastien Bourdeauducq [Tue, 6 Mar 2012 13:20:26 +0000 (14:20 +0100)]
sim: remove temporary files and socket
Sebastien Bourdeauducq [Tue, 6 Mar 2012 13:18:22 +0000 (14:18 +0100)]
fhdl/namer: do not reference objects with __del__ methods to avoid uncollectable cycles
Sebastien Bourdeauducq [Tue, 6 Mar 2012 12:58:49 +0000 (13:58 +0100)]
sim: remove default sockaddr
Sebastien Bourdeauducq [Tue, 6 Mar 2012 12:58:22 +0000 (13:58 +0100)]
fhdl: add simulation functions in fragment
Sebastien Bourdeauducq [Mon, 5 Mar 2012 19:31:41 +0000 (20:31 +0100)]
sim: basic functionality working
Sebastien Bourdeauducq [Mon, 5 Mar 2012 14:40:21 +0000 (15:40 +0100)]
sim: signal writes working
Sebastien Bourdeauducq [Sun, 4 Mar 2012 21:56:56 +0000 (22:56 +0100)]
sim: cleanups
Sebastien Bourdeauducq [Sun, 4 Mar 2012 21:33:03 +0000 (22:33 +0100)]
sim: signal reads working
Sebastien Bourdeauducq [Sun, 4 Mar 2012 20:27:02 +0000 (21:27 +0100)]
sim: compile VPI module
Sebastien Bourdeauducq [Sun, 4 Mar 2012 18:17:03 +0000 (19:17 +0100)]
sim: two way IPC working
Sebastien Bourdeauducq [Sat, 3 Mar 2012 17:55:38 +0000 (18:55 +0100)]
sim: IPC module (lacks str/int encoding)
Sebastien Bourdeauducq [Wed, 29 Feb 2012 19:30:08 +0000 (20:30 +0100)]
README: clarify license
Sebastien Bourdeauducq [Sun, 19 Feb 2012 16:57:04 +0000 (17:57 +0100)]
bus/dfi: fix multiphase naming
Sebastien Bourdeauducq [Sat, 18 Feb 2012 17:56:18 +0000 (18:56 +0100)]
bank/csrgen: fix RE generation
Sebastien Bourdeauducq [Fri, 17 Feb 2012 22:52:06 +0000 (23:52 +0100)]
bank: add RE signal for registers made of fields
Sebastien Bourdeauducq [Fri, 17 Feb 2012 22:51:32 +0000 (23:51 +0100)]
bus: add interconnect statements function
Sebastien Bourdeauducq [Fri, 17 Feb 2012 22:50:54 +0000 (23:50 +0100)]
fhdl: check we pass BV to signals
Sebastien Bourdeauducq [Fri, 17 Feb 2012 10:08:41 +0000 (11:08 +0100)]
fhdl/verilog: properly connect instance inouts
Sebastien Bourdeauducq [Thu, 16 Feb 2012 17:34:32 +0000 (18:34 +0100)]
fhdl: support forwarding of bidirectional signals from instance ports
Sebastien Bourdeauducq [Wed, 15 Feb 2012 20:48:05 +0000 (21:48 +0100)]
bus/dfi: filter signals by direction
Sebastien Bourdeauducq [Wed, 15 Feb 2012 17:23:31 +0000 (18:23 +0100)]
bank: omit device write register when access_bus==READ_ONLY and access_dev==WRITE_ONLY
Sebastien Bourdeauducq [Wed, 15 Feb 2012 17:09:14 +0000 (18:09 +0100)]
bus: add DFI
Sebastien Bourdeauducq [Wed, 15 Feb 2012 15:42:17 +0000 (16:42 +0100)]
bank/csrgen: use new bus API
Sebastien Bourdeauducq [Wed, 15 Feb 2012 15:42:05 +0000 (16:42 +0100)]
bus: fix simple interconnect
Sebastien Bourdeauducq [Wed, 15 Feb 2012 15:30:16 +0000 (16:30 +0100)]
bus: simplify and cleanup
Unify slave and master interfaces
Remove signal direction suffixes
Generic simple interconnect
Wishbone point-to-point interconnect
Description filter (get_name)
Misc cleanups
Sebastien Bourdeauducq [Tue, 14 Feb 2012 13:00:17 +0000 (14:00 +0100)]
bus/asmibus/hub: forward data and tag_call
Sebastien Bourdeauducq [Tue, 14 Feb 2012 12:12:43 +0000 (13:12 +0100)]
Use double quotes for all strings
Sebastien Bourdeauducq [Mon, 13 Feb 2012 22:11:16 +0000 (23:11 +0100)]
bus/wishbone2asmi: cache hits working
Sebastien Bourdeauducq [Mon, 13 Feb 2012 22:10:27 +0000 (23:10 +0100)]
corelogic: support reverse in displacer/chooser
Sebastien Bourdeauducq [Mon, 13 Feb 2012 21:28:02 +0000 (22:28 +0100)]
Fix syntax errors and other stupid problems
Sebastien Bourdeauducq [Mon, 13 Feb 2012 20:46:39 +0000 (21:46 +0100)]
bus/csr: Rename a->adr d->dat to be consistent with the other buses
Sebastien Bourdeauducq [Mon, 13 Feb 2012 16:23:32 +0000 (17:23 +0100)]
doc: update ASMI description
Sebastien Bourdeauducq [Mon, 13 Feb 2012 15:49:43 +0000 (16:49 +0100)]
bus/wishbone2asmi: set WM, and send 0 when inactive
Sebastien Bourdeauducq [Mon, 13 Feb 2012 15:29:38 +0000 (16:29 +0100)]
bus: Wishbone to ASMI caching bridge (untested)
Sebastien Bourdeauducq [Sat, 11 Feb 2012 19:57:08 +0000 (20:57 +0100)]
corelogic/misc: displacer + chooser
Sebastien Bourdeauducq [Sat, 11 Feb 2012 19:56:51 +0000 (20:56 +0100)]
corelogic/misc/multimux: less confusing variable name
Sebastien Bourdeauducq [Sat, 11 Feb 2012 19:56:01 +0000 (20:56 +0100)]
bus/asmibus: fix typo
Sebastien Bourdeauducq [Sat, 11 Feb 2012 19:55:23 +0000 (20:55 +0100)]
corelogic/record: add to_signal convenience function
Sebastien Bourdeauducq [Sat, 11 Feb 2012 10:52:15 +0000 (11:52 +0100)]
corelogic/misc: contiguous split
Sebastien Bourdeauducq [Fri, 10 Feb 2012 16:49:06 +0000 (17:49 +0100)]
bus/asmibus: add get_slots, fix get_fragment
Sebastien Bourdeauducq [Fri, 10 Feb 2012 14:21:04 +0000 (15:21 +0100)]
bus: ASMI hub (untested)
Sebastien Bourdeauducq [Wed, 8 Feb 2012 18:26:56 +0000 (19:26 +0100)]
doc: update Bank description
Sebastien Bourdeauducq [Mon, 6 Feb 2012 17:43:34 +0000 (18:43 +0100)]
bus/wishbone2csr: truncate WB data
Sebastien Bourdeauducq [Mon, 6 Feb 2012 17:07:02 +0000 (18:07 +0100)]
fhdl: do not attempt slicing non-array signals to keep Verilog happy
Sebastien Bourdeauducq [Mon, 6 Feb 2012 16:39:32 +0000 (17:39 +0100)]
bank: event manager
Sebastien Bourdeauducq [Mon, 6 Feb 2012 15:15:27 +0000 (16:15 +0100)]
bank: support registers larger than the bus word width
Sebastien Bourdeauducq [Mon, 6 Feb 2012 12:55:50 +0000 (13:55 +0100)]
bank: refactoring
Sebastien Bourdeauducq [Mon, 6 Feb 2012 10:18:30 +0000 (11:18 +0100)]
bank/csrgen: use enumerate
Sebastien Bourdeauducq [Sun, 5 Feb 2012 18:32:11 +0000 (19:32 +0100)]
fhdl/structure: binary constant builder
Sébastien Bourdeauducq [Fri, 3 Feb 2012 09:25:38 +0000 (01:25 -0800)]
Merge pull request #2 from larsclausen/master
migen patches
Lars-Peter Clausen [Thu, 2 Feb 2012 20:12:37 +0000 (21:12 +0100)]
Use enumerate(x) instead of zip(range(x), x)
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen [Tue, 31 Jan 2012 20:39:53 +0000 (21:39 +0100)]
fhdl/namer: Add support for STORE_DEREF opcode
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Lars-Peter Clausen [Tue, 31 Jan 2012 20:46:08 +0000 (21:46 +0100)]
Lower required python version to 3.1
migen is confirmed to work fine with python 3.1, so lower the required version
from 3.2 to 3.1.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Sebastien Bourdeauducq [Sat, 28 Jan 2012 22:18:21 +0000 (23:18 +0100)]
examples/wb_intercon: update to new APIs
Sebastien Bourdeauducq [Sat, 28 Jan 2012 22:17:44 +0000 (23:17 +0100)]
fhdl/namer: extract variable names with bytecode inspection
Sebastien Bourdeauducq [Sat, 28 Jan 2012 10:39:28 +0000 (11:39 +0100)]
fhdl: do not prefix instance signal names
Sebastien Bourdeauducq [Fri, 27 Jan 2012 21:20:57 +0000 (22:20 +0100)]
Remove explicit bus names and rely on the new automatic namer
Sebastien Bourdeauducq [Fri, 27 Jan 2012 20:39:23 +0000 (21:39 +0100)]
fhdl: support memory read enable
Sebastien Bourdeauducq [Fri, 27 Jan 2012 20:35:58 +0000 (21:35 +0100)]
fhdl: make WRITE_FIRST default
Sebastien Bourdeauducq [Fri, 27 Jan 2012 20:23:17 +0000 (21:23 +0100)]
doc: memories
Sebastien Bourdeauducq [Fri, 27 Jan 2012 19:22:17 +0000 (20:22 +0100)]
fhdl: memories working
Sebastien Bourdeauducq [Fri, 27 Jan 2012 15:54:48 +0000 (16:54 +0100)]
fhdl/verilog: clean up signal classification and support memory descriptions
Sebastien Bourdeauducq [Fri, 27 Jan 2012 15:53:34 +0000 (16:53 +0100)]
fhdl/structure: memory description
Sebastien Bourdeauducq [Fri, 27 Jan 2012 13:35:58 +0000 (14:35 +0100)]
doc: cosmetic changes
Sebastien Bourdeauducq [Thu, 26 Jan 2012 17:01:17 +0000 (18:01 +0100)]
doc: ASMI description
Sebastien Bourdeauducq [Wed, 25 Jan 2012 19:10:11 +0000 (20:10 +0100)]
Remove duplicate logo
Sebastien Bourdeauducq [Wed, 25 Jan 2012 19:01:45 +0000 (20:01 +0100)]
doc: refactor
Sebastien Bourdeauducq [Sat, 21 Jan 2012 23:32:02 +0000 (00:32 +0100)]
flow/ala: fix typo for And (thanks Lars)
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