Luke Kenneth Casson Leighton [Mon, 4 May 2020 08:01:45 +0000 (09:01 +0100)]
move example to separate section, cleanup HTML
Yehowshua [Mon, 4 May 2020 01:25:25 +0000 (02:25 +0100)]
Yehowshua [Mon, 4 May 2020 00:12:04 +0000 (01:12 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:33:12 +0000 (23:33 +0100)]
describe concurrent computational unit
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:16:14 +0000 (23:16 +0100)]
correct image name
Luke Kenneth Casson Leighton [Sun, 3 May 2020 22:15:33 +0000 (23:15 +0100)]
add FU-FU and FU-Regs vectors
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:53:00 +0000 (22:53 +0100)]
add additional images
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:31:03 +0000 (22:31 +0100)]
whitespace
Luke Kenneth Casson Leighton [Sun, 3 May 2020 21:29:40 +0000 (22:29 +0100)]
whitespace
lkcl [Sun, 3 May 2020 21:26:54 +0000 (22:26 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:59:20 +0000 (15:59 +0100)]
mention concurrent units, update regfile image to double-up the pipelines
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:06:03 +0000 (15:06 +0100)]
mention that the 4x4 crossbar is a major data bottleneck
Luke Kenneth Casson Leighton [Sun, 3 May 2020 14:00:51 +0000 (15:00 +0100)]
update diagram and include text on regfile arrangement
lkcl [Sun, 3 May 2020 13:21:23 +0000 (14:21 +0100)]
lkcl [Sun, 3 May 2020 13:21:01 +0000 (14:21 +0100)]
lkcl [Sun, 3 May 2020 13:20:43 +0000 (14:20 +0100)]
lkcl [Sun, 3 May 2020 13:18:00 +0000 (14:18 +0100)]
Luke Kenneth Casson Leighton [Sun, 3 May 2020 13:16:41 +0000 (14:16 +0100)]
add regfile diagram
Luke Kenneth Casson Leighton [Sun, 3 May 2020 13:16:28 +0000 (14:16 +0100)]
add walkthrough video for memory and cache
Yehowshua [Sat, 2 May 2020 19:29:33 +0000 (20:29 +0100)]
Yehowshua [Sat, 2 May 2020 06:10:43 +0000 (07:10 +0100)]
Luke Kenneth Casson Leighton [Fri, 1 May 2020 11:18:46 +0000 (12:18 +0100)]
whitespace
programmerjake [Fri, 1 May 2020 02:45:07 +0000 (03:45 +0100)]
add load-store unit ideas
programmerjake [Fri, 1 May 2020 00:40:37 +0000 (01:40 +0100)]
add prefix sum
lkcl [Thu, 30 Apr 2020 18:56:58 +0000 (19:56 +0100)]
Luke Kenneth Casson Leighton [Thu, 30 Apr 2020 17:30:23 +0000 (18:30 +0100)]
add walk-through videos for LD/ST CompUnit
Luke Kenneth Casson Leighton [Thu, 30 Apr 2020 17:23:16 +0000 (18:23 +0100)]
update new version of LD/ST which can do "update" mode and indexed
lkcl [Wed, 29 Apr 2020 14:07:54 +0000 (15:07 +0100)]
lkcl [Wed, 29 Apr 2020 09:03:07 +0000 (10:03 +0100)]
lkcl [Wed, 29 Apr 2020 09:02:22 +0000 (10:02 +0100)]
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 22:28:29 +0000 (23:28 +0100)]
update wr-any signal in ldstcomp
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 17:06:51 +0000 (18:06 +0100)]
update ld/st diagram to deal with ST-with-update
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 16:20:54 +0000 (17:20 +0100)]
missing signals on SR Latches
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:36:52 +0000 (16:36 +0100)]
add discussion links for LD/ST Comp Unit
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:29:09 +0000 (16:29 +0100)]
corrections to firing WR latch
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:15:46 +0000 (16:15 +0100)]
add text to ld_st_comp_unit image
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 15:04:15 +0000 (16:04 +0100)]
update LD/ST comp unit simplify explanation for now
Luke Kenneth Casson Leighton [Tue, 28 Apr 2020 14:55:18 +0000 (15:55 +0100)]
add new update-capable ld/st comp unit
lkcl [Mon, 27 Apr 2020 20:50:12 +0000 (21:50 +0100)]
lkcl [Mon, 27 Apr 2020 20:47:00 +0000 (21:47 +0100)]
lkcl [Mon, 27 Apr 2020 20:37:59 +0000 (21:37 +0100)]
lkcl [Mon, 27 Apr 2020 20:36:59 +0000 (21:36 +0100)]
lkcl [Mon, 27 Apr 2020 20:36:06 +0000 (21:36 +0100)]
lkcl [Mon, 27 Apr 2020 20:35:21 +0000 (21:35 +0100)]
lkcl [Mon, 27 Apr 2020 20:31:06 +0000 (21:31 +0100)]
lkcl [Mon, 27 Apr 2020 20:30:15 +0000 (21:30 +0100)]
lkcl [Mon, 27 Apr 2020 20:25:40 +0000 (21:25 +0100)]
lkcl [Mon, 27 Apr 2020 20:25:23 +0000 (21:25 +0100)]
lkcl [Mon, 27 Apr 2020 20:22:32 +0000 (21:22 +0100)]
lkcl [Mon, 27 Apr 2020 20:21:24 +0000 (21:21 +0100)]
lkcl [Mon, 27 Apr 2020 20:19:23 +0000 (21:19 +0100)]
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:45:07 +0000 (11:45 +0100)]
update text description to match diagram on L0 cache/buffer
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:37:35 +0000 (11:37 +0100)]
update image size
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:34:32 +0000 (11:34 +0100)]
revise diagram to include twin-l0-port
Luke Kenneth Casson Leighton [Mon, 27 Apr 2020 10:28:03 +0000 (11:28 +0100)]
add memory interface requirements section
lkcl [Mon, 27 Apr 2020 05:28:37 +0000 (06:28 +0100)]
lkcl [Mon, 27 Apr 2020 05:27:43 +0000 (06:27 +0100)]
lkcl [Mon, 27 Apr 2020 05:14:48 +0000 (06:14 +0100)]
lkcl [Sat, 25 Apr 2020 16:53:22 +0000 (17:53 +0100)]
lkcl [Fri, 24 Apr 2020 14:40:34 +0000 (15:40 +0100)]
Luke Kenneth Casson Leighton [Thu, 23 Apr 2020 13:46:46 +0000 (14:46 +0100)]
add link to list
programmerjake [Thu, 23 Apr 2020 05:45:09 +0000 (06:45 +0100)]
add placeholder alternative memory interface design idea
programmerjake [Thu, 23 Apr 2020 05:43:23 +0000 (06:43 +0100)]
add link to alternative memory interface idea
lkcl [Thu, 23 Apr 2020 00:35:09 +0000 (01:35 +0100)]
lkcl [Thu, 23 Apr 2020 00:32:15 +0000 (01:32 +0100)]
lkcl [Thu, 23 Apr 2020 00:28:59 +0000 (01:28 +0100)]
lkcl [Wed, 22 Apr 2020 22:23:11 +0000 (23:23 +0100)]
lkcl [Wed, 22 Apr 2020 22:14:14 +0000 (23:14 +0100)]
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 13:08:06 +0000 (14:08 +0100)]
mention misaligned exception;
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:52:59 +0000 (13:52 +0100)]
add link to comp.arch
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:31:24 +0000 (13:31 +0100)]
write-up on twin L0 cache/buffer
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:11:42 +0000 (13:11 +0100)]
add twin L0 cache/buffer diagram
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 12:09:13 +0000 (13:09 +0100)]
add twin L0 cache/buffer
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 10:41:58 +0000 (11:41 +0100)]
add memory and cache page for 180nm ASIC
Luke Kenneth Casson Leighton [Wed, 22 Apr 2020 10:11:16 +0000 (11:11 +0100)]
add 180nm memory layout diagram
lkcl [Mon, 20 Apr 2020 15:52:38 +0000 (16:52 +0100)]
Luke Kenneth Casson Leighton [Sun, 19 Apr 2020 17:26:23 +0000 (18:26 +0100)]
add alternative L0 to L1 bridge (v2)
Luke Kenneth Casson Leighton [Sun, 19 Apr 2020 15:12:04 +0000 (16:12 +0100)]
whitespace
Luke Kenneth Casson Leighton [Sun, 19 Apr 2020 15:07:05 +0000 (16:07 +0100)]
extend L0 cache/buffer section
Luke Kenneth Casson Leighton [Sun, 19 Apr 2020 14:15:46 +0000 (15:15 +0100)]
add section on L0 cache/buffer
Luke Kenneth Casson Leighton [Sun, 19 Apr 2020 14:00:44 +0000 (15:00 +0100)]
add FU mem L0 to L1 bridge image
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:59:08 +0000 (15:59 +0100)]
mention revisions
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:58:36 +0000 (15:58 +0100)]
mention revisions
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:56:24 +0000 (15:56 +0100)]
clarify about Redhat
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:52:27 +0000 (15:52 +0100)]
add revision 1 stamp
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:51:14 +0000 (15:51 +0100)]
clarify, whitespace
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:47:10 +0000 (15:47 +0100)]
mention trap on illegal instruction
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 14:46:08 +0000 (15:46 +0100)]
whitespace cleanup
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Sat, 18 Apr 2020 14:28:44 +0000 (15:28 +0100)]
tweak word ordering
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 13:54:10 +0000 (14:54 +0100)]
minor shuffle
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 13:52:42 +0000 (14:52 +0100)]
update isans letter
Luke Kenneth Casson Leighton [Sat, 18 Apr 2020 10:48:37 +0000 (11:48 +0100)]
add multi-bus arbiter image
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Thu, 16 Apr 2020 20:22:34 +0000 (21:22 +0100)]
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 15:38:51 +0000 (16:38 +0100)]
replace multi priority picker image
Luke Kenneth Casson Leighton [Thu, 16 Apr 2020 12:50:20 +0000 (13:50 +0100)]
clarify isans letter
Add section 5.4 with references to past fpu mistakes re Trancendentals
Tobias Platen [Wed, 15 Apr 2020 16:51:29 +0000 (18:51 +0200)]
HDL_workflow.mdwn
addw@fa2f8cb1790dfac204f803a3bfd8edda6ef3edc6 [Wed, 15 Apr 2020 16:48:53 +0000 (17:48 +0100)]
Luke Kenneth Casson Leighton [Wed, 15 Apr 2020 11:56:29 +0000 (12:56 +0100)]
isans rewrite
Luke Kenneth Casson Leighton [Wed, 15 Apr 2020 10:55:01 +0000 (11:55 +0100)]
compunit minor adjustment
projects / libreriscv.git / log