Marc Orr [Mon, 6 Aug 2012 23:52:40 +0000 (16:52 -0700)]
syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations,
since some use the generic Linux definitions only, and others
use definitions inherited from earlier Unix flavors on those
architectures.
Also update x86 function pointers so ioctl is no longer
unimplemented on that platform.
This patch is a revised version of Vince Weaver's earlier patch.
Nilay Vaish [Mon, 6 Aug 2012 23:14:32 +0000 (18:14 -0500)]
Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.
Nilay Vaish [Mon, 6 Aug 2012 23:14:31 +0000 (18:14 -0500)]
Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.
Jason Power [Wed, 1 Aug 2012 22:07:34 +0000 (17:07 -0500)]
Ruby NetDest: add assert for bad element in netdest
Ali Saidi [Mon, 30 Jul 2012 16:11:25 +0000 (12:11 -0400)]
stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update
Ali Saidi [Sat, 28 Jul 2012 17:48:04 +0000 (13:48 -0400)]
stats: fix some miss-committed changes from the icache change
Nathanael Premillieu [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
util: Fix issues with style checker.
Ali Saidi [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
stats: update stats for icache change not allowing dirty data
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
dma: remove unused variable
this patch removes the actionInProgress field from the DmaPort class.
this variable is only defined and initiated in the ctor. it is never used.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading the
cpu id register failed because the ids did not match, and hence, the result
of the instruction did not match. this patch ensures that the ids match so
this instruction does not fail. this problem only seemed to manifest itself
when multiple cores were in the system, either multi-core, or extra switched-
out cores present in the system.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
cache: don't allow dirty data in the i-cache
removes the optimization that forwards an exclusive copy to a requester on a
read, only for the i-cache. this optimization isn't necessary because we
typically won't be writing to the i-cache.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ -
b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
Andreas Hansson [Mon, 23 Jul 2012 13:32:22 +0000 (09:32 -0400)]
Config: Use clock option in se/fs script and pass to switch_cpus
This patch changes the se and fs script to use the clock option and
not simply set the CPUs clock to 2 GHz. It also makes a minor change
to the assignment of the switch_cpus clock to allow different clocks.
Andreas Hansson [Mon, 23 Jul 2012 13:32:19 +0000 (09:32 -0400)]
Bridge: Use EventWrapper instead of Event subclass for sendEvent
This class simply cleans up the code by making use of the EventWrapper
convenience class to schedule the sendEvent in the bridge ports.
Steve Reinhardt [Mon, 23 Jul 2012 04:39:12 +0000 (00:39 -0400)]
test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs
were clobbered.
Steve Reinhardt [Mon, 23 Jul 2012 04:33:05 +0000 (00:33 -0400)]
test: Restore eio ref files clobbered in rev
8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
Nilay Vaish [Mon, 23 Jul 2012 01:31:24 +0000 (20:31 -0500)]
Regression: Update stats due to changes to x86 cpuid instruction
Nilay Vaish [Mon, 23 Jul 2012 01:31:23 +0000 (20:31 -0500)]
X86 CPUID: Return false if unknown processor family
Andreas Hansson [Sat, 21 Jul 2012 21:24:01 +0000 (17:24 -0400)]
Regression: Fix topologies path in failing pc-simple-timing-ruby
This patch updates the path to the Ruby topologies and thus fixes a
failing regression.
Steve Reinhardt [Thu, 19 Jul 2012 23:53:02 +0000 (16:53 -0700)]
Added tag stable_2012_06_28 for changeset
f75ee4849c40
Steve Reinhardt [Thu, 19 Jul 2012 23:51:01 +0000 (16:51 -0700)]
Added tag stable_2012_02_02 for changeset
549b72de8f72
Andreas Hansson [Thu, 12 Jul 2012 16:56:13 +0000 (12:56 -0400)]
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
Andreas Hansson [Thu, 12 Jul 2012 16:56:11 +0000 (12:56 -0400)]
scons: Add LIBRARY_PATH from the user environment to Scons
This patch adds the LIBRARY_PATH from the users OS environment to
Scons build environment. This path is used when linking to search for
libraries, and this patch enables tcmalloc to be used during the build
even if it is not placed in the default search paths.
Nilay Vaish [Thu, 12 Jul 2012 13:39:20 +0000 (08:39 -0500)]
Regression: update ruby.stats file
Nilay Vaish [Thu, 12 Jul 2012 13:39:19 +0000 (08:39 -0500)]
Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.
Nilay Vaish [Thu, 12 Jul 2012 13:39:18 +0000 (08:39 -0500)]
Ruby: remove some unused stuff from SLICC files
Brad Beckmann [Wed, 11 Jul 2012 19:21:04 +0000 (12:21 -0700)]
x86: added page size in bytes tlb entry function
Brad Beckmann [Wed, 11 Jul 2012 16:44:34 +0000 (09:44 -0700)]
ruby: improved DRAM reset comment
Brad Beckmann [Wed, 11 Jul 2012 05:51:55 +0000 (22:51 -0700)]
regress: ruby stat additions and config changes
Marc Orr [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
syscall emulation: Add the futex system call.
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
x86: logSize and lruSeq are now optional ckpt params
Steve Reinhardt [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
Add hook to call map() on Process from python.
This enables configuration scripts to set up mappings
from process virtual addresses to specific physical
addresses in SE mode. This feature is needed to
support modeling of user-accessible memories or
devices in SE mode, avoiding the complexities of FS
mode and the need to write a device driver.
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed fatal print statement
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: remove the cpu assumptions for the random tester
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed msgptr print call
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
imported patch jason/slicc-external-structure-fix
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
Joel Hestness [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: tag and data cache access support
Updates to Ruby to support statistics counting of cache accesses. This feature
serves multiple purposes beyond simple stats collection. It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.
Nuwan Jayasena [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Brad Beckmann [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
cpu: added assertions to ensure the correct proxies are used
Brad Beckmann [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
ruby: changes how Topologies are created
Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.
--HG--
rename : src/mem/ruby/network/topologies/Crossbar.py => configs/topologies/Crossbar.py
rename : src/mem/ruby/network/topologies/Mesh.py => configs/topologies/Mesh.py
rename : src/mem/ruby/network/topologies/MeshDirCorners.py => configs/topologies/MeshDirCorners.py
rename : src/mem/ruby/network/topologies/Pt2Pt.py => configs/topologies/Pt2Pt.py
rename : src/mem/ruby/network/topologies/Torus.py => configs/topologies/Torus.py
Andreas Hansson [Mon, 9 Jul 2012 16:35:46 +0000 (12:35 -0400)]
EventManager: Rename queue accessor and remove cast operator
This patch renames the queue() accessor to the less ambigious
eventQueue, and also removes the cast operator. The queue() member
function cause problems in derived classes that declare members with
the same name, e.g. a MemObject subclass that has a packet queue on
its own. The operator is not causing any harm at this point, but as it
is not used there is little point in keeping it.
Andreas Hansson [Mon, 9 Jul 2012 16:35:44 +0000 (12:35 -0400)]
Mem: Make members relating to range and size constant
This patch makes the address-range related members const. The change
is trivial and merely ensures that they can be called on a const
memory.
Andreas Hansson [Mon, 9 Jul 2012 16:35:42 +0000 (12:35 -0400)]
Port: Hide the queue implementation in SimpleTimingPort
This patch makes the queue implementation in the SimpleTimingPort
private to avoid confusion with the protected member queue in the
QueuedSlavePort. The SimpleTimingPort provides the queue_impl to the
QueuedSlavePort and it can be accessed via the reference in the base
class. The use of the member name queue is thus no longer overloaded.
Andreas Hansson [Mon, 9 Jul 2012 16:35:41 +0000 (12:35 -0400)]
Stats: Updates due to bus changes
This patch bumps all the stats to reflect the bus changes, i.e. the
introduction of the state variable, the division into a request and
response layer, and the new default bus width of 8 bytes.
Andreas Hansson [Mon, 9 Jul 2012 16:35:39 +0000 (12:35 -0400)]
Port: Align port names in C++ and Python
This patch is a first step to align the port names used in the Python
world and the C++ world. Ultimately it serves to make the use of
config.json together with output from the simulation easier, including
post-processing of statistics.
Most notably, the CPU, cache, and bus is addressed in this patch, and
there might be other ports that should be updated accordingly. The
dash name separator has also been replaced with a "." which is what is
used to concatenate the names in python, and a separation is made
between the master and slave port in the bus.
Andreas Hansson [Mon, 9 Jul 2012 16:35:38 +0000 (12:35 -0400)]
Bus: Make the default bus width 8 bytes instead of 64
This patch changes the default bus width to a more sensible 8 bytes
(64 bits), which is in line with most on-chip buses. Although there
are cases where a wider or narrower bus is useful, the 8 bytes is a
good compromise to serve as the default.
This patch changes essentially all statistics, and will be bundled
with the outstanding changes to the bus.
Andreas Hansson [Mon, 9 Jul 2012 16:35:37 +0000 (12:35 -0400)]
Bus: Split the bus into separate request/response layers
This patch splits the existing buses into multiple layers. The
non-coherent bus is split into a request and a response layer, and the
coherent bus adds an additional layer for the snoop responses. The
layer is modified to be templatised on the port type, such that the
different layers can have retryLists with either master or slave
ports. This patch also removes the dynamic cast from the retry, as
previously promised when moving the recvRetry from the port base class
to the master/slave port respectively.
Overall, the split bus more closely reflects any modern on-chip bus
and should be at step in the right direction. From this point, it
would be reasonable straight forward to add separate layers (and thus
contention points and arbitration) for each port and thus create a
true crossbar.
The regressions all produce the correct output, but have varying
degrees of changes to their statistics. A separate patch will be
pushed with the updates to the reference statistics.
Andreas Hansson [Mon, 9 Jul 2012 16:35:36 +0000 (12:35 -0400)]
Bus: Add a notion of layers to the buses
This patch moves all flow control, arbitration and state information
into a bus layer. The layer is thus responsible for all the state
transitions, and for keeping hold of the retry list. Consequently the
layer is also responsible for the draining.
With this change, the non-coherent and coherent bus are given a single
layer to avoid changing any temporal behaviour, but the patch opens up
for adding more layers.
Andreas Hansson [Mon, 9 Jul 2012 16:35:35 +0000 (12:35 -0400)]
Bus: Replace tickNextIdle and inRetry with a state variable
This patch adds a state enum and member variable in the bus, tracking
the bus state, thus eliminating the need for tickNextIdle and inRetry,
and fixing an issue that allowed the bus to be occupied by multiple
packets at once (hopefully it also makes it easier to understand the
code).
The bus, in its current form, uses tickNextIdle and inRetry to keep
track of the state of the bus. However, it only updates tickNextIdle
_after_ forwarding a packet using sendTiming, and the result is that
the bus is still seen as idle, and a module that receives the packet
and starts transmitting new packets in zero time will still see the
bus as idle (and this is done by a number of DMA devices). The issue
can also be seen in isOccupied where the bus calls reschedule on an
event instead of schedule.
This patch addresses the problem by marking the bus as _not_ idle
already by the time we conclude that the bus is not occupied and we
will deal with the packet.
As a result of not allowing multiple packets to occupy the bus, some
regressions have slight changes in their statistics. A separate patch
updates these accordingly.
Further ahead, a follow-on patch will introduce a separate state
variable for request/responses/snoop responses, and thus implement a
split request/response bus with separate flow control for the
different message types (even further ahead it will introduce a
multi-layer bus).
Andreas Hansson [Mon, 9 Jul 2012 16:35:34 +0000 (12:35 -0400)]
Port: Make getAddrRanges const
This patch makes getAddrRanges const throughout the code base. There
is no reason why it should not be, and making it const prevents adding
any unintentional side-effects.
Andreas Hansson [Mon, 9 Jul 2012 16:35:33 +0000 (12:35 -0400)]
Port: Add getAddrRanges to master port (asking slave port)
This patch adds getAddrRanges to the master port, and thus avoids
going through getSlavePort to be able to ask the slave. Similar to the
previous patch that added isSnooping to the SlavePort, this patch aims
to introduce an additional level of hierarchy in the ports (base port
being protocol-agnostic) and getSlave/MasterPort will return port
pointers to these base classes.
The function is named getAddrRanges also on the master port, but does
nothing besides asking the connected slave port. The slave port, as
before, has to provide an implementation and actually produce a list
of address ranges. The initial design used the name getSlaveAddrRanges
for the new function, but the more verbose name was later changed.
Andreas Hansson [Mon, 9 Jul 2012 16:35:32 +0000 (12:35 -0400)]
Port: Add isSnooping to slave port (asking master port)
This patch adds isSnooping to the slave port, and thus avoids going
through getMasterPort to be able to ask the master. Over the course of
the next few patches, all getMasterPort/getSlavePort in Port and
MemObject are to be protocol agnostic, and the snooping is part of the
protocol layer.
The function is already present on the master port, where it is
implemented by the module itself, e.g. a cache. On the slave side, it
is merely asking the connected master port. The same name is used by
both functions despite their difference in behaviour. The initial
design used isMasterSnooping on the slave port side, but the more
verbose function name was later changed.
Andreas Hansson [Mon, 9 Jul 2012 16:35:31 +0000 (12:35 -0400)]
Port: Move retry from port base class to Master/SlavePort
This patch is the last part of moving all protocol-related
functionality out of the Port base class. All the send/recv functions
are already moved, and the retry (which still governs all the timing
transport functions) is the only part that remained in the base class.
The only point where this currently causes a bit of inconvenience is
in the bus where the retry list is global and holds Port pointers (not
Master/SlavePort). This is about to change with the split into a
request/response bus and will soon be removed anyway.
The patch has no impact on any regressions.
Andreas Hansson [Mon, 9 Jul 2012 16:35:30 +0000 (12:35 -0400)]
Fix: Address a few benign memory leaks
This patch is the result of static analysis identifying a number of
memory leaks. The leaks are all benign as they are a result of not
deallocating memory in the desctructor. The fix still has value as it
removes false positives in the static analysis.
Andreas Hansson [Mon, 2 Jul 2012 12:21:53 +0000 (08:21 -0400)]
gcc: Fix warnings for gcc 4.7 and clang 3.1
This patch fixes two warnings, one related to a narrowing conversion
(int to MachInst), and one due to the cast operator for arguments and
a mismatch in const-ness (const void* and void*).
Lena Olson [Fri, 29 Jun 2012 15:21:58 +0000 (11:21 -0400)]
Cache: Fix the LRU policy for classic memory hierarchy
The LRU policy always evicted the least recently touched way, even if it
contained valid data and another way was invalid, as can happen if a block has
been invalidated by coherance. This can result in caches never warming up even
though they are replacing blocks. This modifies the LRU policy to move blocks
to LRU position on invalidation.
Uri Wiener [Fri, 29 Jun 2012 15:19:08 +0000 (11:19 -0400)]
Bus: enable non/coherent buses sub-classes
This patch merely changes several methods to be virtual in order to enable
non/coherent buses sub-classes.
Dam Sunwoo [Fri, 29 Jun 2012 15:19:07 +0000 (11:19 -0400)]
Mem: fix master id assertion in cache_impl.hh
The assertion was applied to the wrong packet.
This patch fixes the issue rerported by Xiang Jiang on the gem5-dev mailing list.
Matt Evans [Fri, 29 Jun 2012 15:19:06 +0000 (11:19 -0400)]
Style: Make style.py's invalid warning print which file caused the infraction.
Matt Evans [Fri, 29 Jun 2012 15:19:05 +0000 (11:19 -0400)]
Mem: Fix a livelock resulting in LLSC/locked memory access implementation.
Currently when multiple CPUs perform a load-linked/store-conditional sequence,
the loads all create a list of reservations which is then scanned when the
stores occur. A reservation matching the context and address of the store is
sought, BUT all reservations matching the address are also erased at this point.
The upshot is that a store-conditional will remove all reservations even if the
store itself does not succeed. A livelock was observed using 7-8 CPUs where a
thread would erase the reservations of other threads, not succeed, loop and put
its own reservation in again only to have it blown by another thread that
unsuccessfully now tries to store-conditional -- no forward progress was made,
hanging the system.
The correct way to do this is to only blow a reservation when a store
(conditional or not) actually /occurs/ to its address. One thread always wins
(the one that does the store-conditional first).
Ali Saidi [Fri, 29 Jun 2012 15:19:03 +0000 (11:19 -0400)]
Stats: Update stats for RAS and LRU fixes.
Nathanael Premillieu [Fri, 29 Jun 2012 15:18:29 +0000 (11:18 -0400)]
O3: Track if the RAS has been pushed or not to pop the RAS if neccessary.
Add new flag (named pushedRAS) in the PredictorHistory structure.
This flag tracks whether the RAS has been pushed or not during a prediction.
Then, in the squash function it is used to pop the RAS if necessary.
Ali Saidi [Fri, 29 Jun 2012 15:18:29 +0000 (11:18 -0400)]
ARM: Fix identification of one RAS pop instruction.
The check should be with the op2 field, not with the op1 field.
Ali Saidi [Fri, 29 Jun 2012 15:18:29 +0000 (11:18 -0400)]
Cache: Only invalidate a line in the cache when an uncacheable write is seen.
Ali Saidi [Fri, 29 Jun 2012 15:18:29 +0000 (11:18 -0400)]
ARM: Update version of linux we claim to be to 3.0.0.
Static binaries generated with new versions of libc complain that the kernel
is too old otherwise.
Ali Saidi [Fri, 29 Jun 2012 15:18:28 +0000 (11:18 -0400)]
ARM: Fix issue with predicted next pc being wrong because of advance() ordering.
npc in PCState for ARM was being calculated before the current flags were
updated with the next flags. This causes an issue as the npc is incremented by
two or four depending on the current flags (thumb or not) and was leading to
branches that were predicted correctly being identified as mispredicted.
Ali Saidi [Wed, 27 Jun 2012 23:23:02 +0000 (19:23 -0400)]
ARM: Fix address range issue with VExpress EMM
Andreas Hansson [Wed, 20 Jun 2012 23:32:42 +0000 (19:32 -0400)]
swig: Use SWIG from environment when determining version
This patch fixes a minor issue in the SConstruct where a hardcoded
swig is used instead of the environment SWIG when determining the
version.
Andreas Hansson [Mon, 18 Jun 2012 19:43:12 +0000 (15:43 -0400)]
Build: Point to the appropriate tcmalloc package
This patch updates the message printed if the user does not have
tcmalloc available. It turns out that the correct package (which
creates all required symlinks etc) is libgoogle-perftools-dev. This
has been verified on Ubuntu 12.04.
Anthony Gutierrez [Mon, 11 Jun 2012 15:07:42 +0000 (11:07 -0400)]
configs: add run scripts for ics/gb versions of android and bbench
1) Modifies Benchmarks.py to add support for Android ICS and BBench on Android ICS.
2) An rcS script is added for BBench on ICS.
3) Separates benchmark entries and rcS scripts for GB/ICS
4) Removes the debugging output from the existing BBench run script. These
print statements were used for debugging and they seemed to confuse users
into believing they should see some terminal output.
Anthony Gutierrez [Mon, 11 Jun 2012 15:07:41 +0000 (11:07 -0400)]
ARM: implement the ProcessInfo methods
Ali Saidi [Mon, 11 Jun 2012 14:54:37 +0000 (10:54 -0400)]
scons: Make compiler version error more verbose and easier to debug.
Marc Orr [Mon, 11 Jun 2012 07:16:43 +0000 (03:16 -0400)]
Regression: Fix some bugs in simple-timing-mp-ruby.py.
Andreas Hansson [Fri, 8 Jun 2012 16:45:24 +0000 (12:45 -0400)]
Timing CPU: Remove a redundant port pointer
This patch is trivial and merely prunes a pointer that was never set
or used.
Andreas Hansson [Fri, 8 Jun 2012 16:44:17 +0000 (12:44 -0400)]
Power: Fix MaxMiscDestRegs which was set to zero
This patch fixes a failing compilation caused by MaxMiscDestRegs being
zero. According to gcc 4.6, the result is a comparison that is always
false due to limited range of data type.
Nilay Vaish [Thu, 7 Jun 2012 22:03:45 +0000 (17:03 -0500)]
X86 TLB: Add a missing = sign
Ali Saidi [Thu, 7 Jun 2012 14:59:03 +0000 (10:59 -0400)]
mem: Delay deleting of incoming packets by one call.
This patch is a temporary fix until Andreas' four-phase patches
get reviewed and committed. Removing FastAlloc seems to have exposed
an issue which previously was reasonable rare in which packets are freed
before the sending cache is done with them. This change puts incoming packets
no a pendingDelete queue which are deleted at the start of the next call and
thus breaks the dependency between when the caller returns true and when the
packet is actually used by the sending cache.
Running valgrind on a multi-core linux boot and the memtester results in no
valgrind warnings.
Jayneel Gandhi [Thu, 7 Jun 2012 13:11:00 +0000 (08:11 -0500)]
X86 TLB: Fix for gcc 4.4.3
Due to recent changes to X86 TLB, gem5 stopped compiling on
gcc version 4.4.3. This patch provides the fix for that problem. The patch
is tested on gcc 4.4.3. The change is not required for more recent
versions of gcc (like on 4.6.3).
Nilay Vaish [Thu, 7 Jun 2012 13:05:31 +0000 (08:05 -0500)]
Config: call to setWorkCountOptions() for all ISAs
Nilay Vaish [Thu, 7 Jun 2012 13:05:30 +0000 (08:05 -0500)]
Config: Remove setMipsOptions
As status matrix, MIPS fs does not work. Hence, these options are not
required. Secondly, the function is setting param values for a CPU class.
This seems strange, should probably be done in a different way.
Nilay Vaish [Thu, 7 Jun 2012 13:05:30 +0000 (08:05 -0500)]
Config: changes to a couple of error msgs
Anthony Gutierrez [Tue, 5 Jun 2012 18:20:13 +0000 (14:20 -0400)]
cpu: Don't init simple and inorder CPUs if they are defered.
initCPU() will be called to initialize switched out CPUs for the simple and
inorder CPU models. this patch prevents those CPUs from being initialized
because they should get their state from the active CPU when it is switched
out.
Ali Saidi [Tue, 5 Jun 2012 17:52:30 +0000 (13:52 -0400)]
ISA: Back-out NoopMachInst as a StaticInstPtr change.
Ali Saidi [Tue, 5 Jun 2012 14:36:59 +0000 (10:36 -0400)]
cpt: update some comments in the checkpoint migration script
Ali Saidi [Tue, 5 Jun 2012 05:23:16 +0000 (01:23 -0400)]
all: Update stats for memory per master and total fix.
William Wang [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
stats: when applying an operation to two vectors sum the components first.
Previously writing X/Y in a formula would result in:
x[0]/y[0] + x[1]/y[1]
In reality you want:
(x[0] +x[1])/(y[0] + y[1])
Dam Sunwoo [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
Mem: add per-master stats to physmem
Added per-master stats (similar to cache stats) to physmem.
Geoffrey Blake [Tue, 5 Jun 2012 05:23:11 +0000 (01:23 -0400)]
ARM: Add PCIe support to VExpress_EMM model and remove deprecated ELT
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: removed extra white space
Extra white space fixes in miscregs.hh
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: Fix MPIDR and MIDR register implementation.
This change allows designating a system as MP capable or not as some
bootloaders/kernels care that it's set right. You can have a single
processor MP capable system, but you can't have a multi-processor
UP only system. This change also fixes the initialization of the MIDR
register.
Chander Sudanthi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
ARM: PS2 encoding fix
Fixed Disable encoding and added SetDefaults.
See http://wiki.osdev.org/Mouse_Input for encodings.
Ali Saidi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
sim: Provide a framework for detecting out of data checkpoints and migrating them.
Ali Saidi [Tue, 5 Jun 2012 05:23:10 +0000 (01:23 -0400)]
stats: Add stats unittest for total calculations.
Ali Saidi [Tue, 5 Jun 2012 05:23:09 +0000 (01:23 -0400)]
O3: Clean up the O3 structures and try to pack them a bit better.
DynInst is extremely large the hope is that this re-organization will put the
most used members close to each other.
Ali Saidi [Tue, 5 Jun 2012 05:23:09 +0000 (01:23 -0400)]
sim: Add support for tcmalloc if it's installed and available.
This package is available in Ubuntu, Debian, and Redhat as google-perftools.
With multiple tests on a single machine I've seen a little over 10% performance
gain with tcmalloc.
Ali Saidi [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
sim: Remove FastAlloc
While FastAlloc provides a small performance increase (~1.5%) over regular malloc it isn't thread safe.
After removing FastAlloc and using tcmalloc I've seen a performance increase of 12% over libc malloc
when running twolf for ARM.
Ali Saidi [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
ARM: Fix over-eager assert in gic.
Mitchell Hayenga [Tue, 5 Jun 2012 05:23:08 +0000 (01:23 -0400)]
stats: Provide a mechanism to get a callback when stats are dumped.
This mechanism is useful for dumping output that is correlated with stats
dumping, but isn't tracked by the gem5 statistics.