openpower-isa.git
2 years agoadd missed generated csv changes
Jacob Lifshay [Fri, 24 Jun 2022 05:01:36 +0000 (22:01 -0700)]
add missed generated csv changes

2 years agoadd BM2-Form to power_enums.py
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:13:47 +0000 (17:13 +0100)]
add BM2-Form to power_enums.py

2 years agoelse must be on separate line in pseudocode av.mdwn
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:11:59 +0000 (17:11 +0100)]
else must be on separate line in pseudocode av.mdwn

2 years agomissing "Special Registers Altered" on av.mdwn
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 16:10:10 +0000 (17:10 +0100)]
missing "Special Registers Altered" on av.mdwn

2 years agoAdded bmask, pywriter failing
Andrey Miroshnikov [Thu, 23 Jun 2022 14:55:01 +0000 (14:55 +0000)]
Added bmask, pywriter failing

2 years agoadd SPDX-License-Headers to CSV files
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 09:53:40 +0000 (10:53 +0100)]
add SPDX-License-Headers to CSV files
(now that comments are possible)
mention provenance from microwatt decode1.vhdl

2 years agoadd explanatory comments on minor_22.csv
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 09:45:00 +0000 (10:45 +0100)]
add explanatory comments on minor_22.csv

2 years agoadd comment-stripping to get_csv()
Luke Kenneth Casson Leighton [Thu, 23 Jun 2022 09:39:21 +0000 (10:39 +0100)]
add comment-stripping to get_csv()
there have been a lot of situations where comments are needed
including review of new instructions

2 years agoadd BM2 Form for (DRAFT) bmask instruction
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 14:53:33 +0000 (15:53 +0100)]
add BM2 Form for (DRAFT) bmask instruction

2 years agoAdded pc based on len(lst)
Andrey Miroshnikov [Wed, 22 Jun 2022 16:37:01 +0000 (16:37 +0000)]
Added pc based on len(lst)

2 years agoadd another cprop test, experimenting
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 14:45:46 +0000 (15:45 +0100)]
add another cprop test, experimenting

2 years agoadd 2nd cprop test to see what happens
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 14:44:06 +0000 (15:44 +0100)]
add 2nd cprop test to see what happens

2 years agoexpected number of instructions is 1 (therefore PC after running is 4 not 8)
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 14:41:43 +0000 (15:41 +0100)]
expected number of instructions is 1 (therefore PC after running is 4 not 8)

2 years agoAdded cprop test case, fails atm (not enabled by default)
Andrey Miroshnikov [Wed, 22 Jun 2022 14:38:10 +0000 (15:38 +0100)]
Added cprop test case, fails atm (not enabled by default)

2 years agoModified cprop pseudo-code due to parser bug
Andrey Miroshnikov [Wed, 22 Jun 2022 14:05:48 +0000 (15:05 +0100)]
Modified cprop pseudo-code due to parser bug

2 years agoargh horrible hack that does not work yet for fixing precedence
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 14:04:04 +0000 (15:04 +0100)]
argh horrible hack that does not work yet for fixing precedence

2 years agoadd X-Form to svp64.py av opcode set
Luke Kenneth Casson Leighton [Wed, 22 Jun 2022 13:26:55 +0000 (14:26 +0100)]
add X-Form to svp64.py av opcode set
(to be able to understand what the heck is going on)

2 years agoAdded cprop to caller, enums, svp64
Andrey Miroshnikov [Wed, 22 Jun 2022 13:07:06 +0000 (14:07 +0100)]
Added cprop to caller, enums, svp64

2 years agoAdded CPROP to powerenums
Andrey Miroshnikov [Wed, 22 Jun 2022 12:44:35 +0000 (13:44 +0100)]
Added CPROP to powerenums

2 years agoAdded entries for cprop, not sure if correct
Andrey Miroshnikov [Wed, 22 Jun 2022 12:06:52 +0000 (13:06 +0100)]
Added entries for cprop, not sure if correct

2 years agoadd absolute-signed-diff next to absolute-unsigned-diff
Luke Kenneth Casson Leighton [Mon, 20 Jun 2022 17:42:26 +0000 (18:42 +0100)]
add absolute-signed-diff next to absolute-unsigned-diff

2 years agorename absadd[us] to absdac[ud]
Luke Kenneth Casson Leighton [Mon, 20 Jun 2022 13:47:14 +0000 (14:47 +0100)]
rename absadd[us] to absdac[ud]
matches descriptions
# DRAFT Absolute Accumulate Signed Difference

2 years agofix minu[.] to be unsigned
Jacob Lifshay [Sun, 19 Jun 2022 21:47:48 +0000 (14:47 -0700)]
fix minu[.] to be unsigned

2 years agoupdate after adding av instructions
Jacob Lifshay [Sun, 19 Jun 2022 21:42:10 +0000 (14:42 -0700)]
update after adding av instructions

2 years agoadd absadds - signed accumulating add. DRAFT
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 19:40:12 +0000 (20:40 +0100)]
add absadds - signed accumulating add. DRAFT
https://bugs.libre-soc.org/show_bug.cgi?id=863

2 years agoadd absadd (unsigned) DRAFT
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 19:34:30 +0000 (20:34 +0100)]
add absadd (unsigned) DRAFT
https://bugs.libre-soc.org/show_bug.cgi?id=863

2 years agoadd absolute-difference DRAFT
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 19:05:54 +0000 (20:05 +0100)]
add absolute-difference DRAFT
https://bugs.libre-soc.org/show_bug.cgi?id=863

2 years agoadd average-add DRAFT pseudocode and CSV
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 18:37:47 +0000 (19:37 +0100)]
add average-add DRAFT pseudocode and CSV
https://bugs.libre-soc.org/show_bug.cgi?id=863

2 years agoadd the rest of min/max DRAFT av opcodes
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 18:14:58 +0000 (19:14 +0100)]
add the rest of min/max DRAFT av opcodes
https://bugs.libre-soc.org/show_bug.cgi?id=863

2 years agoadd maxs DRAFT instruction
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 16:10:21 +0000 (17:10 +0100)]
add maxs DRAFT instruction
https://libre-soc.org/openpower/sv/av_opcodes/

2 years agoextend minor_22.csv bitsel pattern to cover bits 21..31
Luke Kenneth Casson Leighton [Sun, 19 Jun 2022 15:08:03 +0000 (16:08 +0100)]
extend minor_22.csv bitsel pattern to cover bits 21..31

2 years agosv_binutils: drop SVP64_NAME_MAX
Dmitry Selyutin [Fri, 17 Jun 2022 13:51:18 +0000 (13:51 +0000)]
sv_binutils: drop SVP64_NAME_MAX

2 years agosv_binutils: minor naming conventions fixup
Dmitry Selyutin [Fri, 17 Jun 2022 13:50:00 +0000 (13:50 +0000)]
sv_binutils: minor naming conventions fixup

2 years agosv_binutils: rename Entry to Record
Dmitry Selyutin [Fri, 17 Jun 2022 13:47:38 +0000 (13:47 +0000)]
sv_binutils: rename Entry to Record

2 years agosv_binutils: rename Record to Desc
Dmitry Selyutin [Fri, 17 Jun 2022 13:41:32 +0000 (13:41 +0000)]
sv_binutils: rename Record to Desc

2 years agowhoops on an OR rather than an AND
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 13:20:44 +0000 (14:20 +0100)]
whoops on an OR rather than an AND

2 years agoadd "redirection" of MTSPR/MFSPR into TRAP pipeline for KAIVB
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 13:14:28 +0000 (14:14 +0100)]
add "redirection" of MTSPR/MFSPR into TRAP pipeline for KAIVB
in PowerDecoderSubset
https://bugs.libre-soc.org/show_bug.cgi?id=859
this reduces a lot of messing about by actually storing KAIVB
directly in the TRAP pipeline which is the only place it is used

2 years agoadd KAIVB SPR 850
Luke Kenneth Casson Leighton [Fri, 17 Jun 2022 12:54:52 +0000 (13:54 +0100)]
add KAIVB SPR 850
https://bugs.libre-soc.org/show_bug.cgi?id=859

2 years agoupdate version to 0.0 to stop unnecessary pip3 installs
Luke Kenneth Casson Leighton [Tue, 14 Jun 2022 14:13:43 +0000 (15:13 +0100)]
update version to 0.0 to stop unnecessary pip3 installs

2 years agoadd version constraints on setup install_requires
Luke Kenneth Casson Leighton [Tue, 14 Jun 2022 14:11:36 +0000 (15:11 +0100)]
add version constraints on setup install_requires

2 years agomedia/Makefile: switch to explicit LE toolchain
Dmitry Selyutin [Wed, 8 Jun 2022 17:53:49 +0000 (17:53 +0000)]
media/Makefile: switch to explicit LE toolchain

2 years agosvp64.py: simplify core script translation
Dmitry Selyutin [Wed, 8 Jun 2022 12:31:46 +0000 (12:31 +0000)]
svp64.py: simplify core script translation

2 years agomp3_0: update assembly listing
Dmitry Selyutin [Wed, 8 Jun 2022 11:52:44 +0000 (11:52 +0000)]
mp3_0: update assembly listing

2 years agosvp64.py: fix stdin/stdout modus operandi
Dmitry Selyutin [Mon, 6 Jun 2022 19:30:42 +0000 (19:30 +0000)]
svp64.py: fix stdin/stdout modus operandi

2 years agosvp64.py: switch print statements to logger
Dmitry Selyutin [Mon, 6 Jun 2022 18:27:50 +0000 (18:27 +0000)]
svp64.py: switch print statements to logger

2 years agosv_binutils: consider RA0 operand
Dmitry Selyutin [Wed, 1 Jun 2022 19:56:13 +0000 (19:56 +0000)]
sv_binutils: consider RA0 operand

2 years agosv_binutils: drop redundant prefix in C tags
Dmitry Selyutin [Wed, 1 Jun 2022 18:39:30 +0000 (18:39 +0000)]
sv_binutils: drop redundant prefix in C tags

2 years agosv_binutils: exclude useless records
Dmitry Selyutin [Wed, 1 Jun 2022 18:16:14 +0000 (18:16 +0000)]
sv_binutils: exclude useless records

2 years agosv_binutils: refactor CSV iteration
Dmitry Selyutin [Wed, 1 Jun 2022 18:07:11 +0000 (18:07 +0000)]
sv_binutils: refactor CSV iteration

2 years agosv_binutils: allow excluding enum values
Dmitry Selyutin [Wed, 1 Jun 2022 17:03:41 +0000 (17:03 +0000)]
sv_binutils: allow excluding enum values

2 years agosv_binutils: update sv_extra naming
Dmitry Selyutin [Wed, 1 Jun 2022 17:39:24 +0000 (17:39 +0000)]
sv_binutils: update sv_extra naming

2 years agosv_binutils: fix selector names
Dmitry Selyutin [Wed, 1 Jun 2022 11:12:52 +0000 (11:12 +0000)]
sv_binutils: fix selector names

2 years agosv_binutils: use ppc_opindex_t instead of unsigned char
Dmitry Selyutin [Wed, 1 Jun 2022 11:05:00 +0000 (11:05 +0000)]
sv_binutils: use ppc_opindex_t instead of unsigned char

2 years agosv_binutils: use BC instead of CRB
Dmitry Selyutin [Tue, 31 May 2022 19:21:15 +0000 (19:21 +0000)]
sv_binutils: use BC instead of CRB

2 years agosv_binutils: fix enum name in C code
Dmitry Selyutin [Tue, 31 May 2022 16:16:03 +0000 (16:16 +0000)]
sv_binutils: fix enum name in C code

2 years agosv_binutils: follow binutils PPC indentation
Dmitry Selyutin [Fri, 27 May 2022 12:17:24 +0000 (12:17 +0000)]
sv_binutils: follow binutils PPC indentation

2 years agosv_binutils: make C enums more readable
Dmitry Selyutin [Fri, 27 May 2022 12:16:23 +0000 (12:16 +0000)]
sv_binutils: make C enums more readable

2 years agosv_binutils: rename opsel to opindex as in binutils
Dmitry Selyutin [Fri, 27 May 2022 12:12:26 +0000 (12:12 +0000)]
sv_binutils: rename opsel to opindex as in binutils

2 years agoadd preamble on reg field encoding
Luke Kenneth Casson Leighton [Thu, 26 May 2022 17:00:33 +0000 (18:00 +0100)]
add preamble on reg field encoding

2 years agosplit out CR field encoding into function
Luke Kenneth Casson Leighton [Thu, 26 May 2022 16:49:36 +0000 (17:49 +0100)]
split out CR field encoding into function
add link to specification

2 years agoadd some code-comments to explain CR field svp64 EXTRA encoding
Luke Kenneth Casson Leighton [Thu, 26 May 2022 15:11:04 +0000 (16:11 +0100)]
add some code-comments to explain CR field svp64 EXTRA encoding

2 years agoRevert "svp64.py: simplify CR sv_extra and field processing"
Luke Kenneth Casson Leighton [Thu, 26 May 2022 14:55:03 +0000 (15:55 +0100)]
Revert "svp64.py: simplify CR sv_extra and field processing"

This reverts commit d56564910763a69f113615bedf94022da9457de5.

2 years agosvp64.py: always put leading zeroes for prefix
Dmitry Selyutin [Thu, 26 May 2022 14:23:07 +0000 (14:23 +0000)]
svp64.py: always put leading zeroes for prefix

2 years agosvp64.py: simplify CR sv_extra and field processing
Dmitry Selyutin [Thu, 26 May 2022 12:14:03 +0000 (12:14 +0000)]
svp64.py: simplify CR sv_extra and field processing

2 years agobit of a mess being sorted out
Luke Kenneth Casson Leighton [Fri, 20 May 2022 11:54:05 +0000 (12:54 +0100)]
bit of a mess being sorted out
1) update to this page was inconsistent: now fixed
   https://libre-soc.org/openpower/sv/bitmanip/
2) power_decoder.py bitsel for minor_22.csv had been set to (1,5) which
   is *only four bits* (LSB0 numbering, python-style) 1 2 3 4
   where what was actually needed was (1,6) to be bits (MSB0) 26..30
3) when converting to "ignore" format (previous: 0b00000 new 000000-)
   and adding the extra bit, (2) messed things up.
   bitsel has now been set to (0,6) which is bits 0 1 2 3 4 5
   aka (MSB0) 26..31 and the four instructions setvl/svremap/svshap/svstep
   set to 10011- and 011001 etc. as appropriate
4) the minor_22.csv entries for both svshape and svremap were set to
   Rc=1 mode which is NOT correct

astoundingly the unit tests all functioned correctly despite the above
errors.  now all corrected, unit test test_caller_setvl.py still functions

2 years agotemporarily revert opcode changes
Dmitry Selyutin [Thu, 19 May 2022 11:02:52 +0000 (11:02 +0000)]
temporarily revert opcode changes

b9ffa13 isatables/minor_22.csv: reflect a new XO bit
0e87485 power_decoder: reflect a new XO bit
e5564ad svp64.py: sync remap opcode
c968dab svp64.py: sync svshape opcode

2 years agoisatables/minor_22.csv: reflect a new XO bit
Dmitry Selyutin [Thu, 19 May 2022 07:58:09 +0000 (07:58 +0000)]
isatables/minor_22.csv: reflect a new XO bit

2 years agopower_decoder: reflect a new XO bit
Dmitry Selyutin [Thu, 19 May 2022 07:56:30 +0000 (07:56 +0000)]
power_decoder: reflect a new XO bit

2 years agosvp64.py: sync remap opcode
Dmitry Selyutin [Wed, 18 May 2022 20:01:40 +0000 (20:01 +0000)]
svp64.py: sync remap opcode

2 years agosvp64.py: sync svshape opcode
Dmitry Selyutin [Wed, 18 May 2022 19:39:22 +0000 (19:39 +0000)]
svp64.py: sync svshape opcode

2 years agoadd BM-Form and CRB-Form for bitmanip
Luke Kenneth Casson Leighton [Wed, 18 May 2022 10:32:37 +0000 (11:32 +0100)]
add BM-Form and CRB-Form for bitmanip

2 years agoadd to VA-Form, alter XO on SVM and SVRM Form
Luke Kenneth Casson Leighton [Mon, 16 May 2022 13:37:25 +0000 (14:37 +0100)]
add to VA-Form, alter XO on SVM and SVRM Form

2 years agoadd VA2-Form for Bitmanip ops [DRAFT]
Luke Kenneth Casson Leighton [Mon, 16 May 2022 12:42:36 +0000 (13:42 +0100)]
add VA2-Form for Bitmanip ops [DRAFT]

2 years agoadd L field to TLI-Form for grwvlut
Luke Kenneth Casson Leighton [Sun, 15 May 2022 22:49:29 +0000 (23:49 +0100)]
add L field to TLI-Form for grwvlut

2 years agocut/paste error resulted in Rc=0 twice, should be Rc=1
Luke Kenneth Casson Leighton [Sat, 14 May 2022 12:20:04 +0000 (13:20 +0100)]
cut/paste error resulted in Rc=0 twice, should be Rc=1

2 years agocut/paste error resulted in Rc=0 twice, should be Rc=1
Luke Kenneth Casson Leighton [Sat, 14 May 2022 12:18:16 +0000 (13:18 +0100)]
cut/paste error resulted in Rc=0 twice, should be Rc=1

2 years agoadd "DRAFT" in front of svfparith instruction descriptions
Luke Kenneth Casson Leighton [Thu, 12 May 2022 06:34:23 +0000 (07:34 +0100)]
add "DRAFT" in front of svfparith instruction descriptions

2 years agoadd ci
Jacob Lifshay [Thu, 12 May 2022 01:52:07 +0000 (18:52 -0700)]
add ci

2 years agoadd SimpleV-Form SVL/SVM/SVRM to svp64.py
Luke Kenneth Casson Leighton [Tue, 10 May 2022 09:55:22 +0000 (10:55 +0100)]
add SimpleV-Form SVL/SVM/SVRM to svp64.py

2 years agorename comments persistent bit on svremap
Luke Kenneth Casson Leighton [Tue, 10 May 2022 09:49:38 +0000 (10:49 +0100)]
rename comments persistent bit on svremap

2 years agocomments for setvl were the wrong bit-position
Luke Kenneth Casson Leighton [Mon, 9 May 2022 14:24:29 +0000 (15:24 +0100)]
comments for setvl were the wrong bit-position
not the actual fields (whew)

2 years agoupdate comments on sv.svstep
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:40:46 +0000 (14:40 +0100)]
update comments on sv.svstep

2 years agoremove sv.setvl but *not* sv.svstep
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:38:23 +0000 (14:38 +0100)]
remove sv.setvl but *not* sv.svstep

2 years agowhitespace
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:37:06 +0000 (14:37 +0100)]
whitespace

2 years agoRevert "remove appearance of supporting sv.setvl and sv.svstep"
Luke Kenneth Casson Leighton [Mon, 9 May 2022 13:35:22 +0000 (14:35 +0100)]
Revert "remove appearance of supporting sv.setvl and sv.svstep"

This reverts commit 7351a6051e032234cb52a0833f3eb2262023a775.

2 years agoremove appearance of supporting sv.setvl and sv.svstep
Luke Kenneth Casson Leighton [Sun, 8 May 2022 18:08:23 +0000 (19:08 +0100)]
remove appearance of supporting sv.setvl and sv.svstep

2 years agoadd code-comments explaining that setvl, svstep svremap and svshape are
Luke Kenneth Casson Leighton [Sun, 8 May 2022 12:00:43 +0000 (13:00 +0100)]
add code-comments explaining that setvl, svstep svremap and svshape are
all 32-bit *only* as they are *control* instructions not themselves
vector instructions

2 years agosv_binutils: do not index array entries
Dmitry Selyutin [Wed, 4 May 2022 16:02:57 +0000 (16:02 +0000)]
sv_binutils: do not index array entries

2 years agosv_binutils: update disclaimer
Dmitry Selyutin [Wed, 4 May 2022 14:32:12 +0000 (14:32 +0000)]
sv_binutils: update disclaimer

2 years agosv_binutils: whitespaces cleanup, another take
Dmitry Selyutin [Tue, 3 May 2022 17:00:18 +0000 (17:00 +0000)]
sv_binutils: whitespaces cleanup, another take

2 years agospace at end of lines
Luke Kenneth Casson Leighton [Tue, 3 May 2022 16:53:33 +0000 (17:53 +0100)]
space at end of lines

2 years agocode-comments on madded and divmod2du should say RS=RT+MAXVL now
Luke Kenneth Casson Leighton [Tue, 3 May 2022 10:31:00 +0000 (11:31 +0100)]
code-comments on madded and divmod2du should say RS=RT+MAXVL now

2 years agoproperly fix pagereader.py to parse markdown with indented comments
Luke Kenneth Casson Leighton [Tue, 3 May 2022 10:30:23 +0000 (11:30 +0100)]
properly fix pagereader.py to parse markdown with indented comments
these are supposed to be developer-hints rather than actually end up
in the pseudocode itself

2 years agoallow HTML comments to start with whitespace
Luke Kenneth Casson Leighton [Tue, 3 May 2022 08:49:28 +0000 (09:49 +0100)]
allow HTML comments to start with whitespace
this is very deliberate as these comments should not appear in the
pseudocode

2 years agoadd Rc to ternlogi
Jacob Lifshay [Tue, 3 May 2022 08:30:50 +0000 (01:30 -0700)]
add Rc to ternlogi

2 years agoformat code
Jacob Lifshay [Tue, 3 May 2022 08:28:58 +0000 (01:28 -0700)]
format code

2 years agoadd make generate
Jacob Lifshay [Tue, 3 May 2022 08:12:09 +0000 (01:12 -0700)]
add make generate

2 years agoadd svfixedarith.py to .gitignore
Jacob Lifshay [Tue, 3 May 2022 08:07:22 +0000 (01:07 -0700)]
add svfixedarith.py to .gitignore

2 years agofix syntax error
Jacob Lifshay [Tue, 3 May 2022 08:05:58 +0000 (01:05 -0700)]
fix syntax error

2 years agowhitespace cleanup
Luke Kenneth Casson Leighton [Mon, 2 May 2022 15:40:49 +0000 (16:40 +0100)]
whitespace cleanup