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Wesley W. Terpstra [Sat, 21 Jan 2017 06:38:27 +0000 (22:38 -0800)]
xilinx pcie: put buffers before the outputs to the controller
Wesley W. Terpstra [Fri, 20 Jan 2017 03:53:03 +0000 (19:53 -0800)]
mig: track change to Blind port API in rocket
Wesley W. Terpstra [Wed, 7 Dec 2016 21:21:20 +0000 (13:21 -0800)]
LazyModule: provide Parameters
This tracks PR #478 in rocketchip.
Wesley W. Terpstra [Wed, 7 Dec 2016 00:13:12 +0000 (16:13 -0800)]
xilinx pcie: bytes, not bits
This bug amazingly compiled correctly and ran correctly!
It was saved by the AXIFragmenter which turned the "narrow burst" into
individual beats that then got converted to 64b in TileLink land via
inspection of the mask bits.
The consequence is that AXI bus mastering proceeded at one word per
DDR round-trip. Now it is one cache line per DDR round-trip. When we
get L2 back in the design, it should really fly!
Wesley W. Terpstra [Sat, 3 Dec 2016 01:48:17 +0000 (17:48 -0800)]
RegMapFIFO: amoor.w can do thread-safe TX
Richard Xia [Wed, 30 Nov 2016 21:29:54 +0000 (13:29 -0800)]
Add /target to .gitignore.
SiFive [Tue, 29 Nov 2016 12:08:44 +0000 (04:08 -0800)]
Initial commit.
projects / sifive-blocks.git / log