Andreas Hansson [Mon, 10 Sep 2012 15:57:37 +0000 (11:57 -0400)]
Device: Update stats for PIO and PCI latency change
This patch merely updates the regression stats to reflect the change
in PIO and PCI latency.
Andreas Hansson [Mon, 10 Sep 2012 15:57:36 +0000 (11:57 -0400)]
Device: Bump PIO and PCI latencies to more reasonable values
This patch addresses a previously highlighted issue with the default
latencies used for PIO and PCI devices. The values are merely educated
guesses and might not represent the particular system you want to
model. However, the values in this patch are definitely far more
realistic than the previous ones.
In i8254xGBe, the writeConfig method is updated to use configDelay
instead of pioDelay.
A follow-up patch will update the regression stats.
Nilay Vaish [Sun, 9 Sep 2012 14:33:45 +0000 (09:33 -0500)]
se.py: support specifying multiple programs via command line
This patch allows for specifying multiple programs via command line. It also
adds an option for specifying whether to use of SMT. But SMT does not work for
the o3 cpu as of now.
Andreas Sandberg [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
sim: Update the SimObject documentation
Includes a small change in sim_object.cc that adds the name space to
the output stream parameter in serializeAll. Leaving out the name
space unfortunately confuses Doxygen.
Andreas Sandberg [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
sim: Remove the unused SimObject::regFormulas method
Simulation objects normally register derived statistics, presumably
what regFormulas originally was meant for, in regStats(). This patch
removes regRegformulas since there is no need to have a separate
method call to register formulas.
Ali Saidi [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
O3: Get rid of incorrect assert in RAS.
Ali Saidi [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
dev: Fix bifield definition in timer_cpulocal.hh
Bitfield definition in the local timer model for ARM had the bitfield
range numbers reversed which could lead to buggy behavior.
Ali Saidi [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
ARM: Fix the compiler and platform identification for building on ARM.
Ali Saidi [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
ARM: fix m5 op binary to properly convert 64bit operands
Matt Evans [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
ARM: Fix issue with with way MPIDR is read to include affinity levels.
The simple_bootloader checks for CPU0 in a manner incompatible with systems
actually using affinity levels -- just looking at MPIDR[7:0]. However, in
future we may wish to use real affinity levels and this method will be in danger
of matching several CPUs with affinity0 = 0.
Match affinity2 == affinity1 == affinity0 == 0 instead.
Ali Saidi [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
Igbe: Newer kernels seem to allow TSO headers and packet data to be in one desc
Implement some code we used to panic on as it actually does happen with the
e1000 driver in Linux 3.3+. We used to assume that a TSO header would never
be part of a larger payload, however it appears as though it now can be.
Djordje Kovacevic [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
CPU: O3-PipeView.py doesn't display the end of timelines.
Insts' timeline that stretches over multiple lines doesn't always get printed.
Krishnendra Nathella [Fri, 7 Sep 2012 19:20:53 +0000 (14:20 -0500)]
sim: add validation to make sure there is memory where we're loading the kernel
Ali Saidi [Fri, 7 Sep 2012 19:20:52 +0000 (14:20 -0500)]
loader: initialize all memory in the ObjectFile objects.
Some bare metal build flows seem to build binaries that we aren't necessarily
expecting. Initialize everything to 0, so we don't make any assumptions about
what is or isn't in the binary.
Ali Saidi [Fri, 7 Sep 2012 19:20:52 +0000 (14:20 -0500)]
ARM: Fix one of the timers used in the VExpress EMM platform.
Andreas Hansson [Fri, 7 Sep 2012 16:34:38 +0000 (12:34 -0400)]
Param: Transition to Cycles for relevant parameters
This patch is a first step to using Cycles as a parameter type. The
main affected modules are the CPUs and the Ruby caches. There are
definitely plenty more places that are affected, but this patch serves
as a starting point to making the transition.
An important part of this patch is to actually enable parameters to be
specified as Param.Cycles which involves some changes to params.py.
Joel Hestness [Thu, 6 Sep 2012 01:53:34 +0000 (20:53 -0500)]
stats: Update Ruby regressions for memory controller fix
Joel Hestness [Thu, 6 Sep 2012 01:51:41 +0000 (20:51 -0500)]
Ruby Memory Controller: Fix clocking
Jason Power [Tue, 28 Aug 2012 22:57:51 +0000 (17:57 -0500)]
Ruby: Correct DataBlock =operator
The =operator for the DataBlock class was incorrectly interpreting the class
member m_alloc. This variable stands for whether the assigned memory for the
data block needs to be freed or not by the class itself. It seems that the
=operator interpreted the variable as whether the memory is assigned to the
data block. This wrong interpretation was causing values not to propagate
to RubySystem::m_mem_vec_ptr. This caused major issues with restoring from
checkpoints when using a protocol which verified that the cache data was
consistent with the backing store (i.e. MOESI-hammer).
Andreas Hansson [Tue, 28 Aug 2012 18:30:33 +0000 (14:30 -0400)]
Clock: Add a Cycles wrapper class and use where applicable
This patch addresses the comments and feedback on the preceding patch
that reworks the clocks and now more clearly shows where cycles
(relative cycle counts) are used to express time.
Instead of bumping the existing patch I chose to make this a separate
patch, merely to try and focus the discussion around a smaller set of
changes. The two patches will be pushed together though.
This changes done as part of this patch are mostly following directly
from the introduction of the wrapper class, and change enough code to
make things compile and run again. There are definitely more places
where int/uint/Tick is still used to represent cycles, and it will
take some time to chase them all down. Similarly, a lot of parameters
should be changed from Param.Tick and Param.Unsigned to
Param.Cycles.
In addition, the use of curTick is questionable as there should not be
an absolute cycle. Potential solutions can be built on top of this
patch. There is a similar situation in the o3 CPU where
lastRunningCycle is currently counting in Cycles, and is still an
absolute time. More discussion to be had in other words.
An additional change that would be appropriate in the future is to
perform a similar wrapping of Tick and probably also introduce a
Ticks class along with suitable operators for all these classes.
Andreas Hansson [Tue, 28 Aug 2012 18:30:31 +0000 (14:30 -0400)]
Clock: Rework clocks to avoid tick-to-cycle transformations
This patch introduces the notion of a clock update function that aims
to avoid costly divisions when turning the current tick into a
cycle. Each clocked object advances a private (hidden) cycle member
and a tick member and uses these to implement functions for getting
the tick of the next cycle, or the tick of a cycle some time in the
future.
In the different modules using the clocks, changes are made to avoid
counting in ticks only to later translate to cycles. There are a few
oddities in how the O3 and inorder CPU count idle cycles, as seen by a
few locations where a cycle is subtracted in the calculation. This is
done such that the regression does not change any stats, but should be
revisited in a future patch.
Another, much needed, change that is not done as part of this patch is
to introduce a new typedef uint64_t Cycle to be able to at least hint
at the unit of the variables counting Ticks vs Cycles. This will be
done as a follow-up patch.
As an additional follow up, the thread context still uses ticks for
the book keeping of last activate and last suspend and this should
probably also be changed into cycles as well.
Andreas Hansson [Tue, 28 Aug 2012 18:30:27 +0000 (14:30 -0400)]
Port: Stricter port bind/unbind semantics
This patch tightens up the semantics around port binding and checks
that the ports that are being bound are currently not connected, and
similarly connected before unbind is called.
The patch consequently also changes the order of the unbind and bind
for the switching of CPUs to ensure that the rules are adhered
to. Previously the ports would be "over-written" without any check.
There are no changes in behaviour due to this patch, and the only
place where the unbind functionality is used is in the CPU.
Andreas Hansson [Tue, 28 Aug 2012 18:30:25 +0000 (14:30 -0400)]
Checker: Bump the realview-o3-checker regression
This patch bumps the stats for the realview-o3-checker after fixing
the checker CPU in the previous patch.
Andreas Hansson [Tue, 28 Aug 2012 18:30:24 +0000 (14:30 -0400)]
Checker: Fix checker CPU ports
This patch updates how the checker CPU handles the ports such that the
regressions will once again run without causing a panic.
A minor amount of tidying up was also done as part of this patch.
Andreas Hansson [Tue, 28 Aug 2012 18:30:22 +0000 (14:30 -0400)]
swig: Disable unused value warning with llvm 3.1 compilers
This patch disables a warning for unused values which causes problems
when compiling the swig-generated sources using recent llvm-based
compilers like llvm-gcc and clang.
Anthony Gutierrez [Tue, 28 Aug 2012 00:53:20 +0000 (20:53 -0400)]
sim: fix overflow check in simulate because Tick is now unsigned
Nilay Vaish [Mon, 27 Aug 2012 19:57:46 +0000 (14:57 -0500)]
Ruby: remove README.debugging and Decommissioning_note
These files were relevant when Ruby was part of GEMS. They are not required
any longer.
Nilay Vaish [Mon, 27 Aug 2012 06:14:46 +0000 (01:14 -0500)]
System: Remove redundant call to startupCPU
Nilay Vaish [Mon, 27 Aug 2012 06:00:55 +0000 (01:00 -0500)]
Ruby: Remove RubyEventQueue
This patch removes RubyEventQueue. Consumer objects now rely on RubySystem
or themselves for scheduling events.
Nilay Vaish [Mon, 27 Aug 2012 06:00:54 +0000 (01:00 -0500)]
Ruby Memory Vector: Allow more than 4GB of memory
The memory size variable was a 32-bit int. This meant that the size of the
memory was limited to 4GB. This patch changes the type of the variable to
64-bit to support larger memory sizes. Thanks to Raghuraman Balasubramanian
for bringing this to notice.
Nilay Vaish [Sat, 25 Aug 2012 20:49:07 +0000 (15:49 -0500)]
Regression: updates ruby.stats due to change in virtual network
Nilay Vaish [Sat, 25 Aug 2012 20:49:06 +0000 (15:49 -0500)]
MESI Protocol: Correct the virtual network in profile functions
The virtual network in a couple of places was incorrectly mentioned
as 3 in place of 1. This is being corrected.
Nilay Vaish [Sat, 25 Aug 2012 18:16:45 +0000 (13:16 -0500)]
MESI Coherence Protocol: Add copyright notice
Andreas Hansson [Wed, 22 Aug 2012 15:40:01 +0000 (11:40 -0400)]
DMA: Refactor the DMA device and align timing and atomic
This patch does a bunch of house-keeping updates on the DMA, including
indentation, and formatting, but most importantly breaks out the
response handling such that it can be shared between the atomic and
timing modes. It also removes a potential bug caused by the atomic
handling of responses only deleting the allocated request (pkt->req)
once the DMA action completes instead of doing so for every packet.
Before this patch, the handling of responses was near identical for
atomic and timing, but the code was simply duplicated. With this
patch, the handleResp method deals with the responses in both cases.
There are further updates to make after removing the NACKs, but that
will be part of a separate follow-up patch. This patch does not change
the behaviour of any regression.
Andreas Hansson [Wed, 22 Aug 2012 15:39:59 +0000 (11:39 -0400)]
Packet: Remove NACKs from packet and its use in endpoints
This patch removes the NACK frrom the packet as there is no longer any
module in the system that issues them (the bridge was the only one and
the previous patch removes that).
The handling of NACKs was mostly avoided throughout the code base, by
using e.g. panic or assert false, but in a few locations the NACKs
were actually dealt with (although NACKs never occured in any of the
regressions). Most notably, the DMA port will now never receive a NACK
and the backoff time is thus never changed. As a consequence, the
entire backoff mechanism (similar to a PCI bus) is now removed and the
DMA port entirely relies on the bus performing the arbitration and
issuing a retry when appropriate. This is more in line with e.g. PCIe.
Surprisingly, this patch has no impact on any of the regressions. As
mentioned in the patch that removes the NACK from the bridge, a
follow-up patch should change the request and response buffer size for
at least one regression to also verify that the system behaves as
expected when the bridge fills up.
Andreas Hansson [Wed, 22 Aug 2012 15:39:58 +0000 (11:39 -0400)]
Bridge: Remove NACKs in the bridge and unify with packet queue
This patch removes the NACKing in the bridge, as the split
request/response busses now ensure that protocol deadlocks do not
occur, i.e. the message-dependency chain is broken by always allowing
responses to make progress without being stalled by requests. The
NACKs had limited support in the system with most components ignoring
their use (with a suitable call to panic), and as the NACKs are no
longer needed to avoid protocol deadlocks, the cleanest way is to
simply remove them.
The bridge is the starting point as this is the only place where the
NACKs are created. A follow-up patch will remove the code that deals
with NACKs in the endpoints, e.g. the X86 table walker and DMA
port. Ultimately the type of packet can be complete removed (until
someone sees a need for modelling more complex protocols, which can
now be done in parts of the system since the port and interface is
split).
As a consequence of the NACK removal, the bridge now has to send a
retry to a master if the request or response queue was full on the
first attempt. This change also makes the bridge ports very similar to
QueuedPorts, and a later patch will change the bridge to use these. A
first step in this direction is taken by aligning the name of the
member functions, as done by this patch.
A bit of tidying up has also been done as part of the simplifications.
Surprisingly, this patch has no impact on any of the
regressions. Hence, there was never any NACKs issued. In a follow-up
patch I would suggest changing the size of the bridge buffers set in
FSConfig.py to also test the situation where the bridge fills up.
Andreas Hansson [Wed, 22 Aug 2012 15:39:56 +0000 (11:39 -0400)]
Port: Extend the QueuedPort interface and use where appropriate
This patch extends the queued port interfaces with methods for
scheduling the transmission of a timing request/response. The methods
are named similar to the corresponding sendTiming(Snoop)Req/Resp,
replacing the "send" with "sched". As the queues are currently
unbounded, the methods always succeed and hence do not return a value.
This functionality was previously provided in the subclasses by
calling PacketQueue::schedSendTiming with the appropriate
parameters. With this change, there is no need to introduce these
extra methods in the subclasses, and the use of the queued interface
is more uniform and explicit.
Andreas Hansson [Tue, 21 Aug 2012 09:50:03 +0000 (05:50 -0400)]
Device: Remove overloaded pio_latency parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.
The PciConfigAll now also uses a Param.Latency rather than a
Param.Tick. For backwards compatibility it still sets the pio_latency
to 1 tick. All the comments have also been updated to not state that
it is in simticks when it is not necessarily the case.
Andreas Hansson [Tue, 21 Aug 2012 09:49:43 +0000 (05:49 -0400)]
CPU: Remove overloaded function_trace_start parameter
This patch removes the overloading of the parameter, which seems both
redundant, and possibly incorrect.
The inorder CPU is particularly interesting as it uses a different
name for the parameter, and never make any use of it internally.
Andreas Hansson [Tue, 21 Aug 2012 09:49:24 +0000 (05:49 -0400)]
PacketQueue: Allow queuing in the same tick as desired send tick
This patch allows packets to be enqueued in the same tick as they are
intended to be sent. This does not imply they actually are sent that
tick, although that is possible.
This change is useful for module that use the queued ports primarly to
avoid handling the flow control involved in sending and retrying
packets.
Andreas Hansson [Tue, 21 Aug 2012 09:49:18 +0000 (05:49 -0400)]
EventManager: Remove test for NULL pointer in constructor
This patch tidies up the EventManager constructor and prunes a corner
case where the EventManager would initialise its eventq pointer to
NULL. This would cause segmentation faults on actual use and should
never happen.
Andreas Hansson [Tue, 21 Aug 2012 09:49:09 +0000 (05:49 -0400)]
Clock: Make Tick unsigned and remove UTick
This patch makes the Tick unsigned and removes the UTick typedef. The
ticks should never be negative, and there was only one major issue
with removing it, caused by the o3 CPU using a -1 as an initial value.
The patch has no impact on any regressions.
Andreas Hansson [Tue, 21 Aug 2012 09:49:01 +0000 (05:49 -0400)]
Clock: Move the clock and related functions to ClockedObject
This patch moves the clock of the CPU, bus, and numerous devices to
the new class ClockedObject, that sits in between the SimObject and
MemObject in the class hierarchy. Although there are currently a fair
amount of MemObjects that do not make use of the clock, they
potentially should do so, e.g. the caches should at some point have
the same clock as the CPU, potentially with a 1:n ratio. This patch
does not introduce any new clock objects or object hierarchies
(clusters, clock domains etc), but is still a step in the direction of
having a more structured approach clock domains.
The most contentious part of this patch is the serialisation of clocks
that some of the modules (but not all) did previously. This
serialisation should not be needed as the clock is set through the
parameters even when restoring from the checkpoint. In other words,
the state is "stored" in the Python code that creates the modules.
The nextCycle methods are also simplified and the clock phase
parameter of the CPU is removed (this could be part of a clock object
once they are introduced).
Andreas Hansson [Tue, 21 Aug 2012 09:48:52 +0000 (05:48 -0400)]
Checkpoint: Fix broken checkpointing functionality
This patch fixes the checkpointing by ensuring that the directory is
passer to the scriptCheckpoints function, and that the num_checkpoints
is not used before it is initialised.
Nilay Vaish [Sun, 19 Aug 2012 18:05:53 +0000 (13:05 -0500)]
Ruby Banked Array: add copyrights
Jason Power [Fri, 17 Aug 2012 04:39:36 +0000 (23:39 -0500)]
Ruby: Add RubySystem parameter to MemoryControl
This guarantees that RubySystem object is created before the MemoryController
object is created.
Nilay Vaish [Fri, 17 Aug 2012 04:45:21 +0000 (23:45 -0500)]
Alpha System: override startup(), instead of loadState()
Alpha System was overriding loadState() function to setup some functional
event. The system tried to read/write to memory before the Ruby memory had
unserialized the state. With this patch, Alpha System overrides the
startup() function, and sets up functional events in this function. This
works because startup() is called after Ruby memory system has unserialized
the memory state.
Anthony Gutierrez [Wed, 15 Aug 2012 14:38:08 +0000 (10:38 -0400)]
O3,ARM: fix some problems with drain/switchout functionality and add Drain DPRINTFs
This patch fixes some problems with the drain/switchout functionality
for the O3 cpu and for the ARM ISA and adds some useful debug print
statements.
This is an incremental fix as there are still a few bugs/mem leaks with the
switchout code. Particularly when switching from an O3CPU to a
TimingSimpleCPU. However, when switching from O3 to O3 cores with the ARM ISA
I haven't encountered any more assertion failures; now the kernel will
typically panic inside of simulation.
Anthony Gutierrez [Wed, 15 Aug 2012 14:38:07 +0000 (10:38 -0400)]
configs: add option for repeatedly switching back-and-forth between cpu types.
This patch adds a --repeat-switch option that will enable repeat core
switching at a user defined period (set with --switch-freq option).
currently, a switch can only occur between like CPU types. inorder CPU
switching is not supported.
*note*
this patch simply allows a config that will perform repeat switching, it
does not fix drain/switchout functionality. if you run with repeat switching
you will hit assertion failures and/or your workload with hang or die.
Ali Saidi [Wed, 15 Aug 2012 14:38:05 +0000 (10:38 -0400)]
stats: Update stats for syscall emulation Linux kernel changes.
Ali Saidi [Wed, 15 Aug 2012 14:38:04 +0000 (10:38 -0400)]
sysemul: bump all linux versions of for syscal emulation to 3.0.
New tool chains seem to be looking for kernel versions newer than what
this this was previously set to. Also take this opportunity to change
the hostname we report in uname to sim.gem5.org.
Jason Power [Fri, 10 Aug 2012 18:50:42 +0000 (13:50 -0500)]
Ruby: Clean up topology changes
This patch moves instantiateTopology into Ruby.py and removes the
mem/ruby/network/topologies directory. It also adds some extra inheritance to
the topologies to clean up some issues in the existing topologies.
Nilay Vaish [Wed, 8 Aug 2012 18:40:32 +0000 (13:40 -0500)]
System: set kernel to null, if unspecified.
Marc Orr [Tue, 7 Aug 2012 02:52:56 +0000 (19:52 -0700)]
syscall emulation: Enabled getrlimit and getrusage for x86.
Added/moved rlimit constants to base linux header file.
This patch is a revised version of Vince Weaver's earlier patch.
Steve Reinhardt [Mon, 6 Aug 2012 23:57:11 +0000 (16:57 -0700)]
SETranslatingPortProxy: fix bug in tryReadString()
Off-by-one loop termination meant that we were stuffing
the terminating '\0' into the std::string value, which
makes for difficult-to-debug string comparison failures.
Steve Reinhardt [Mon, 6 Aug 2012 23:55:34 +0000 (16:55 -0700)]
process: add progName() virtual function
This replaces a (potentially uninitialized) string
field with a virtual function so that we can have
a safe interface without requiring changes to the
eio code.
Steve Reinhardt [Mon, 6 Aug 2012 23:55:28 +0000 (16:55 -0700)]
syscall_emul: clean up open() code a bit.
Steve Reinhardt [Mon, 6 Aug 2012 23:52:49 +0000 (16:52 -0700)]
str: add an overloaded startswith() utility method
for various string types and use it in a few places.
Marc Orr [Mon, 6 Aug 2012 23:52:40 +0000 (16:52 -0700)]
syscall emulation: Clean up ioctl handling, and implement for x86.
Enable different whitelists for different OS/arch combinations,
since some use the generic Linux definitions only, and others
use definitions inherited from earlier Unix flavors on those
architectures.
Also update x86 function pointers so ioctl is no longer
unimplemented on that platform.
This patch is a revised version of Vince Weaver's earlier patch.
Nilay Vaish [Mon, 6 Aug 2012 23:14:32 +0000 (18:14 -0500)]
Simulation.py: move code related to checkpointing to functions
This patch moves the code related to checkpointing from the run() function to
several different functions. The aim is to make the code more manageable. No
functionality changes are expected, but since the code is kind of unruly, it
is possible that some change might have creeped in.
Nilay Vaish [Mon, 6 Aug 2012 23:14:31 +0000 (18:14 -0500)]
Config: change how cpu class is set
This changes the way in which the cpu class while restoring from a checkpoint
is set. Earlier it was assumed if cpu type with which to restore is not same
as the cpu type with the which to run the simulation, then the checkpoint
should be restored with the atomic cpu. This assumption is being dropped. The
checkpoint can now be restored with any cpu type, the default being atomic cpu.
Jason Power [Wed, 1 Aug 2012 22:07:34 +0000 (17:07 -0500)]
Ruby NetDest: add assert for bad element in netdest
Ali Saidi [Mon, 30 Jul 2012 16:11:25 +0000 (12:11 -0400)]
stats: revert pc-simple-timing-ruby-MESI_CMP_directory to before last update
Ali Saidi [Sat, 28 Jul 2012 17:48:04 +0000 (13:48 -0400)]
stats: fix some miss-committed changes from the icache change
Nathanael Premillieu [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
util: Fix issues with style checker.
Ali Saidi [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
stats: update stats for icache change not allowing dirty data
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:05 +0000 (16:08 -0400)]
dma: remove unused variable
this patch removes the actionInProgress field from the DmaPort class.
this variable is only defined and initiated in the ctor. it is never used.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
checker: make checker cpu id match its host's cpu id
when using the checker i ran into problems where an instruction reading the
cpu id register failed because the ids did not match, and hence, the result
of the instruction did not match. this patch ensures that the ids match so
this instruction does not fail. this problem only seemed to manifest itself
when multiple cores were in the system, either multi-core, or extra switched-
out cores present in the system.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
cache: don't allow dirty data in the i-cache
removes the optimization that forwards an exclusive copy to a requester on a
read, only for the i-cache. this optimization isn't necessary because we
typically won't be writing to the i-cache.
Anthony Gutierrez [Fri, 27 Jul 2012 20:08:04 +0000 (16:08 -0400)]
ARM: fix value of MISCREG_CTR returned by readMiscReg()
According to the A15 TRM the value of this register is as follows (assuming 16 word = 64 byte lines)
[31:29] Format - b100 specifies v7
[28] RAZ - b0
[27:24] CWG log2(max writeback size #words) - 0x4 16 words
[23:20] ERG log2(max reservation size #words) - 0x4 16 words
[19:16] DminLine log2(smallest dcache line #words) - 0x4 16 words
[15:14] L1Ip L1 index/tagging policy - b11 specifies PIPT
[13:4] RAZ -
b0000000000
[3:0] IminLine log2(smallest icache line #words) - 0x4 16 words
Andreas Hansson [Mon, 23 Jul 2012 13:32:22 +0000 (09:32 -0400)]
Config: Use clock option in se/fs script and pass to switch_cpus
This patch changes the se and fs script to use the clock option and
not simply set the CPUs clock to 2 GHz. It also makes a minor change
to the assignment of the switch_cpus clock to allow different clocks.
Andreas Hansson [Mon, 23 Jul 2012 13:32:19 +0000 (09:32 -0400)]
Bridge: Use EventWrapper instead of Event subclass for sendEvent
This class simply cleans up the code by making use of the EventWrapper
convenience class to schedule the sendEvent in the bridge ports.
Steve Reinhardt [Mon, 23 Jul 2012 04:39:12 +0000 (00:39 -0400)]
test: Update eio ref outputs due to recent changes
Actual stats updates covering period since original ref outputs
were clobbered.
Steve Reinhardt [Mon, 23 Jul 2012 04:33:05 +0000 (00:33 -0400)]
test: Restore eio ref files clobbered in rev
8800b05e1cb3.
Apparently Nate did a wholesale update of stats files using
a binary compiled without eio, resulting in broken refernce
outputs.
Nilay Vaish [Mon, 23 Jul 2012 01:31:24 +0000 (20:31 -0500)]
Regression: Update stats due to changes to x86 cpuid instruction
Nilay Vaish [Mon, 23 Jul 2012 01:31:23 +0000 (20:31 -0500)]
X86 CPUID: Return false if unknown processor family
Andreas Hansson [Sat, 21 Jul 2012 21:24:01 +0000 (17:24 -0400)]
Regression: Fix topologies path in failing pc-simple-timing-ruby
This patch updates the path to the Ruby topologies and thus fixes a
failing regression.
Steve Reinhardt [Thu, 19 Jul 2012 23:53:02 +0000 (16:53 -0700)]
Added tag stable_2012_06_28 for changeset
f75ee4849c40
Steve Reinhardt [Thu, 19 Jul 2012 23:51:01 +0000 (16:51 -0700)]
Added tag stable_2012_02_02 for changeset
549b72de8f72
Andreas Hansson [Thu, 12 Jul 2012 16:56:13 +0000 (12:56 -0400)]
Mem: Make SimpleMemory single ported
This patch changes the simple memory to have a single slave port
rather than a vector port. The simple memory makes no attempts at
modelling the contention between multiple ports, and any such
multiplexing and demultiplexing could be done in a bus (or crossbar)
outside the memory controller. This scenario also matches with the
ongoing work on a SimpleDRAM model, which will be a single-ported
single-channel controller that can be used in conjunction with a bus
(or crossbar) to create a multi-port multi-channel controller.
There are only very few regressions that make use of the vector port,
and these are all for functional accesses only. To facilitate these
cases, memtest and memtest-ruby have been updated to also have a
"functional" bus to perform the (de)multiplexing of the functional
memory accesses.
Andreas Hansson [Thu, 12 Jul 2012 16:56:11 +0000 (12:56 -0400)]
scons: Add LIBRARY_PATH from the user environment to Scons
This patch adds the LIBRARY_PATH from the users OS environment to
Scons build environment. This path is used when linking to search for
libraries, and this patch enables tcmalloc to be used during the build
even if it is not placed in the default search paths.
Nilay Vaish [Thu, 12 Jul 2012 13:39:20 +0000 (08:39 -0500)]
Regression: update ruby.stats file
Nilay Vaish [Thu, 12 Jul 2012 13:39:19 +0000 (08:39 -0500)]
Ruby: remove config information from ruby.stats
This patch removes printConfig() functions from all structures in Ruby.
Most of the information is already part of config.ini, and where ever it
is not, it would become in due course.
Nilay Vaish [Thu, 12 Jul 2012 13:39:18 +0000 (08:39 -0500)]
Ruby: remove some unused stuff from SLICC files
Brad Beckmann [Wed, 11 Jul 2012 19:21:04 +0000 (12:21 -0700)]
x86: added page size in bytes tlb entry function
Brad Beckmann [Wed, 11 Jul 2012 16:44:34 +0000 (09:44 -0700)]
ruby: improved DRAM reset comment
Brad Beckmann [Wed, 11 Jul 2012 05:51:55 +0000 (22:51 -0700)]
regress: ruby stat additions and config changes
Marc Orr [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
syscall emulation: Add the futex system call.
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
x86: logSize and lruSeq are now optional ckpt params
Steve Reinhardt [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
Add hook to call map() on Process from python.
This enables configuration scripts to set up mappings
from process virtual addresses to specific physical
addresses in SE mode. This feature is needed to
support modeling of user-accessible memories or
devices in SE mode, avoiding the complexities of FS
mode and the need to write a device driver.
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed fatal print statement
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: remove the cpu assumptions for the random tester
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
# User Brad Beckmann <Brad.Beckmann@amd.com>
ruby: fixed msgptr print call
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
imported patch jason/slicc-external-structure-fix
Brad Beckmann [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: banked cache array resource model
This patch models a cache as separate tag and data arrays. The patch exposes
the banked array as another resource that is checked by SLICC before a
transition is allowed to execute. This is similar to how TBE entries and slots
in output ports are modeled.
Joel Hestness [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: tag and data cache access support
Updates to Ruby to support statistics counting of cache accesses. This feature
serves multiple purposes beyond simple stats collection. It provides the
foundation for ruby to model the cache tag and data arrays as physical
resources, as well as provide the necessary input data for McPAT power
modeling.
Nuwan Jayasena [Wed, 11 Jul 2012 05:51:54 +0000 (22:51 -0700)]
ruby: adds reset function to Ruby memory controllers
Nuwan Jayasena [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
ruby: memory controllers now inherit from an abstract "MemoryControl" class
Brad Beckmann [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
cpu: added assertions to ensure the correct proxies are used
Brad Beckmann [Wed, 11 Jul 2012 05:51:53 +0000 (22:51 -0700)]
ruby: changes how Topologies are created
Instead of just passing a list of controllers to the makeTopology function
in src/mem/ruby/network/topologies/<Topo>.py we pass in a function pointer
which knows how to make the topology, possibly with some extra state set
in the configs/ruby/<protocol>.py file. Thus, we can move all of the files
from network/topologies to configs/topologies. A new class BaseTopology
is added which all topologies in configs/topologies must inheirit from and
follow its API.
--HG--
rename : src/mem/ruby/network/topologies/Crossbar.py => configs/topologies/Crossbar.py
rename : src/mem/ruby/network/topologies/Mesh.py => configs/topologies/Mesh.py
rename : src/mem/ruby/network/topologies/MeshDirCorners.py => configs/topologies/MeshDirCorners.py
rename : src/mem/ruby/network/topologies/Pt2Pt.py => configs/topologies/Pt2Pt.py
rename : src/mem/ruby/network/topologies/Torus.py => configs/topologies/Torus.py