radeonsi: store compute local_size into tgsi_shader_info

This is kinda a hack, but it's enough for the shader cache.

radeonsi: unify duplicated code for initial shader compilation

ac: set +auto-waitcnt-before-barrier when needed

This removes useless s_waitcnt before barriers.
Only radeonsi uses this function.

radeonsi/gfx9: insert the barrier between merged shaders inside the if block

gallium: plumb invariant output attrib thru TGSI

Add support for glsl 'invariant' modifier for output data declarations.
Gallium drivers that use TGSI serialization currently loose invariant
modifiers in glsl shaders.

v2: use boolean for invariant instead of unsigned.

Tested: chromiumos on qemu with virglrenderer.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

intel/fs: Build 32-wide FS shaders.

Co-authored-by: Jason Ekstrand <jason@jlekstrand.net>

intel/anv,blorp,i965: Implement the SKL 16x MSAA SIMD32 workaround

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

intel/fs: Add fields to wm_prog_data for SIMD32 dispatch

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix nir_intrinsic_load_helper_invocation for SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix fs_builder::sample_mask_reg() for 32-wide FS dispatch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix Gen6+ interpolation setup for SIMD32

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Get rid of MOV_DISPATCH_TO_FLAGS

We can just emit the MOV in the two places where we use this.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Emit MOV_DISPATCH_TO_FLAGS once for the centroid workaround

There's no reason for us to emit it a pile of times and then have a
whole pass to clean it up.  Just emit it once like we really want.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Generalize the unlit centroid workaround

This generalizes the unlit centroid workaround so it's less code and now
supports SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix sample id setup for SIMD32.

v2 (Jason Ekstrand):
 - Disallow gl_SampleId in SIMD32 on gen7

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix Gen7 compressed source region alignment restriction for SIMD32

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Implement 32-wide FS payload setup on Gen6+

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Extend thread payload layout to SIMD32

And handle 32-wide payload register reads in fetch_payload_reg().

v2 (Jason Ekstrand);
 - Fix some whitespace and brace placement

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Wrap FS payload register look-up in a helper function.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Use fs_regs instead of brw_regs in the unlit centroid workaround

While we're here, we change to using horiz_offset() instead of abusing
half().

v2 (Jason Ekstrand):
 - Use horiz_offset() instead of half()

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Simplify fs_visitor::emit_samplepos_setup

The original code manually handled splitting the MOVs to 8-wide to
handle various regioning restrictions.  Now that we have a SIMD width
splitting pass that handles these things, we can just emit everything at
the full width and let the SIMD splitting pass handle it.  We also now
have a useful "subscript" helper which is designed exactly for the case
where you want to take a W type and read it as a vector of Bs so we may
as well use that too.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Add plumbing for shader time in 32-wide FS dispatch mode.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Disable opt_sampler_eot() in 32-wide dispatch.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Emit LINE+MAC for LINTERP with unaligned coordinates

On g4x through Sandy Bridge, src1 (the coordinates) of the PLN
instruction is required to be an even register number.  When it's odd
(which can happen with SIMD32), we have to emit a LINE+MAC combination
instead.  Unfortunately, we can't just fall through to the gen4 case
because the input registers are still set up for PLN which lays out the
four src1 registers differently in SIMD16 than LINE.

v2 (Jason Ekstrand):
 - Take advantage of both accumulators and emit LINE LINE MAC MAC
   (Based on a patch from Francisco Jerez)
 - Unify the gen4 and gen4x-6 cases using a loop

v3 (Jason Ekstrand):
 - Don't unify gen4 with gen4x-6 as this turns out to be more fragile
   than first thought without reworking the gen4 barycentric coordinate
   layout.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Mark LINTERP opcode as writing accumulator on platforms without PLN

When we don't have PLN (gen4 and gen11+), we implement LINTERP as either
LINE+MAC or a pair of MADs.  In both cases, the accumulator is written
by the first of the two instructions and read by the second.  Even
though the accumulator value isn't actually ever used from a logical
instruction perspective, it is trashed so we need to make the scheduler
aware.  Otherwise, the scheduler could end up re-ordering instructions
and putting a LINTERP between another an instruction which writes the
accumulator and another which tries to use that result.

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Rework INTERPOLATE_AT_PER_SLOT_OFFSET

This reworks INTERPOLATE_AT_PER_SLOT_OFFSET to work more like an ALU
operation and less like a send.  This is less code over-all and, as a
side-effect, it now properly handles execution groups and lowering so
SIMD32 support just falls out.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Add the group to the flag subreg number on SNB and older

We want consistent behavior in the meaning of the flag_subreg field
between SNB and IVB+.

v2 (Jason Ekstrand):
 - Add some extra commentary

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix FB read header setup for SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix logical FB write lowering for SIMD32

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix FB write message control codegen for SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Don't enable dual source blend if no outputs are written

This prevents a crash in some arb_enhanced_layouts tests that would be
caused by the next commit.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix codegen of FS_OPCODE_SET_SAMPLE_ID for SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/eu: Fix pixel interpolator queries for SIMD32.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Disable SIMD32 dispatch for fragment shaders with discard.

Current discard handling requires dedicating the second flag register to
discard.  However, control-flow in SIMD32 requires both flag registers
so it's incompatible with the current discard handling.  Just don't
support SIMD32+discard for now.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Disable SIMD32 dispatch on Gen4-6 with control flow

The hardware's control flow logic is 16-wide so we're out of luck
here.  We could, in theory, support SIMD32 if we know the control-flow
is uniform but we don't have that information at this point.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Split instructions low to high in lower_simd_width

Commit 0d905597f fixed an issue with the placement of the zip and unzip
instructions.  However, as a side-effect, it reversed the order in which
we were emitting the split instructions so that they went from high
group to low instead of low to high.  This is fine for most things like
texture instructions and the like but certain render target writes
really want to be emitted low to high.  This commit just switches the
order back around to be low to high.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Fixes: 0d905597f "intel/fs: Be more explicit about our placement of [un]zip"

intel/fs: Rework KSP data to be SIMD width-based

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/compiler: Add and use helpers for working with KSP indices

The pixel shader dispatch table is kind-of a confusing mess.  This adds
some helpers for dealing with it and for easily extracting the correct
data from wm_prog_data.

Reviewed-by: Matt Turner <mattst88@gmail.com>

i965: Re-arrange shader kernel setup in WM state

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Remove program key argument from generator.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Set up FB write message headers in the visitor

Doing instruction header setup in the generator is awful for a number
of reasons.  For one, we can't schedule the header setup at all.  For
another, it means lots of implied writes which the instruction scheduler
and other passes can't properly read about.  The second isn't a huge
problem for FB writes since they always happen at the end.  We made a
similar change to sampler handling in ff4726077d86.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix implied_mrf_writes() for headerless FB writes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Fix fs_inst::flags_written() for Gen4-5 FB writes.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/eu: Return new instruction to caller from brw_fb_WRITE().

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Pull FB write implied headers from src[0]

Now that we have the implied header in src[0] for tracking purposes, we
may as well use it in the generator.  This makes things a tiny bit more
general.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: Properly track implied header regs read by FB writes

The FB write opcode on gen4-5 does implied copies from g0 and g1 to the
message payload.  With this commit, we start tracking that as part of
the IR by having the FB write read from g0-1.

Reviewed-by: Matt Turner <mattst88@gmail.com>

intel/fs: FS_OPCODE_REP_FB_WRITE has side effects

It doesn't matter since we don't ever run replicated write shaders
through the optimizer but it's good to be complete.

Reviewed-by: Matt Turner <mattst88@gmail.com>

docs: Add news item for mesa 18.1.2

Which I forgot to do when 18.1.2 came out.

Signed-off-by: Dylan Baker <dylan.c.baker@intel.com>

nvc0: remove magic values in nve4_set_tex_handles()

With this commit, things no longer break if NVC0_CB_AUX_TEX_INFO is
changed to anything other than 0x20.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>

nvc0/ir: fix TargetNVC0::insnCanLoadOffset()

Previously, TargetNVC0::insnCanLoadOffset() returned whether the offset
could be set to a specific value. The IndirectPropagation pass expected
it to return whether the offset could be increased by a specific value,
which is what TargetNV50::insnCanLoadOffset() does.

Fixes: 37b67db6ae34fb6586d640a7a1b6232f091dd812
("nvc0/ir: be careful about propagating very large offsets into const load")

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Signed-off-by: Karol Herbst <kherbst@redhat.com>

swr/rast: Updating code style based on current clang-format rules

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Fix addPassesToEmitFile usage with llvm-7.0.

Fix build error after llvm-7.0svn r332881 ("CodeGen: Add a dwo output
file argument to addPassesToEmitFile and hook it up to dwo output.").

  CXX      rasterizer/jitter/libmesaswr_la-JitManager.lo
rasterizer/jitter/JitManager.cpp:368:93: error: too few arguments to function call, expected at least 4, have 3
        pTarget->addPassesToEmitFile(*pMPasses, filestream, TargetMachine::CGFT_AssemblyFile);
        ~~~~~~~~~~~~~~~~~~~~~~~~~~~~                                                        ^

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Handling removed LLVM intrinsics in trunk

- Functionality replaced with emulated intrinsics
- Fixes Bug 106558

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Adding SCATTERPS functionality to BuilderGfxMem

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

swr/rast: Adding Read/Write specifier to TranslateGfxAddress stack

- Removing unused generic translate function
- Requiring read/write specifier in builder_gfx_mem

Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>

gallium: Fix automake for Android (v2)

Chromium OS uses Autotools and pkg-config when building Mesa for
Android. The gallium drivers were failing to find the headers and
libraries for zlib and Android's libbacktrace.

v2:
  - Don't add a check for zlib.pc. configure.ac already checks for
    zlib.pc elsewhere. [for tfiga]
  - Check for backtrace.pc separately from the other Android libs.
    [for tfiga]

Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>

glsl: skip comparison opt when adding vars of different size

The spec allows adding scalars with a vector or matrix. In this case
the opt was losing swizzle and size information.

This fixes a bug with Doom (2016) shaders.

Fixes: 34ec1a24d61f ("glsl: Optimize (x + y cmp 0) into (x cmp -y).")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>

Revert "anv: Print the actual enum for ignored structure types"

This reverts commit fda7014c35e5f5dfa26f078ad0512d13ead8b717.  It was
hitting an unreachable when the sType was unknown.

anv: Print the actual enum for ignored structure types

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

i965/bufmgr: Use the correct argument order for bo_alloc_internal

The memzone and flags parameters were accidentally flipped in the call
from brw_bo_alloc_tiled_2d.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

vulkan/wsi_common_display: Return SURFACE_LOST for fatal DRM errors

Instead of encouraging the client to re-create the swapchain and keep
going with an OUT_OF_DATE error, tell the client that further use of
the current surface will not succeed as the associated kernel objects
are no longer valid.

In particular, when a DRM lease is revoked, then the client needs to
get another lease and create a new surface for that.

Signed-off-by: Keith Packard <keithp@keithp.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

glsl: Make sure that packed varyings reflect always_active_io properly.

The always_active_io flag was only set according to the first variable
that got packed in, so NIR io compaction would end up compacting XFB
varyings that shouldn't move at that point.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

v3d: Fix Z clipping when viewport.scale[2] is negative.

Fixes:
dEQP-GLES3.functional.shaders.builtin_variable.depth_range_fragment
dEQP-GLES3.functional.shaders.builtin_variable.depth_range_vertex

v3d: Convert a bunch of our "minus one" fields over to the new XML attr.

This fixes up their formatting for CLIF files and makes the code more
legible.

v3d: Add pack/unpack/decode support for fields with a "- 1" modifier.

Right now, we name these fields as "field name minus one" so that your C
code obviously states what the value should be.  However, it's easy enough
to handle at the codegen level with another little XML attribute, meaning
less C code and easier-to-read values in CLIF dumping and gdb as well.

(The actual CLIF format for simulator and FPGA replay takes in
pre-minus-one values, so we need it there too).

i965: small cleanup in blorp debug printing output (trivial)

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: add a space between headers and source (trivial)

There used to be one and it looks like it was removed by eb63640c1d.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

features.txt: mark some extensions as done

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

mesa: Return number of result bits for GL_ANY_SAMPLES_PASSED_CONSERVATIVE

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106986
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

radv: use separate bind points for the dynamic buffers

The Vulkan spec says:

   "pipelineBindPoint is a VkPipelineBindPoint indicating whether
    the descriptors will be used by graphics pipelines or compute
    pipelines. There is a separate set of bind points for each of
    graphics and compute, so binding one does not disturb the other."

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove unused 'predicated' parameter from some functions

It's always false.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

virgl: add ARB_texture_view support

Reviewed-By: Gert Wollny <gert.wollny@collabora.com>

nir/opt_if: Remove unneeded phis if we make progress

Now that SSA values can be derefs and they have special rules, we have
to be a bit more careful about our LCSSA phis.  In particular, we need
to clean up in case LCSSA ended up creating a phi node for a deref.
This fixes validation issues with some Vulkan CTS tests with the new
deref instructions.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

radv: emit PIPELINESTAT_{START,STOP} events for pipeline stats queries

Ported from RadeonSI.
This appears to fix some random fails with:
dEQP-VK.query_pool.statistics_query.*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

glsl: serialize data from glTransformFeedbackVaryings

While XFB has been enabled for cache, we did not serialize enough
data for the whole API to work (such as glGetProgramiv).

Fixes: 6d830940f7 "Allow shader cache usage with transform feedback"
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=106907
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

radv: enable VK_EXT_shader_stencil_export

The driver already supports exporting the stencil value.

The following CTS test now pass:
dEQP-VK.pipeline.shader_stencil_export.op_replace

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: ignore pInheritanceInfo for primary command buffers

From the Vulkan spec:
"If this is a primary command buffer, then this value is ignored."

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

i965/gen6/gs: Handle case where a GS doesn't allocate VUE

We can not use the VUE Dereference flags combination for EOT
message under ILK and SNB because the threads are not initialized
there with initial VUE handle unlike Pre-IL.
So to avoid GPU hangs on SNB and ILK we need
to avoid usage of the VUE Dereference flags combination.
(Was tested only on SNB but according to the specification
SNB Volume 2 Part 1: 1.6.5.3, 1.6.5.6
the ILK must behave itself in the similar way)

v2: Approach to fix this issue was changed.
Instead of different EOT flags in the program end
we will create VUE every time even if GS produces no output.

v3: Clean up the patch.
Signed-off-by: Andrii Simiklit <andrii.simiklit@globallogic.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105399
CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Tested-by: Mark Janes <mark.a.janes@intel.com>

radeon: duplicate cmask surface for now.

The radeon winsys isn't linked against the ac code, I have vague
memories of this causing some problems before, for now fix the build
but just duplicating the code.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>

radeonsi: rename r600_transfer -> si_transfer

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: properly set cmask_buffer in si_reallocate_texture_inplace

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: remove redundant si_texture::cmask_size

cmask_buffer and surface.cmask_size can replace its role.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: inline struct r600_cmask_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: move CMASK size computation into ac_surface

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

ac/surface: move cmask_size/alignment into radeon_surf

cmask_size is changed to uint32_t because it can't be greater than 4GB.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename r600_surface -> si_surface

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename r600_memory_object -> si_memory_object

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: remove unused r600_memory_object::offset

The real offset is passed through resource_from_memobj.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: unify duplicated texture_from_handle & texture_from_memobj

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: reorder and initialize more fields in si_reallocate_texture_inplace

Some fields shouldn't be initialized, like framebuffers_bound and other stats.
It's hopefully complete now.

Cc: 18.1 <mesa-stable@lists.freedesktop.org>

radeonsi: stop using lp_build_emit_llvm_unary/binary

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: stop using lp_build_alloc

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: use gallivm less

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: stop using lp_bld_intr.h

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: remove last uses of lp_build_context::undef

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: stop using lp_bld_arit.h

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: stop using lp_build_gather_values

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: clean up some #includes

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: clean up passing the is_monolithic flag for compilation

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

egl/android: Add DRM node probing and filtering

This patch both adds support for probing & filtering DRM nodes
and switches away from using the GRALLOC_MODULE_PERFORM_GET_DRM_FD
gralloc call.

Currently the filtering is based just on the driver name,
and the desired name is supplied using the "drm.gpu.vendor_name"
Android property.

Signed-off-by: Robert Foss <robert.foss@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>