mesa.git
4 years agodocs: add new features for RADV/ACO.
Daniel Schürmann [Wed, 29 Jan 2020 14:30:25 +0000 (15:30 +0100)]
docs: add new features for RADV/ACO.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3627>

4 years agoradv: refactor physical device properties
Samuel Pitoiset [Wed, 29 Jan 2020 14:02:26 +0000 (15:02 +0100)]
radv: refactor physical device properties

Based on ANV. This removes a bunch of duplicated code for properties.

Fixes: 1b8d99e2885 ("radv: bump conformance version to 1.2.0.0")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3626>

4 years agofreedreno: remove flush-queue
Rob Clark [Wed, 22 Jan 2020 00:15:28 +0000 (16:15 -0800)]
freedreno: remove flush-queue

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: add gmem_lock
Rob Clark [Tue, 21 Jan 2020 23:59:22 +0000 (15:59 -0800)]
freedreno: add gmem_lock

The gmem state is split out now, so it does not require synchronization.
But gmem rendering still accesses vsc state from the context.

TODO maybe there is a better way?  For gen's that don't do vsc resizing,
this is probably easier.. but for a6xx there isn't really a great
position for more fine grained locking.  Maybe it doesn't matter since
in practice the lock shouldn't be contended.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: add gmem state cache
Rob Clark [Tue, 21 Jan 2020 22:28:06 +0000 (14:28 -0800)]
freedreno: add gmem state cache

Which also has the benefit of getting rid of fd_context::gmem.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: get GMEM state from batch
Rob Clark [Tue, 21 Jan 2020 19:27:14 +0000 (11:27 -0800)]
freedreno: get GMEM state from batch

Prep work to reduce churn in next patch.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno/a2xx: constify gmem state
Rob Clark [Sat, 25 Jan 2020 19:18:32 +0000 (11:18 -0800)]
freedreno/a2xx: constify gmem state

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno/a3xx: constify gmem state
Rob Clark [Sat, 25 Jan 2020 19:17:43 +0000 (11:17 -0800)]
freedreno/a3xx: constify gmem state

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno/a4xx: constify gmem state
Rob Clark [Sat, 25 Jan 2020 19:16:35 +0000 (11:16 -0800)]
freedreno/a4xx: constify gmem state

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno/a5xx: constify gmem state
Rob Clark [Sat, 25 Jan 2020 19:14:41 +0000 (11:14 -0800)]
freedreno/a5xx: constify gmem state

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno/a6xx: constify gmem state
Rob Clark [Sat, 25 Jan 2020 19:13:49 +0000 (11:13 -0800)]
freedreno/a6xx: constify gmem state

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: constify fd_vsc_pipe
Rob Clark [Sat, 25 Jan 2020 19:10:38 +0000 (11:10 -0800)]
freedreno: constify fd_vsc_pipe

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: constify fd_tile
Rob Clark [Sat, 25 Jan 2020 19:04:58 +0000 (11:04 -0800)]
freedreno: constify fd_tile

In a following patch, when we cache the gmem state, we will want to
treat the gmem state as immuatable.  So start converting things to
const to make this more clear.. fd_tile is a good place to start.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: consolidate GMEM state
Rob Clark [Tue, 21 Jan 2020 18:47:45 +0000 (10:47 -0800)]
freedreno: consolidate GMEM state

The tile and vsc_pipe arrays are really part of the GMEM configuration.
So pull these out of fd_context and into fd_gmem_stateobj.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agofreedreno: extract vsc pipe bo from GMEM state
Rob Clark [Tue, 21 Jan 2020 18:34:29 +0000 (10:34 -0800)]
freedreno: extract vsc pipe bo from GMEM state

Prep work for reorganizing GMEM state and extracting out of fd_context.
The vsc pipe bo was the one thing that doesn't change with GMEM/tile
config.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3503>

4 years agoturnip: remove unused descriptor state dirty
Alejandro Piñeiro [Wed, 29 Jan 2020 13:20:19 +0000 (14:20 +0100)]
turnip: remove unused descriptor state dirty

It was only used to be initialized to zero. Not even updated as
descriptor sets are bind.

As far as I understand, setting the bit TU_CMD_DIRTY_DESCRIPTOR_SET on
tu_cmd_state.dirty is used instead.

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3624>

4 years agoaco: Fix the meaning of is_atomic.
Timur Kristóf [Wed, 29 Jan 2020 12:28:58 +0000 (13:28 +0100)]
aco: Fix the meaning of is_atomic.

Previously, is_atomic really meant "is not atomic", contrary to its name.
This commit fixes it to mean what one would think it means.

Fixes: 69bed1c9186c3e24ad54089218d58c5f7b83befe
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3618>

4 years agoiris: Support multiple chained batches.
Kenneth Graunke [Tue, 14 Jan 2020 00:14:24 +0000 (16:14 -0800)]
iris: Support multiple chained batches.

There was never much point in artificially limiting chaining to two
batches - we can trivially support arbitrary length chains.

Currently, we should only ever have 1 or 2, but this may change.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>

4 years agoiris: Make iris_emit_default_l3_config pull devinfo from the batch
Kenneth Graunke [Tue, 3 Sep 2019 15:03:13 +0000 (08:03 -0700)]
iris: Make iris_emit_default_l3_config pull devinfo from the batch

No need to pass it, we can just use batch->screen->devinfo.

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>

4 years agoiris: Drop 'engine' from iris_batch.
Kenneth Graunke [Tue, 3 Sep 2019 14:19:32 +0000 (07:19 -0700)]
iris: Drop 'engine' from iris_batch.

For the moment, everything is I915_EXEC_RENDER, so this isn't necessary.
But even should that change, I don't think we want to handle multiple
engines in this manner.

Nowadays, we have batch->name (IRIS_BATCH_RENDER, IRIS_BATCH_COMPUTE,
possibly an IRIS_BATCH_BLIT for blorp batches someday), which describes
the functional usage of the batch.  We can simply check that and select
an engine for that class of work (assuming there ever is more than one).

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3613>

4 years agotu: Fix binning address setup after pack macros change.
Eric Anholt [Wed, 29 Jan 2020 00:00:45 +0000 (16:00 -0800)]
tu: Fix binning address setup after pack macros change.

This fixes a regression in "vkcube -m headless" rendering, but upsettingly
none of my CTS tests I've been using.

Fixes: 59f29fc845ce ("turnip: Convert the rest of tu_cmd_buffer.c over to the new pack macros.")
Caught-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3609>

4 years agoturnip: Enable occlusionQueryPrecise
Brian Ho [Tue, 28 Jan 2020 22:18:27 +0000 (17:18 -0500)]
turnip: Enable occlusionQueryPrecise

This commit enables the occlusionQueryPrecise feature. No additonal
work is required as occlusion queries are already implemented to
track exact sample counts.

Also enables a number of extra tests on the Vulkan CTS.

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3605>

4 years agoaco: simplify gathering of MIMG address components
Daniel Schürmann [Thu, 23 Jan 2020 18:12:55 +0000 (19:12 +0100)]
aco: simplify gathering of MIMG address components

This patch has a slight effect on pipelinedb:
Totals from affected shaders:
SGPRS: 23616 -> 21504 (-8.94 %)
VGPRS: 15088 -> 14444 (-4.27 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 662660 -> 664600 (0.29 %) bytes
LDS: 49 -> 49 (0.00 %) blocks
Max Waves: 3079 -> 3204 (4.06 %)

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>

4 years agoaco: simplify adjust_sample_index_using_fmask() & get_image_coords()
Daniel Schürmann [Thu, 23 Jan 2020 14:38:53 +0000 (15:38 +0100)]
aco: simplify adjust_sample_index_using_fmask() & get_image_coords()

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>

4 years agoaco: fix register allocation with multiple live-range splits
Daniel Schürmann [Tue, 21 Jan 2020 11:11:12 +0000 (12:11 +0100)]
aco: fix register allocation with multiple live-range splits

This patch fixes register allocation if multiple live-range splits
occur to the same variable within one instruction.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>

4 years agoaco: reorder VMEM operands in ACO IR
Daniel Schürmann [Thu, 16 Jan 2020 15:54:35 +0000 (16:54 +0100)]
aco: reorder VMEM operands in ACO IR

For all VMEM instructions, the resource constant is now
in operands[0]. For MIMG instructions, the sampler shares
operands[1] with write data in case this instruction writes memory.
Moving the VADDR to be the last operand for MIMG is the first step to
support Navi NSA encoding.

Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3602>

4 years agonir: Make nir_deref_path_init skip trivial casts
Caio Marcelo de Oliveira Filho [Wed, 15 Jan 2020 19:51:58 +0000 (11:51 -0800)]
nir: Make nir_deref_path_init skip trivial casts

In a NIR generated using SPIR-V initializers to variables, copy
propagation can end up transforming

    vec1 32 ssa_33 = deref_var &@1 (shared mat2x4)
    vec1 32 ssa_35 = mov ssa_33
    vec1 32 ssa_7 = deref_cast (mat2x4 *)ssa_35 (shared mat2x4)  /* ptr_stride=0 */

into

    vec1 32 ssa_33 = deref_var &@1 (shared mat2x4)
    vec1 32 ssa_7 = deref_cast (mat2x4 *)ssa_33 (shared mat2x4)  /* ptr_stride=0 */

Before the optimization, the "head" of a path of deref that uses ssa_7
will be the cast.  After, it will be the variable in ssa_33.  Since
the types are the same, this is a trivial cast that would be picked up
by nir_opt_deref.

If we need to compare such deref-chain after optimization with another
deref-chain for the same variable, the compare function will get
confused by the cast in the middle.

One alternative would be to add nir_opt_deref to places that compare
derefs, but that might not scale well, so skip the trivial casts when
generating the paths instead.

Motivated by the discussion in
https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3047#note_383660.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3420>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3420>

4 years agoaco: fix exec mask consistency issues
Rhys Perry [Mon, 20 Jan 2020 17:40:13 +0000 (17:40 +0000)]
aco: fix exec mask consistency issues

There seems to be more, these are just the ones found in
Detroit: Become Human shaders.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: parallelcopy exec mask before s_wqm
Rhys Perry [Mon, 20 Jan 2020 16:22:56 +0000 (16:22 +0000)]
aco: parallelcopy exec mask before s_wqm

It can be used later and we want any uses to not be fixed to exec, so it's
definition can't be fixed to exec because of how exec masks interact with
register demand calculation.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: fill reg_demand with sensible information in add_coupling_code()
Rhys Perry [Mon, 20 Jan 2020 15:57:21 +0000 (15:57 +0000)]
aco: fill reg_demand with sensible information in add_coupling_code()

process_block() will use this to determine the register demand of the
before the current instruction. Previously, it was filled with zeroes
which could result in process_block() only using the register demand
of after the current instruction.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: improve assertion at the end of spiller
Rhys Perry [Fri, 10 Jan 2020 16:16:43 +0000 (16:16 +0000)]
aco: improve assertion at the end of spiller

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: set exec_potentially_empty after continues/breaks in nested IFs
Rhys Perry [Tue, 7 Jan 2020 16:33:47 +0000 (16:33 +0000)]
aco: set exec_potentially_empty after continues/breaks in nested IFs

Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: error when block has no logical preds but VGPRs are live at the start
Rhys Perry [Wed, 8 Jan 2020 16:13:03 +0000 (16:13 +0000)]
aco: error when block has no logical preds but VGPRs are live at the start

This would have caught the liveness error fixed in the previous commit.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: don't always add logical edges from continue_break blocks to headers
Rhys Perry [Tue, 7 Jan 2020 19:13:08 +0000 (19:13 +0000)]
aco: don't always add logical edges from continue_break blocks to headers

Otherwise, code like this will be broken:
loop {
   if (...) {
      break;
   } else {
      break;
   }
}
The continue_or_break block doesn't have any logical predecessors but it's
a logical predecessor of the header block. This liveness error breaks the
spiller in init_live_in_vars() (under "keep variables spilled on all
incoming paths") and eventually creates garbage reloads.

Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: only create parallelcopy to restore exec at loop exit if needed
Rhys Perry [Mon, 6 Jan 2020 15:17:21 +0000 (15:17 +0000)]
aco: only create parallelcopy to restore exec at loop exit if needed

The operand isn't fixed to exec, which can mess up the spiller. This also
adds a new situation where a phi is needed.

Fixes dEQP-VK.ssbo.layout.random.descriptor_indexing.2 and an assertion
when compiling a Detroit: Become Human shader.

Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: don't update demand in add_coupling_code() for loop headers
Rhys Perry [Thu, 2 Jan 2020 14:57:02 +0000 (14:57 +0000)]
aco: don't update demand in add_coupling_code() for loop headers

We don't need to update it since it won't be used later.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: don't consider loop header blocks branch blocks in add_coupling_code
Rhys Perry [Thu, 2 Jan 2020 14:54:31 +0000 (14:54 +0000)]
aco: don't consider loop header blocks branch blocks in add_coupling_code

Loops without continues create header blocks with only 1 predecessor.

CC: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoaco: fix target calculation when vgpr spilling introduces sgpr spilling
Rhys Perry [Thu, 2 Jan 2020 15:36:49 +0000 (15:36 +0000)]
aco: fix target calculation when vgpr spilling introduces sgpr spilling

A shader might require vgpr spilling but not require sgpr spilling. In
that case, the spiller lowers the sgpr target by 5 which could mean sgpr
spilling is then required. Then the vgpr target has to be lowered to make
space for the linear vgprs. Previously, space wasn't make for the linear
vgprs.

Found while testing the spiller on the pipeline-db with a lowered limit

Fixes: a7ff1bb5b9a78cf57073b5e2e136daf0c85078d6
   ('aco: simplify calculation of target register pressure when spilling')

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3257>

4 years agoradv/gfx10: re-enable NGG GS
Samuel Pitoiset [Mon, 13 Jan 2020 08:49:49 +0000 (09:49 +0100)]
radv/gfx10: re-enable NGG GS

Now that NGG GS queries are implemented, it should be safe enough
to enable NGG GS by default. It can be disabled with RADV_DEBUG=nongg
if necessary.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>

4 years agoradv/gfx10: implement NGG GS queries
Samuel Pitoiset [Mon, 13 Jan 2020 17:30:50 +0000 (18:30 +0100)]
radv/gfx10: implement NGG GS queries

The number of generated primitives is only counted by the hardware
if GS uses the legacy path. For NGG GS, we need to accumulate that
value in the NGG GS itself. To achieve that, we use a plain GDS
atomic operation.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>

4 years agoradv/gfx10: add a separate flag for creating a GDS OA buffer
Samuel Pitoiset [Tue, 14 Jan 2020 08:14:07 +0000 (09:14 +0100)]
radv/gfx10: add a separate flag for creating a GDS OA buffer

For implementing NGG GS queries, we decided to use GDS but GDS OA
is only required for NGG streamout.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3380>

4 years agowinsys/amdgpu: Close KMS handles for other DRM file descriptions
Michel Dänzer [Tue, 28 Jan 2020 10:12:24 +0000 (11:12 +0100)]
winsys/amdgpu: Close KMS handles for other DRM file descriptions

When a BO or amdgpu_screen_winsys is destroyed.

Should fix leaking such BOs in other DRM file descriptions.

v2:
* Pass the correct file descriptor to drmIoctl (Pierre-Eric
  Pelloux-Prayer)
* Use _mesa_hash_table_remove
v3:
* Close handles in amdgpu_winsys_unref as well
v4:
* Adapt to amdgpu_winsys::sws_list_lock.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2270
Fixes: 11a3679e3aba "winsys/amdgpu: Make KMS handles valid for original
                     DRM file descriptor"

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>

4 years agowinsys/amdgpu: Re-use amdgpu_screen_winsys when possible
Michel Dänzer [Tue, 28 Jan 2020 10:07:15 +0000 (11:07 +0100)]
winsys/amdgpu: Re-use amdgpu_screen_winsys when possible

Namely, if os_same_file_description determined that the DRM file
descriptor references the same file description.

v2:
* Adapt to amdgpu_winsys::sws_list_lock.
v3:
* Fix comparison of amdgpu_screen_winsys file descriptions, see
  https://gitlab.freedesktop.org/mesa/mesa/issues/2413 .
* Lock amdgpu_winsys::sws_list_lock for traversing the sws_list in
  amdgpu_winsys_create.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3582>

4 years agoanv: Rename a variable
Jason Ekstrand [Wed, 29 Jan 2020 04:25:48 +0000 (22:25 -0600)]
anv: Rename a variable

The name "desc" shadows another variable.  Name it "desc_data" like all
of the other descriptor data variables in this file.

4 years agoanv/block_pool: Ensure allocations have contiguous maps
Jason Ekstrand [Tue, 28 Jan 2020 23:42:31 +0000 (17:42 -0600)]
anv/block_pool: Ensure allocations have contiguous maps

Because softpin block pools are made up of a set of BOs with different
maps, it was possible for a single state to end up straddling blocks.
To fix this, we pass a contiguous size to anv_block_pool_grow and it
ensures that the next allocation in the pool will have at least that
size.

We also add an assert in anv_block_pool_map to ensure we always get
contiguous maps.  Prior to the changes to anv_block_pool_grow, the unit
tests failed with this assert.  With this patch, the tests pass.

This was causing problems on Gen12 where we allocate the pages for the
AUX table from the dynamic state pool.  The first chunk, which gets
allocated very early in the pool's history, is 1MB which was enough that
it was getting multiple BOs.  This caused the gen_aux_map code to write
outside of the map and overwrite the instruction state pool buffer which
lead to GPU hangs.

Fixes: 731c4adcf9b "anv/allocator: Add support for non-userptr"
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agoanv: Re-use one old BT block in reset_batch_bo_chain
Jason Ekstrand [Tue, 28 Jan 2020 22:21:56 +0000 (16:21 -0600)]
anv: Re-use one old BT block in reset_batch_bo_chain

We intentionally throw away all but one BT block but then we set
cmd_buffer->bt_block to ANV_STATE_NULL instead of the one we hung on to.
This causes the command buffer to immediately re-emit STATE_BASE_ADDRESS
the first time a BT is needed for no good reason.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agoanv: Set actual state pool sizes when we have softpin
Jason Ekstrand [Tue, 28 Jan 2020 22:20:35 +0000 (16:20 -0600)]
anv: Set actual state pool sizes when we have softpin

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
4 years agonir/algebraic: add some half packing optimizations
Rhys Perry [Wed, 9 Oct 2019 14:27:07 +0000 (15:27 +0100)]
nir/algebraic: add some half packing optimizations

pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 29200 -> 29200 (0.00 %)
VGPRS: 17372 -> 17372 (0.00 %)
Spilled SGPRs: 105 -> 105 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 1406576 -> 1389256 (-1.23 %) bytes
LDS: 83 -> 83 (0.00 %) blocks
Max Waves: 3976 -> 3976 (0.00 %)

pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 21320 -> 21320 (0.00 %)
VGPRS: 17056 -> 17036 (-0.12 %)
Spilled SGPRs: 22 -> 22 (0.00 %)
Spilled VGPRs: 503 -> 487 (-3.18 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 396 -> 396 (0.00 %) dwords per thread
Code Size: 1441244 -> 1423292 (-1.25 %) bytes
LDS: 463 -> 463 (0.00 %) blocks
Max Waves: 3609 -> 3611 (0.06 %)

v2: add pattern for ishr

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>

4 years agonir/algebraic: add patterns for a >> #b << #b
Rhys Perry [Wed, 9 Oct 2019 14:03:45 +0000 (15:03 +0100)]
nir/algebraic: add patterns for a >> #b << #b

Fixes compilation of a Battlefront 2 shader with ACO by removing VGPR
spilling. The reassociation makes it worse on LLVM though.

pipeline-db (ACO):
Totals from affected shaders:
SGPRS: 10704 -> 10688 (-0.15 %)
VGPRS: 18736 -> 18528 (-1.11 %)
Spilled SGPRs: 70 -> 70 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 909696 -> 885796 (-2.63 %) bytes
LDS: 225 -> 225 (0.00 %) blocks
Max Waves: 1115 -> 1129 (1.26 %)

pipeline-db (LLVM):
Totals from affected shaders:
SGPRS: 8472 -> 8424 (-0.57 %)
VGPRS: 14284 -> 14368 (0.59 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 442 -> 503 (13.80 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 268 -> 396 (47.76 %) dwords per thread
Code Size: 862568 -> 853028 (-1.11 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 971 -> 964 (-0.72 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2271>

4 years agoaco: fix VS input loads with MUBUF on GFX6
Samuel Pitoiset [Wed, 29 Jan 2020 08:18:20 +0000 (09:18 +0100)]
aco: fix VS input loads with MUBUF on GFX6

Only MTBUF supports vec3.

Fixes: 03a0d39366d ("aco: use MUBUF in some situations instead of splitting vertex fetches")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3615>

4 years agoaco: run p_wqm instructions in WQM
Rhys Perry [Mon, 13 Jan 2020 14:53:56 +0000 (14:53 +0000)]
aco: run p_wqm instructions in WQM

If the p_wqm ends up creating copies, these need to be in WQM. Helps (but
doesn't completely fix) artifacts in Strange Brigade. The actual issue
still exists and is harder to fix.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>

4 years agoaco: ensure predecessors' p_logical_end is in WQM when a p_phi is in WQM
Rhys Perry [Thu, 2 Jan 2020 19:13:53 +0000 (19:13 +0000)]
aco: ensure predecessors' p_logical_end is in WQM when a p_phi is in WQM

We want any copies to be in WQM. I don't know if this fixes any real
application, but I can create a vkrunner test than reproduces the issue.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3273>

4 years agopan/midgard: Fix a liveness info leak
Icecream95 [Sun, 26 Jan 2020 01:59:24 +0000 (14:59 +1300)]
pan/midgard: Fix a liveness info leak

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3566>

4 years agoetnaviv: implement UBOs
Jonathan Marek [Sat, 4 Jan 2020 19:17:15 +0000 (14:17 -0500)]
etnaviv: implement UBOs

At the same time, use pre-HALTI2 to use address register for indirect
uniform loads, since integers/LOAD instruction isn't always available.

Passes all dEQP-GLES3.functional.ubo.* on GC7000L. GC3000 with an extra
flush hack passes most of them, but still fails on some of the cases with
many loads.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3389>

4 years agofreedreno/a6xx: convert blend state to stateobj
Rob Clark [Sat, 25 Jan 2020 22:44:55 +0000 (14:44 -0800)]
freedreno/a6xx: convert blend state to stateobj

And move to new register builders while we are at it.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>

4 years agofreedreno/a6xx: remove special handling based on MRT format
Rob Clark [Sat, 25 Jan 2020 21:44:59 +0000 (13:44 -0800)]
freedreno/a6xx: remove special handling based on MRT format

Logicop in particular is supposed to work for integer formats.. but
maybe this situation doesn't happen in gles.  The only thing that isn't
required for integer formats is blending.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>

4 years agomesa/st: random whitespace cleanup
Rob Clark [Fri, 17 Jan 2020 22:00:13 +0000 (14:00 -0800)]
mesa/st: random whitespace cleanup

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>

4 years agofreedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND
Rob Clark [Fri, 17 Jan 2020 21:58:44 +0000 (13:58 -0800)]
freedreno: use PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND

This lets us drop a bunch of special handling for xRGB blend.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3565>

4 years agogallium/util: Increase the debug_flush map depth
Thomas Hellstrom [Tue, 28 Jan 2020 12:04:23 +0000 (13:04 +0100)]
gallium/util: Increase the debug_flush map depth

Some piglit tests trigger a map depth assert when debug_flush is active.
Fix this by increasing the map depth from 16 to 32.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>

4 years agosvga: Avoid discard DMA uploads
Thomas Hellstrom [Tue, 28 Jan 2020 11:49:30 +0000 (12:49 +0100)]
svga: Avoid discard DMA uploads

Newer versions of the device code will make discard DMA uploads
sub-optimal. Disable them for guest-backed aware code, where we previously
had them conditionally enabled.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>

4 years agowinsys/svga: Enable transhuge pages for buffer objects
Thomas Hellstrom [Tue, 21 Jan 2020 09:58:25 +0000 (10:58 +0100)]
winsys/svga: Enable transhuge pages for buffer objects

If the kernel supports it, enable transhuge pages for graphics buffer
objects. Except for the syscall itself, this is never expected to cause
any negative performance implications.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>

4 years agowinsys/svga: use new ioctl for logging
Roland Scheidegger [Thu, 24 Oct 2019 04:10:46 +0000 (06:10 +0200)]
winsys/svga: use new ioctl for logging

Use the new ioctl for logging (rather than duplicating what the kernel
is doing). This way it's also independent from the actual guest/host
mechanism to do the logging.

Signed-off-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Thomas Hellstrom <thellstrom@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3614>

4 years agoradv: remove the non conformant VK implementation warning on GFX10
Samuel Pitoiset [Tue, 28 Jan 2020 13:49:16 +0000 (14:49 +0100)]
radv: remove the non conformant VK implementation warning on GFX10

It's no longer true.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>

4 years agoradv: bump conformance version to 1.2.0.0
Samuel Pitoiset [Tue, 28 Jan 2020 10:34:06 +0000 (11:34 +0100)]
radv: bump conformance version to 1.2.0.0

https://www.khronos.org/conformance/adopters/conformant-products#submission_472
https://www.khronos.org/conformance/adopters/conformant-products#submission_473
https://www.khronos.org/conformance/adopters/conformant-products#submission_474

Fixes dEQP-VK.api.driver_properties.conformance_version.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3597>

4 years agoradv: implement VK_AMD_shader_explicit_vertex_parameter
Samuel Pitoiset [Mon, 27 Jan 2020 10:08:26 +0000 (11:08 +0100)]
radv: implement VK_AMD_shader_explicit_vertex_parameter

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2402
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agoradv: gather which input PS variables use an explicit interpolation mode
Samuel Pitoiset [Mon, 27 Jan 2020 10:07:42 +0000 (11:07 +0100)]
radv: gather which input PS variables use an explicit interpolation mode

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agoaco: implement VK_AMD_shader_explicit_vertex_parameter
Samuel Pitoiset [Mon, 27 Jan 2020 11:16:41 +0000 (12:16 +0100)]
aco: implement VK_AMD_shader_explicit_vertex_parameter

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agoac/llvm: implement VK_AMD_shader_explicit_vertex_parameter
Samuel Pitoiset [Fri, 24 Jan 2020 09:18:06 +0000 (10:18 +0100)]
ac/llvm: implement VK_AMD_shader_explicit_vertex_parameter

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agospirv: implement SPV_AMD_shader_explicit_vertex_parameter
Samuel Pitoiset [Fri, 24 Jan 2020 09:55:55 +0000 (10:55 +0100)]
spirv: implement SPV_AMD_shader_explicit_vertex_parameter

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agonir: lower interp_deref_at_vertex to load_input_vertex
Samuel Pitoiset [Mon, 27 Jan 2020 10:34:00 +0000 (11:34 +0100)]
nir: lower interp_deref_at_vertex to load_input_vertex

This introduces a new NIR intrinsic for loading inputs at a specific
vertex index.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agonir: add nir_intrinsic_interp_deref_at_vertex
Samuel Pitoiset [Fri, 24 Jan 2020 15:01:04 +0000 (16:01 +0100)]
nir: add nir_intrinsic_interp_deref_at_vertex

From the SPV_AMD_shader_explicit_vertex_parameter extension:
   "Returns the value of the input <interpolant> without any
    interpolation, i.e. the raw output value of previous shader
    stage."

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agonir: lower SYSTEM_VALUE_BARYCENTRIC_* to nir_load_barycentric()
Samuel Pitoiset [Fri, 24 Jan 2020 15:13:01 +0000 (16:13 +0100)]
nir: lower SYSTEM_VALUE_BARYCENTRIC_* to nir_load_barycentric()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agonir: add nir_intrinsic_load_barycentric_model
Samuel Pitoiset [Fri, 24 Jan 2020 10:36:37 +0000 (11:36 +0100)]
nir: add nir_intrinsic_load_barycentric_model

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agospirv: add support for SpvBuiltInBaryCoord*
Samuel Pitoiset [Fri, 24 Jan 2020 09:54:06 +0000 (10:54 +0100)]
spirv: add support for SpvBuiltInBaryCoord*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agocompiler: add new SYSTEM_VALUE_BARYCENTRIC_*
Samuel Pitoiset [Fri, 24 Jan 2020 09:52:25 +0000 (10:52 +0100)]
compiler: add new SYSTEM_VALUE_BARYCENTRIC_*

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agocompiler: add PERSP to the existing barycentric system values
Samuel Pitoiset [Mon, 27 Jan 2020 17:45:26 +0000 (18:45 +0100)]
compiler: add PERSP to the existing barycentric system values

We need the LINEAR versions for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agospirv: add support for SpvDecorationExplicitInterpAMD
Samuel Pitoiset [Fri, 24 Jan 2020 09:16:56 +0000 (10:16 +0100)]
spirv: add support for SpvDecorationExplicitInterpAMD

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agocompiler: add a new explicit interpolation mode
Samuel Pitoiset [Fri, 24 Jan 2020 09:14:42 +0000 (10:14 +0100)]
compiler: add a new explicit interpolation mode

This introduces one more interpolation mode INTERP_MODE_EXPLICIT,
which is needed for AMD_shader_explicit_vertex_parameter.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3578>

4 years agoturnip: Fix issues in tu_compute_pipeline_create() that may lead to crash
Eduardo Lima Mitev [Sun, 26 Jan 2020 22:25:17 +0000 (22:25 +0000)]
turnip: Fix issues in tu_compute_pipeline_create() that may lead to crash

The shader object is destroyed even if its creation failed. It is also
not destroyed if its compilation or upload fails, leading to leaks.

Finally, tu_compute_pipeline_create() should set output var
pPipeline to VK_NULL_HANDLE if it fails.

Avoids crash on
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>

4 years agoturnip: Remove failed command buffer from pool
Eduardo Lima Mitev [Fri, 24 Jan 2020 12:02:22 +0000 (12:02 +0000)]
turnip: Remove failed command buffer from pool

When an error condition occurs during tu_create_cmd_buffer(), the
cmd buffer has already been added to a pool, so the cleanup code should
remove it.

Fixes a crash (assert in tu_device::tu_bo_finish()) in dEQP tests:

dEQP-VK.api.object_management.max_concurrent.command_buffer_primary
dEQP-VK.api.object_management.max_concurrent.command_buffer_secondary

due to pool attempting to destroy an invalid command buffer.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3572>

4 years agoradeonsi: stop using the VM_ALWAYS_VALID flag
Pierre-Eric Pelloux-Prayer [Thu, 16 Jan 2020 11:31:24 +0000 (12:31 +0100)]
radeonsi: stop using the VM_ALWAYS_VALID flag

Allocation all the bo as ALWAYS_VALID means they must all fit in memory
(vram + gtt) at each command submission.
This causes some trouble when the total allocated memory is greater than
the available memory.

Possible solutions:
- being able to tag/untag a bo as ALWAYS_VALID: would require kernel changes
- disable VM_ALWAYS_VALID when memory usage is more than a percentage of the
  available memory
- disable VM_ALWAYS_VALID entirely

v1 of this patch implemented option 2. v2 (this version) implements option 3.

Related issues:
 - https://gitlab.freedesktop.org/drm/amd/issues/607
 - https://gitlab.freedesktop.org/mesa/mesa/issues/1257

It also helps with some piglit tests (-t maxsize -t "max[_-].*size" -t maxuniformblocksize):
instead of crashing the machine, the tests fail cleanly.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2190
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3430>

4 years agoradv: enable VK_AMD_shader_fragment_mask on GFX6-GFX7
Samuel Pitoiset [Tue, 28 Jan 2020 16:51:02 +0000 (17:51 +0100)]
radv: enable VK_AMD_shader_fragment_mask on GFX6-GFX7

Works fine.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3603>

4 years agoloader: Check if the kernel driver is i915 before loading iris
Kenneth Graunke [Tue, 28 Jan 2020 01:21:03 +0000 (17:21 -0800)]
loader: Check if the kernel driver is i915 before loading iris

To prevent it from trying to load on say gma500 hardware.

Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3595>

4 years agoanv: Emit CS Stall before Instruction Cache flush for gen12 WA
Jordan Justen [Thu, 16 Jan 2020 21:16:24 +0000 (13:16 -0800)]
anv: Emit CS Stall before Instruction Cache flush for gen12 WA

Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Rework: Merge with other anvil pre-invalidate stalls (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>

4 years agoiris: Emit CS Stall before Instruction Cache flush for gen12 WA
Jordan Justen [Thu, 16 Jan 2020 21:16:24 +0000 (13:16 -0800)]
iris: Emit CS Stall before Instruction Cache flush for gen12 WA

Before flushing the instruction cache with a pipe control, we need to
use a CS Stall pipe control.

Ref: GEN:BUG:1409226450
Rework: Add stall-at-scoreboard (Lionel)
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3457>

4 years agozink: set compareEnable when setting compareOp
Erik Faye-Lund [Mon, 20 Jan 2020 16:35:55 +0000 (17:35 +0100)]
zink: set compareEnable when setting compareOp

We need to enable compareEnable for compareOp to be valid, and ANV was
recently updated to respect this. So let's update Zink to match.

This fixes the shadow-variants of several piglit regressions, like these:
spec@arb_shader_texture_lod@execution@tex-miplevel-selection
spec@glsl-1.20@execution@tex-miplevel-selection

Fixes: a19cdf989b1 ("anv: only use VkSamplerCreateInfo::compareOp if enabled")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3473>

4 years agoci: Enable -Werror on the meson-i386 build.
Eric Anholt [Tue, 17 Dec 2019 05:23:02 +0000 (21:23 -0800)]
ci: Enable -Werror on the meson-i386 build.

I find warnings to be very disruptive to my workflow (using emacs's "go to
next error" feature), and I periodically have to go clean up other
people's drivers to get back to finding my own warnings in the noise.  I
know I'm not the only one doing something like this.

We don't want to enable -Werror by default in builds, since it means that
end users will have builds spuriously fail based on what compiler version
and opt flags they have compared to what the devs are using.  However, it
is quite easy to have CI ensure that we at least don't introduce warnings
on the compiler version that it uses.

For now I've just enabled it on meson-i386 to cover a bunch of Mesa core
and get us started on ratcheting up warnings-cleanliness in the tree,
without me having to fix up all the drivers at once.

Reviewed-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>

4 years agomesa/st: Fix compiler warnings from INTEL_shader_integer_functions.
Eric Anholt [Fri, 24 Jan 2020 22:35:49 +0000 (14:35 -0800)]
mesa/st: Fix compiler warnings from INTEL_shader_integer_functions.

Fixes: 1d165b054863 ("glsl: Add new expressions for INTEL_shader_integer_functions2")
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>

4 years agoiris: Silence warning about AUX_USAGE_MC.
Eric Anholt [Tue, 17 Dec 2019 05:17:17 +0000 (21:17 -0800)]
iris: Silence warning about AUX_USAGE_MC.

It was recently introduced and not added to iris yet it looks like.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>

4 years agovulkan/wsi: Fix compiler warning when no WSI platforms are enabled.
Eric Anholt [Tue, 17 Dec 2019 03:58:39 +0000 (19:58 -0800)]
vulkan/wsi: Fix compiler warning when no WSI platforms are enabled.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3539>

4 years agodocs: update news, calendar, and link release notes for 19.3.3
Dylan Baker [Tue, 28 Jan 2020 19:36:21 +0000 (11:36 -0800)]
docs: update news, calendar, and link release notes for 19.3.3

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>

4 years agodocs: Add SHA 256 sums for 19.3.3
Dylan Baker [Tue, 28 Jan 2020 19:32:51 +0000 (11:32 -0800)]
docs: Add SHA 256 sums for 19.3.3

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>

4 years agodocs: Add relnotes for 19.3.3 release
Dylan Baker [Tue, 28 Jan 2020 19:06:07 +0000 (11:06 -0800)]
docs: Add relnotes for 19.3.3 release

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3604>

4 years agointel/mi_builder: Force write completion on Gen12+
Jason Ekstrand [Mon, 27 Jan 2020 20:42:20 +0000 (14:42 -0600)]
intel/mi_builder: Force write completion on Gen12+

Otherwise, we have no guarantee that the write actually lands before we
move on to other things.  Doing this on every SDI is probably a bit
harsh but it's safe.  We should figure out a good way to avoid this when
we can.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>

4 years agoanv: Replace one more aux_surface.isl.size_B check
Jason Ekstrand [Tue, 28 Jan 2020 04:10:36 +0000 (22:10 -0600)]
anv: Replace one more aux_surface.isl.size_B check

This one was missed in 41bffe09135.

Fixes: 41bffe09135 "anv: Replace aux_surface.isl.size_B checks with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>

4 years agointel/blorp: Handle bit-casting UNORM and BGRA formats
Jason Ekstrand [Tue, 28 Jan 2020 00:22:14 +0000 (18:22 -0600)]
intel/blorp: Handle bit-casting UNORM and BGRA formats

In f132e0fddfa, I attempted to allow BLORP to do CCS_E copies by using
the UNORM formats instead.  However, the old BLORP bit-cast code could
only handle RGBA formats and asserted on anything other than UINT
formats.  The reason we didn't catch this is because it only comes up on
Gen12 platforms which aren't in our normal CI yet.

Fixes: f132e0fddfad "intel/blorp: Add support for CCS_E copies with..."
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3593>

4 years agoaco: fix combine_salu_not_bitwise() when SCC is used
Daniel Schürmann [Tue, 28 Jan 2020 11:32:09 +0000 (12:32 +0100)]
aco: fix combine_salu_not_bitwise() when SCC is used

Previously, we didn't use the SCC bit, and thus, we didn't care about it.
With 'aco: Transform uniform bitwise instructions to 32-bit if possible.'
that changed, so that we have to handle it.

Fixes: 8a32f57fff56b3b94f1b5589feba38016f39427c ('aco: Transform uniform bitwise instructions to 32-bit if possible.')
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3598>

4 years agoradeonsi: Clear uninitialized variable
Drew Davenport [Mon, 27 Jan 2020 18:13:19 +0000 (11:13 -0700)]
radeonsi: Clear uninitialized variable

|view| was not initialized leading to flaky test failures in SkQP
test unitTest_ES2BlendWithNoTexture.

Fixes: 029bfa3d253 "radeonsi: add ability to bind images as image buffers"
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3592>

4 years agoanv: Handle unavailable queries in vkCmdCopyQueryPoolResults
Brian Ho [Mon, 27 Jan 2020 03:50:42 +0000 (19:50 -0800)]
anv: Handle unavailable queries in vkCmdCopyQueryPoolResults

If VK_QUERY_RESULT_WAIT_BIT is not set, there is currently no
special handling of unavailable queries in vkCmdCopyQueryPoolResults,
and anv will write an invalid value for the query result.

This commit updates vkCmdCopyQueryPoolResults for unavailable
queries to return 0 if the VK_QUERY_RESULT_PARTIAL_BIT flag is set
and if not, skip writing altogether.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>

4 years agoanv: Properly fetch partial results in vkGetQueryPoolResults
Brian Ho [Sun, 26 Jan 2020 23:12:11 +0000 (15:12 -0800)]
anv: Properly fetch partial results in vkGetQueryPoolResults

Currently, fetching the partial results (VK_QUERY_RESULT_PARTIAL_BIT)
of an unavailable occlusion query via vkGetQueryPoolResults can
return invalid values. anv returns slot.end - slot.begin, but in the
case of unavailable queries, slot.end is still at the initial value
of 0. If slot.begin is non-zero, the occlusion count underflows to
a value that is likely outside the acceptable range of the partial
result.

This commit fixes vkGetQueryPoolResults by always returning 0 if the
query is unavailable and the VK_QUERY_RESULT_PARTIAL_BIT is set.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3586>