git.libre-soc.org Git - mesa.git/log

radeonsi: work around an LLVM crash when using llvm.amdgcn.icmp.i64.i1

Cc: 19.2 19.3 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>

radeonsi: fix si_build_wrapper_function for compute-based primitive culling

Fixes: 3b143369a55 "ac/nir, radv, radeonsi: Switch to using ac_shader_args"
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3338>

radeonsi/gfx10: separate code for determining the number of vertices for NGG

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi/gfx10: separate code for getting edgeflags from the gs_invocation_id VGPR

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: move VS_STATE.LS_OUT_PATCH_SIZE a few bits higher to make space there

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: make si_insert_input_* functions non-static

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

ac/cull: don't read Position.Z if it's not needed for culling

It could be NULL.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: separate code computing info for small primitive culling

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

intel/compiler: Fix illegal mutation in get_nir_image_intrinsic_image

get_nir_image_intrinsic_image() was incorrectly mutating the value held
by the register which holds the intrinsic's first source (image index).

If this happened to be the register for an SSA def which is also used
elsewhere in the program, this meant that we would clobber that value
in subsequent uses.

Note that this only affects i965, because neither anv nor iris use the
binding table start sections, so nothing is ever added here.

Fixes KHR-GL46.compute_shader.resources-max on i965 with Eric Anholt's
MR !3240 applied. That MR reorders SSBOs and ABOs, so that test uses
image 0 and SSBO 0, causing this code to brilliantly add binding table
index 45 to both the image (correct) and the SSBO (bzzt, wrong!).

Fixes: 09f1de97a76 ("anv,i965: Lower away image derefs in the driver")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3404>

gitlab-ci: fix missing caselist.css/xsl

My best guess is that this was broken by d62dd8b0

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3413>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3413>

relnotes: Add Vulkan 1.2

radv: enable Vulkan 1.2

This bumps the Vulkan version to 1.2.128.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: implement Vulkan 1.2 features and properties

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: implement Vulkan 1.1 features and properties

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_timeline_semaphore for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_uniform_buffer_standard_layout for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_shader_subgroup_extended_types for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_shader_float_controls for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_shader_float16_int8 for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_shader_atomic_int64 for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_imageless_framebuffer for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_image_format_list for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_driver_properties for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_draw_indirect_count for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_depth_stencil_resolve for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_create_renderpass2 for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_buffer_device_address for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_KHR_8bit_storage for Vulkan 1.2

Promoted to Vulkan 1.2 with the KHR suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_EXT_scalar_block_layout for Vulkan 1.2

Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_EXT_sampler_filter_minmax for Vulkan 1.2

Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_EXT_host_query_reset for Vulkan 1.2

Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: update VK_EXT_descriptor_indexing for Vulkan 1.2

Promoted to Vulkan 1.2 with the EXT suffix omitted.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

anv: Enable Vulkan 1.2 support

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: Implement the new core version property queries

Vulkan 1.2 introduces some new structures to get the properties and
features of a device from extensions that were promoted to core in 1.1
and 1.2. This commit implements the new property queries and makes all
of the corresponding extension queries map to them.

Reviewed-by: Iván Briano <ivan.briano@intel.com>

anv: Implement the new core version feature queries

Vulkan 1.2 introduces some new structures to get the properties and
features of a device from extensions that were promoted to core in 1.1
and 1.2. This commit implements the new feature queries and makes all
of the corresponding extension queries map to them.

Reviewed-by: Iván Briano <ivan.briano@intel.com>

anv,nir: Lower quad_broadcast with dynamic index in NIR

This is required for the subgroupBroadcastDynamicId feature that was
added in Vulkan 1.2.

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>

anv: Bump the patch version to 131

vulkan/overlay: Fix for Vulkan 1.2

v2 (Jason Ekstrand):
- Add duplicate hooks for both the 1.2 and KHR versions of
vkCmdDraw[Indexed]IndirectCount.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

turnip: Pretend to support Vulkan 1.2

It doesn't really support any Vulkan properly yet so why not claim 1.2?
This was an easier way of fixing the build than trying to roll it
forward to a later version of ANV's entrypoint generator scripts.

vulkan: Update the XML and headers to 1.2.131

Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

gitlab-ci: Stop using manual jobs for merge requests

They were causing trouble with Marge Bot: The project settings require
that the pipeline succeeds before a merge request (MR) can be merged,
otherwise Marge doesn't wait for the pipeline to succeed before merging
an MR assigned to her. But Marge can't start manual jobs, so she would
always time out waiting for pipelines with manual jobs.

To avoid this, use these rules:
* Run the pipeline by default for MRs and main project branches changing
  any files affecting it.
* For other MRs, run a single dummy job which always succeeds.
* Don't run any jobs for main project branch changes (e.g. from an MR
  having been merged) not affecting the pipeline.
* Allow jobs to be started manually on branches of forked projects, as
  before.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3361>

radeonsi: drop the negation from fmask_is_not_identity

This change eases code reading ("fmask_is_identity = true" is clearer than
"fmask_is_not_identity = false").
Initialization is not changed so fmask_is_identity is false when a texture is
created.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>

radeonsi: unbind image before compute clear

It's not used and avoid infinite recursion when used from si_compute_expand_fmask

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>

radeonsi: make sure fmask expand is done if needed

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2248
Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>

radeonsi: fix fmask expand compute shader

'coord' variable was using TGSI_WRITEMASK_XYZ so subsequent uses of
TGSI_WRITEMASK_W were dropped.
The result for a 2 samples program was:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  2: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  3: END

instead of the expected:

  0: UMAD TEMP[0].xy, SV[1].xyyy, IMM[0].xxxx, SV[0].xyyy
  1: MOV TEMP[0].w, IMM[0].yyyy
  2: LOAD TEMP[1], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  3: MOV TEMP[0].w, IMM[0].zzzz
  4: LOAD TEMP[2], IMAGE[0], TEMP[0], RESTRICT, 2D_MSAA
  5: MOV TEMP[0].w, IMM[0].yyyy
  6: STORE IMAGE[0], TEMP[0], TEMP[1], RESTRICT, 2D_MSAA
  7: MOV TEMP[0].w, IMM[0].zzzz
  8: STORE IMAGE[0], TEMP[0], TEMP[2], RESTRICT, 2D_MSAA
  9: END

This fixes half of https://gitlab.freedesktop.org/mesa/mesa/issues/2248

Fixes: 095a58204d9 ("radeonsi: expand FMASK before MSAA image stores are used")
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174>

egl/android: Restrict minimum triple buffering for android color_buffers

The patch restricts triple buffering as minimum at driver for android
color_buffers in order to fix onscreen performance hit for T-Rex and
Manhattan.

v2: Update min_buffer check condition (Tapani Pälli)
v3: further code cleanup (Eric Engestrom)

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2332
Fixes: 0661c357c60 ("egl/android: Update color_buffers querying for buffer age")
Signed-off-by: Nataraj Deshpande <nataraj.deshpande@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3384>

anv: fix pipeline switch back for non pipelined states

Setting state base address can happen even before pipeline is
selected. Also we must ensure it is set to 3D for Gen12, we can't
switch back to an invalid pipeline value (UINT32_MAX).

v2: Reuse helpers (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: b34422db5e66 ("anv: Implement Gen12 workaround for non pipelined state")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3396>

radv/gfx10: simplify some duplicated NGG GS code

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>

radv/gfx10: enable all CUs if NGG is never used

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3382>

radv: only use VkSamplerCreateInfo::compareOp if enabled

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3392>

v3d: fix bug when checking result of syncobj fence import

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3383>

st/mesa: run st_nir_lower_tex_src_plane for lowered xyuv/ayuv

Has the effect of removing the nir_tex_src_plane for these formats too.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>

st/mesa: don't lower YUV when driver supports it natively

This fixes YUYV support on etnaviv.

Fixes: 7404833c "gallium: add handling for YUV planar surfaces"
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/1896>

radv: Disable VK_EXT_sample_locations on GFX10.

Workaround for https://gitlab.freedesktop.org/mesa/mesa/issues/2163

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3236>

st/mesa: implement EGLImageTargetTexStorage

We can now support this extension.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>

st/mesa: refactor egl image binding a bit

We'll need it for egl image tex storage.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>

st/dri: track if image is created by a dmabuf

Will be used by EXT_EGL_image_storage later.

Acked-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3375>

freedreno/ir3: rename instructions

Turns out this range of opcodes are more general purpose if/else/endif
instructions.

We should re-work tess to create a basic block and use normal flow
control. And possibly (for a6xx+) optimize cases to use if/else/endif
when appropriate.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3398>

nir/algebraic: sqrt(x)*sqrt(x) -> fabs(x)

total instructions in shared programs: 12840840 -> 12839341 (-0.01%)
instructions in affected programs: 122581 -> 121082 (-1.22%)
helped: 559
HURT: 0

total cycles in shared programs: 302505756 -> 302490031 (<.01%)
cycles in affected programs: 2022900 -> 2007175 (-0.78%)
helped: 1090
HURT: 130

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>

nir/algebraic: i2f(f2i()) -> trunc()

total instructions in shared programs: 12840968 -> 12840784 (<.01%)
instructions in affected programs: 17886 -> 17702 (-1.03%)
helped: 77
HURT: 0

total cycles in shared programs: 302508917 -> 302505592 (<.01%)
cycles in affected programs: 249964 -> 246639 (-1.33%)
helped: 70
HURT: 7

Signed-off-by: Elie Tournier <elie.tournier@collabora.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/948>

i965: Reuse the new core glsl_count_dword_slots().

The only difference I could see was treating interfaces like structs.
Maintain that case.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>

mesa/st: Move the dword slot counting function to glsl_types as well.

To implement NIR-to-TGSI, we need to be able to get the size of the
uniform variable for the TGSI declaration, not just the
.driver_location. With its location in mesa/st, drivers couldn't link
to it from nir-to-tgsi.

This feels like a common enough function to want, so let's share it in
the core compiler.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>

mesa/prog: Reuse count_vec4_slots() from ir_to_mesa.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>

mesa/st: Move the vec4 type size function into core GLSL types.

The only bit that gallium varied on was handling of bindless. We can
retain previous behavior for count_attribute_slots() by passing in
"true" (though I suspect this is just giving a silly answer to a silly
question), and delete our recursive function from mesa/st.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>

mesa/st: Deduplicate the NIR uniform lowering code.

Just a little refactor as I go looking at the type size functions.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3297>

radeonsi: move PS LLVM code into si_shader_llvm_ps.c

This is an attempt to clean up si_shader.c.

v2: don't move code that is not specific to LLVM

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)

radeonsi: remove always constant ballot_mask_bits from si_llvm_context_init

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: fold si_create_function into si_llvm_create_func

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename si_shader_create -> si_create_shader_variant for clarity

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename si_compile_tgsi_main -> si_build_main_function

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: clean up si_shader_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: merge si_tessctrl_info into si_shader_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename si_shader_info -> si_shader_binary_info

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: remove TGSI from comments

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIR

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

radeonsi: don't adjust depth and stencil PS output locations

this was for compatibility with TGSI

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>

nir: Add missing nir_var_mem_global to various passes

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>

spirv: Handle PhysicalStorageBuffer in memory barriers

PhysicalStorageBuffer is lowered to nir_var_mem_global, and
SPIR-V 1.5rev1 in section "3.25. Memory Semantics <id>" says

    UniformMemory

    Apply the memory-ordering constraints to StorageBuffer,
    PhysicalStorageBuffer, or Uniform Storage Class memory.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>

spirv: Drop EXT for PhysicalStorageBuffer symbols

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3322>

aco: Flip s_cbranch / s_cselect to optimize out an s_not if possible.

When possible, get rid of an s_not when all it does is invert the SCC,
and its successor s_cbranch / s_cselect can be inverted instead.

Also modify some parts of instruction_selection to take advantage of
this feature.

Example:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
s2: %3902 = s_cselect_b64 -1, 0, %3900:scc
s2: %407,  s1: %3903:scc = s_not_b64 %3902
s2: %3906,  s1: %3905:scc = s_and_b64 %407, %0:exec
p_cbranch_z %3905:scc
Can now be optimized to:
s2: %3900,  s1: %3899:scc = s_andn2_b64 %0:exec, %406
p_cbranch_nz %3900:scc

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Optimize out s_and with exec, when used on uniform bitwise values.

Previously all booleans needed an s_and with exec when they were turned
into a scalar condition. However, this is not needed for uniform booleans.

v2 by Daniel Schürmann:
- Make the code more readable
v3 by Timur Kristóf:
- Fix regressions, make it work in wave32 mode

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Don't skip combine_instruction when definitions[1] is used.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Allow optimizing vote_all and nir_op_iand.

By adding an extra instruction, we can replace the operands of
the s_cselect_b64, which allows it to get picked up by the
optimizer when it looks for uniform booleans.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

aco: Implement 64-bit constant propagation.

Signed-off-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>

panfrost: Fix linear depth textures

As pointed out by Boris, what we were calling PAN_LINEAR depth textures
was in fact u-interleaved tiled (!), but we never noticed since we
flipped the flag used for sampling, leading to all sorts of fun bugs
when attempting to directly acess depth textures from the CPU. Which
begs the question -- if what we called LINEAR was tiled, how do we
actually render linear depth textures? It turns out the flags for AFBC
form a mali_block_format 2-bit code just like their render-target
counterparts, so we can render to any of the above.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reported-by: Boris Brezillon <boris.brezillon@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3393>

vulkan/wsi: Add a driconf option to force WSI to advertise BGRA8_UNORM first

The Aztec Ruins benchmark just grabs the first format in the list and
SRGB causes it to render washed out. With this workaround, it renders
the same as OpenGL.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3350>

intel/fs: Only use SLM fence in compute shaders

Fixes: b390ff35170 ("intel/fs: Add support for SLM fence in Gen11")
Fixes: e142061399c ("intel/fs: Implement scoped_memory_barrier")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radeonsi: actually enable VBOs in user SGPRs

Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

radeonsi: fix assertion and other failures in si_emit_graphics_shader_pointers

The assertion was failing.

Fixes: 363b4027fcb - radeonsi: put up to 5 VBO descriptors into user SGPRs
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

nir/algebraic: a & ~(a >> 31) -> imax(a, 0)

Found in some Doom shaders

Totals from affected shaders:
SGPRS: 30056 -> 30064 (0.03 %)
VGPRS: 28024 -> 28024 (0.00 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 4278648 -> 4270852 (-0.18 %) bytes
Max Waves: 1476 -> 1476 (0.00 %)
Instructions: 835287 -> 833338 (-0.23 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3089>

etnaviv: Fix assert when try to accumulate an invalid fd

Check if it is a valid fd before merging it to the context's fd.

Signed-off-by: Marco Felsch <m.felsch@pengutronix.de>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3381>

pan/midgard: Fix midgard_compile.h includes

We now use enum mali_format which is defined in panfrost-job.h

Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3243>

anv: only use VkSamplerCreateInfo::compareOp if enabled

The spec says nothing about the validity of the compareOp field when
compareEnable is false.

v2: use vulkan enum to pick default value (Caio)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2350
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3387>

nir/sink,nir/move: move/sink nir_op_mov

Can uncover opportunities to move other instructions. This can increase
register usage, but that doesn't seem to actually happen.

This optimizes a pattern of a load_per_vertex_input followed by several
moves and then a store_output in a different block.

v2: add nir_move_copies to make it optional

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net> (v1)
Acked-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>

nir/sink,nir/move: move/sink load_per_vertex_input

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2420>

gitlab-ci: Consolidate container and build stages for LAVA

Use the normal build job to also prepare the artifacts for LAVA jobs.

For that, the build container needs to also build the test suites,
kernel, ramdisk, etc.

Then the build job will place the just-built Mesa in the ramdisk and the
test job can generate a LAVA job and point to those artifacts.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3295>

aco: add integer min/max to can_swap_operands

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>

aco: improve readfirstlane after uniform LDS loads

Totals from affected shaders:
SGPRS: 976 -> 968 (-0.82 %)
VGPRS: 580 -> 584 (0.69 %)
Spilled SGPRs: 0 -> 0 (0.00 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Code Size: 106032 -> 103076 (-2.79 %) bytes
Max Waves: 237 -> 237 (0.00 %)
Instructions: 19452 -> 18740 (-3.66 %)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2883>