freedreno/a6xx: Make DEBUG_BLIT_FALLBACK only dump fallbacks

Use new macro, DEBUG_BLIT, for dumping all blits.

Reviewed-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2848>

freedreno/ir3: fix vertex shader sysvals with pre_assign_inputs

The first pre_assign_inputs loop doesn't pre-assign sysvals, so skip the
second part for sysvals.

The sysvals don't need to be pre-assigned since the state for those isn't
shared between binning / nonbinning shaders.

Fixes assert failures in cases where the sysvals didn't end up in the same
registers for binning / nonbinning.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3168>

st/va: Convert interlaced NV12 to progressive

In vlVaDeriveImage, convert interlaced NV12 buffers to progressive.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1193
Signed-off-by: Thong Thai <thong.thai@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3157>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3157>

pan/midgard: Add uniform/work heuristic

Uniform/work registers are partitioned on a shader-by-shader basis as
determined by the compiler. We add a simple heuristic here running
before scheduling that prioritizes mitigating spilling at all costs.

A more sophisticated heuristic should run *after* scheduling, doing a
dry run of the register allocator itself to determine spilling. Fitting
this into our current scheduling model is difficult, so while this
heuristic does hurt some shaders, overall the results are acceptable:

total instructions in shared programs: 50065 -> 38747 (-22.61%)
instructions in affected programs: 37187 -> 25869 (-30.44%)
helped: 59
HURT: 77
helped stats (abs) min: 1 max: 757 x̄: 198.46 x̃: 151
helped stats (rel) min: 0.48% max: 62.89% x̄: 32.95% x̃: 36.27%
HURT stats (abs)   min: 1 max: 9 x̄: 5.08 x̃: 6
HURT stats (rel)   min: 0.92% max: 14.29% x̄: 6.71% x̃: 4.60%
95% mean confidence interval for instructions value: -111.15 -55.29
95% mean confidence interval for instructions %-change: -14.33% -6.67%
Instructions are helped.

total bundles in shared programs: 30606 -> 19157 (-37.41%)
bundles in affected programs: 23907 -> 12458 (-47.89%)
helped: 58
HURT: 74
helped stats (abs) min: 6 max: 757 x̄: 203.09 x̃: 152
helped stats (rel) min: 5.19% max: 77.00% x̄: 49.38% x̃: 53.79%
HURT stats (abs)   min: 1 max: 9 x̄: 4.46 x̃: 5
HURT stats (rel)   min: 1.85% max: 26.32% x̄: 11.70% x̃: 9.57%
95% mean confidence interval for bundles value: -115.46 -58.01
95% mean confidence interval for bundles %-change: -20.87% -9.41%
Bundles are helped.

total quadwords in shared programs: 31305 -> 32027 (2.31%)
quadwords in affected programs: 20471 -> 21193 (3.53%)
helped: 0
HURT: 133
HURT stats (abs)   min: 1 max: 9 x̄: 5.43 x̃: 5
HURT stats (rel)   min: 0.76% max: 15.15% x̄: 5.47% x̃: 4.65%
95% mean confidence interval for quadwords value: 5.00 5.86
95% mean confidence interval for quadwords %-change: 4.85% 6.08%
Quadwords are HURT.

total registers in shared programs: 2256 -> 2545 (12.81%)
registers in affected programs: 708 -> 997 (40.82%)
helped: 0
HURT: 95
HURT stats (abs)   min: 1 max: 8 x̄: 3.04 x̃: 3
HURT stats (rel)   min: 12.50% max: 100.00% x̄: 39.41% x̃: 37.50%
95% mean confidence interval for registers value: 2.64 3.45
95% mean confidence interval for registers %-change: 34.62% 44.19%
Registers are HURT.

total threads in shared programs: 1776 -> 1709 (-3.77%)
threads in affected programs: 134 -> 67 (-50.00%)
helped: 0
HURT: 67
HURT stats (abs)   min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel)   min: 50.00% max: 50.00% x̄: 50.00% x̃: 50.00%
95% mean confidence interval for threads value: -1.00 -1.00
95% mean confidence interval for threads %-change: -50.00% -50.00%
Threads are HURT.

total spills in shared programs: 3868 -> 2 (-99.95%)
spills in affected programs: 3868 -> 2 (-99.95%)
helped: 60
HURT: 0

total fills in shared programs: 6456 -> 4 (-99.94%)
fills in affected programs: 6456 -> 4 (-99.94%)
helped: 60
HURT: 0

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3150>

ac: declare an enum for the OOB select field on GFX10

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>

radv/gfx10: fix the out-of-bounds check for vertex descriptors

When stride is 0, it should check against the offset not the index.

This fixes black character models with Beat Saber and missing snow
with Dragon Quest.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2233
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1975
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3147>

nir/lower_double_ops: relax lower mod()

Currently when lowering mod() we add an extra instruction so if
mod(a,b) == b then 0 is returned instead of b, as mathematically
mod(a,b) is in the interval [0, b).

But Vulkan spec has relaxed this restriction, and allows the result to
be in the interval [0, b].

This commit takes this in account to remove the extra instruction
required to return 0 instead.

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2922>

zink: implement nir_texop_txd

This lets us enable PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD, which in turns
gives us ARB_shader_texture_lod.

Still fails one piglit test on ANV, namely
spec@arb_shader_texture_lod@execution@arb_shader_texture_lod-texgradcube,
but with 33 new passing tests, I think this is worth it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3140>

zink: enable PIPE_CAP_MIXED_COLORBUFFER_FORMATS

This just works in Vulkan, there's no work neeed to enable it.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3148>

turnip: don't set SP_FS_CTRL_REG0_VARYING if only fragcoord is used

Fixes artifacts in the subpasses demo, which has a shader using fragcoord
without any varyings. It looks like setting this bit when there are no
varyings can cause weirdness in some cases (without this change, if the
previous shader had <= 8 varyings it would work, but with 9 varyings it
would have artifacts).

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>

turnip: add cache invalidate to fix input attachment cases

Fixes artifacts in the subpasses demo.

Workaround texture cache with input attachments from GMEM by adding a cache
invalidate between subpasses.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3143>

loader: fix close on uninitialized file descriptor value

Using a drm syscall layer faking a kernel driver :

  ==581460== Conditional jump or move depends on uninitialised value(s)
  ==581460==    by 0x48A4C2B: close (drm-hooks.cpp:185)
  ==581460==    by 0x5A815F1: dri3_alloc_render_buffer (loader_dri3_helper.c:1469)
  ==581460==    by 0x5A82050: dri3_get_buffer (loader_dri3_helper.c:1827)
  ==581460==    by 0x5A82662: loader_dri3_get_buffers (loader_dri3_helper.c:2028)
  ==581460==    by 0x6C78109: intel_update_image_buffers (brw_context.c:1870)
  ==581460==    by 0x6C77805: intel_update_renderbuffers (brw_context.c:1499)
  ==581460==    by 0x6C7789D: intel_prepare_render (brw_context.c:1520)
  ==581460==    by 0x6C773D4: intelMakeCurrent (brw_context.c:1341)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 069fdd5f9fac ("egl/x11: Support DRI3 v1.1")
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3152>

freedreno: Fix CP_MEM_TO_REG flag definitions

These actually mean something completely different, at least on A5xx
and A6xx. The only other usage of the old flags on something older than
A6xx was a typo, so I don't know if it was always this way, but at the
same time it means that we don't have to worry too much about that.

Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>

freedreno: Use new macros for CP_WAIT_REG_MEM and CP_WAIT_MEM_GTE

Similar to the existing usage for CP_COND_WRITE5, this makes it clear
what each of the magic parameters are for.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>

a6xx: Add more CP packets

And add fields uncovered by looking at the firmware. I think this covers
all the memory, register, and scratch manipulation opcodes that exist on
A6xx, plus one additional nice find for Vulkan and describing a
previously unknown opcode and documenting CP_WAIT_REG_MEM.

Note that the bits for the CP_REG_TO_MEM count, as well as the formula
for computing the actual count for both CP_REG_TO_MEM and CP_MEM_TO_REG,
are changed because the A630 SQE firmware actually does something
different. I haven't investigated older microcodes to see whether this
extends back to A5xx and A4xx, but the only non-A6xx uses of this
field result in the same bit-pattern when using the A6xx bit range and
formula, so it should be safe to change the definition universally.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@gmail.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3116>

radv: Limit workgroup size to 1024.

Fixes a hang with geekbench.

The existence of RX 580 and NAVI10 results shows that the generations
before and after this do not have the issue. (They show up on the
website). So this is likely a GFX9 only issue.

This is not something weird like LDS size since none of the shaders
seem to use LDS.

CC: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3145>

docs: Add release notes, news, and update calendar for 19.2.8

docs/relnotes/19.2.8: Add SHA256 sum

docs: add relnotes for 19.2.8

docs: Add release notes, update calendar, and add news for 19.3.1

dcos: add releanse notes for 19.3.1

i965/iris/perf: factor out frequency register capture

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3113>

freedreno/ir3: update prefetch input_offset when packing inlocs

If the input location changes then prefetch input_offset needs to change.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3141>

ci: Fix caselist results archiving after parallel-deqp-runner rename.

Noticed while reviewing some lava parallel-deqp-runner changes.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3138>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3138>

freedreno/a6xx: Document the CP_SET_DRAW_STATE enable bits

There are bits for binning, gmem and sysmem.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Signed-off-by: Kristian H. Kristensen <hoegsberg@google.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3131>

anv/gen12: Temporarily disable VK_KHR_buffer_device_address (and EXT)

For the sake of our testing infrastructure, disable this extension
for TGL until we can sort out a hang in Vulkan CTS.

Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Acked-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>

intel/vec4: Fix lowering of multiplication by 16-bit constant

Existing code was ignoring whether the type of the immediate source
was signed or not.  If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).

Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for older
platforms that don't support MUL with 32x32 types and use vec4.

Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

intel/fs: Fix lowering of dword multiplication by 16-bit constant

Existing code was ignoring whether the type of the immediate source
was signed or not.  If the source was signed, it would ignore small
negative values but it also would wrongly accept values between
INT16_MAX and UINT16_MAX, causing the atual value to later be
reinterpreted as a negative number (under 16-bits).

Fixes tests/shaders/glsl-mul-const.shader_test in Piglit for platforms
that don't support MUL with 32x32 types, including ICL and TGL.

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2186
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

pan/midgard: Set Z to shadow comparator for 2D

We still need to generalize for other types of (non-2D / array) shadow
samplers, but this is enough for sampler2DShadow to work with initial
dEQP tests passing.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

pan/midgard: Set .shadow for shadow samplers

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

pan/midgard: Hoist temporary coordinate for cubemaps

We'll reuse some of this code for shadow samplers, which are represented
by a distinct source in NIR.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

pan/midgard: Use a reg temporary for mutiple writes

Bug in texelfetch implementation from inspection.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

panfrost: Handle empty shaders

I didn't realize this was in spec, but it fixes a crash in shaderdb.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

panfrost: Let precompile imply shaderdb

This cuts down the number of random environmental variables we need
flying around; now PAN_MESA_DEBUG=precompile is sufficient and
MIDGARD_MESA_DEBUG=shaderdb will be implied.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

panfrost: Add PAN_MESA_DEBUG=precompile for shader-db

We would like to use run.c for shader-db runs (rather than capturing in
real-time, which is limiting).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3125>

mesa: avoid triggering assert in implementation

When tearing down a GL context with an active performance query, the
implementation can be confused by a query marked active when it's
being deleted.

This shouldn't happen in the implementation because the context will
already be idle.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2235
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3115>

radv/gfx10: fix ngg_get_ordered_id

Ported from RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3133>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3133>

ci: Remove T820 from CI temporarily

Our lab will have continuous programmed power cuts until the 6th January 2020,
so it's safer to disable the T820 CI running on the BayLibre kernelCI lab
to avoid breaking CI.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3135>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3135>

i965: expose MESA_FORMAT_B8G8R8X8_SRGB visual

Patch adds BGRX sRGB visuals, required format translation information
to the __DRI_IMAGE_FOURCC_SXRGB8888 format and makes all BGRX visuals
sRGB capable just like is done with BGRA.

squashed patches from Yevhenii Kolesnikov:
  dri: Add __DRI_IMAGE_FOURCC_SXRGB8888 conversion
  i965: force visuals without alpha bits to use sRGB

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/1501
Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Yevhenii Kolesnikov <yevhenii.kolesnikov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>

dri: add __DRI_IMAGE_FORMAT_SXRGB8

Add format definition and required plumbing to create images.

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3077>

virgl: Increase the shader transfer buffer by doubling the size

With only linearly increasing the size of the shader transfer buffer
the transfer of very large shaders may fail, so with each attempt double
the size of the buffer.

CTS:
  dEQP-GLES31.functional.ssbo.layout.random.all_shared_buffer.48
  for VTK-GL-CTS b5dcfb9c5 and newer

virglrenderer bug:
  https://gitlab.freedesktop.org/virgl/virglrenderer/issues/150

Fixes: a8987b88ff1db4ac00720a9b56c4bc3aeb666537
    virgl: add driver for virtio-gpu 3D (v2)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Gurchetan Singh <gurchetansingh@chromium.org>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3121>

turnip: Fix support for immutable samplers.

We were setting up the hardware sampler state when updating a combined
image sampler, but never looking at the immutable sampler for in the
separate case.

Fixes failures in
dEQP-VK.binding_model.shader_access.primary_cmd_buf.sampler_immutable.fragment.*

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3127>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3127>

turnip: don't set LRZ enable at end of renderpass

Fixes hanging with cases that use more than one renderpass.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3122>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3122>

freedreno/ir3: lower pack/unpack ops

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>

nir: add option to lower half packing opcodes

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3106>

turnip: Add support for descriptor arrays.

I had a bigger rework I was working on, but this is simple and gets tests
passing.

Fixes 36 failures in
dEQP-VK.binding_model.shader_access.primary_cmd_buf.sampler_mutable.fragment.*
(now all passing)

Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>

turnip: Drop unused variable.

We really need -Werror in CI.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3124>

panfrost: Don't double-create scratchpad

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 4f7fddbd716 ("panfrost: Pass size to panfrost_batch_get_scratchpad")
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>

panfrost: Simplify sampler upload condition

Makes it more obvious what's going on.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3119>

gallium/auxiliary: Handle count == 0 in u_vbuf_get_minmax_index_mapped

This makes u_vbuf_get_minmax_index_mapped return min = 0 / max = 0
when info->count == 0.

That should never happen anyway, but this commit makes it at least
return a sane value that callers expect, and also allows us - and
GCC - to assume count != 0 for optimization purposes.

Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>

gallium/auxiliary: Reduce conversions in u_vbuf_get_minmax_index_mapped

With this patch, GCC generates vectorized code that does the comparisons
without converting the indices to 32-bit first.

This optimization makes the aforementioned function almost twice as fast
for ARM NEON, and should speed up vectorised code on other platforms.

Without vectorisation, the function is still a percent or two faster,
but slightly larger.

Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3050>

amd/addrlib: update to the latest version

Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>

turnip: remove duplicate A6XX_SP_CS_CONFIG_NIBO

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>

turnip: change emit_ibo to be like emit_textures

Adds missing alignment and error checking.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>

turnip: fix emit_ibo

Based on the GL driver:
-Compute needs different opcode (this fixes a GPU hang problem)
-REG_A6XX_SP_IBO_LO/REG_A6XX_SP_CS_IBO_LO were swapped

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>

turnip: remove compute emit_border_color

Current tu6_emit_border_color doesn't work for compute and there's no
example from the GL driver to base it on, so replace it with a finishme.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>

turnip: fix emit_textures for compute shaders

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3104>

utils/os_socket: Define ssize_t on windows.

Fixes: ef5266ebd50 ("util/os_socket: Add socket related functions.")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>

radeonsi/gfx10: fix ngg_get_ordered_id

This could have caused issues with NGG streamout.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: reset more fields in si_llvm_context_set_ir to fix reusing ctx

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: fix determining whether the VS prolog is needed

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: allow generating VS prologs with 0 inputs

If "ls_vgpr_fix" is set, we use a prolog, but it can have 0 inputs.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi/gfx10: don't insert NGG streamout atomics if they are never used

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: don't wrap the VS prolog in if (ES thread) .. endif

We can execute it unconditionally and the values computed for disabled
threads won't be used anyway.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: set is_monolithic for VS prologs when the shader is really monolithic

This fixes a bug with NGG that is probably harmless.

Basically, !is_monolithic makes the VS prolog emit
llvm.amdgcn.init.exec.from.input, which sets the EXEC mask to only enable
ES threads. In the NGG non-GS case, the GS threads <= ES threads, so it was
never an issue.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: disallow compute-based culling if polygon mode is enabled

Polygon mode can generate thick points or lines.

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

radeonsi: deduplicate ES and GS thread enablement code

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

ac: fix the return value in cull_bbox when bbox culling is disabled

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

ac: fix ac_get_i1_sgpr_mask for Wave32

Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3095>

panfrost: Remove asserts in panfrost_pack_work_groups_compute

It's a hot routine and these are exceedingly unlikely to break.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>

panfrost: Pack invocation_shifts manually instead of a bit field

gcc generates exceptionally bad code for panfrost_pack_work_groups_fused
otherwise ... although that routine is somehow still hot ...

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3067>

anv: Export VK_KHR_buffer_device_address only when really supported

Fixes: 1b6991ba1d8 ("anv: Implement VK_KHR_buffer_device_address")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>

anv: Export filter_minmax support only when it's really supported

Fixes: bea4d4c78c3 ("anv: add VK_EXT_sampler_filter_minmax support")
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3071>

freedreno/ir3: lower mul_2x32_64

lower_mul_2x32_64 generates mul_high opcodes, and lower_mul_high is done by
nir_lower_alu, so call nir_lower_alu after nir_opt_algebraic.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

turnip: implement CmdFillBuffer/CmdUpdateBuffer

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

turnip: don't require src image to be set for clear blits

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

turnip: use common blit path for buffer copy

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

turnip: use single substream cs

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Reviewed-by: Eric Anholt <eric@anholt.net>

panfrost: Remove fbd_type enum

Just use the MALI_MFBD tag directly; it's clean.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>

ci: Reinstate Panfrost CI

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>

panfrost: Fix FBD issue

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: b0e915b4e65 ("panfrost: Emit SFBD/MFBD after a batch, instead of before")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3118>

vulkan/wsi: error out when image fence doesn't signal

If for some reason the fence associated with an image doesn't signal,
we're likely in a device lost scenario, we should report that error.

We can't really wait for a given amount of time because we could get a
timeout and that is not a valid error to report for vkQueuePresentKHR,
so just wait forever.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/830
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>

anv: drop unused parameter from apply layout pass

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

anv: constify pipeline layout in nir passes

Was hoping to find potential issues but nothing. Still probably a good
idea.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

pan/midgard: Set r1.w magic

I'm honestly unsure what this is for, but it's needed on MFBD systems
for unknown reasons, at least when MRT is actually in use and then
sometimes without MRT (it fixes a blend shader issue on T760?)

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>

pan/midgard: Fix liveness analysis with multiple epilogues

Epilogues are special fixed-function blocks, so they need special
handling for liveness analysis to work completely. This in turns fixes
RA issues for many shaders using MRT.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>

pan/midgard: Writeout per render target

The flow is considerably more complicated. Instead of one writeout loop
like usual, we have a separate write loop for each render target. This
requires some scheduling shenanigans to get right.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>

pan/midgard: Add schedule barrier after fragment writeout

This is a branch, like discard, so we need a barrier to make it safe.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>

panfrost: Pass blend RT number through

We have to key the blend shader for the render target number due to
writeout silliness.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Tomeu Visoso <tomeu.vizoso@collabora.com>

gallium: refuse to create buffers larger than UINT32_MAX

pipe_resource.width0 is 32 bits and hardware support for bigger buffer is
limited (eg: AMD hardware doesn't support buffer shader resources bigger
than 4GB).

Closes: https://gitlab.freedesktop.org/mesa/mesa/issues/2053
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2948>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2948>

radeonsi: disable dcc for 2x MSAA surface and bpe < 4

This fixes a series of dEQP tests on Raven platforms:
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgba4
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb5_a1
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rgb565
  - dEQP-GLES3.functional.fbo.msaa.2_samples.rg8
  - dEQP-GLES3.functional.fbo.msaa.2_samples.r16f

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3090>

v3d: expose OES_geometry_shader

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: support precompiling geometry shaders

At present, this is only relevant for shader-db.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: disable lowering of indirect inputs

V3D can do indirect inputs so we don't need it. Also, the lowering
produces horrible if-ladder code that is particularly bad for geometry
shaders where inputs are always arrays and shader bodies usually have
a loop indexing into them.

This fixes a couple of geometry shader tests in CTS that would fail to
register allocate otherwise.

There are no changes in shader-db.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: fix primitive queries for geometry shaders

With geometry shaders the number of emitted primitived is decided
at run time, so we cannot precompute it in the CPU and we need to
use the PRIMITIVE_COUNTS_FEEDBACK commands to have the GPU provide
the number like we do for the number of primitives written to
transform feedback. This may have a performance impact though, since
it requires a sync wait for the draw to complete, so we only do
it when geometry shaders are present.

v2: remove '> 0' comparison for ponter type (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: handle writes to gl_Layer from geometry shaders

When geometry shaders write a value to gl_Layer that doesn't correspond to
an existing layer in the target framebuffer the rendering behavior is
undefined according to the spec, however, there are CTS tests that trigger
this scenario on purpose, probably to ensure that nothing terrible happens.

For V3D, this situation is problematic because the binner uses the layer
index to select the offset to write into the tile state data, and we only
allocate tile state for MAX2(num_layers, 1), so we want to make sure we
don't produce values that would lead to out of bounds writes. The simulator
has an assert to catch this, although we haven't observed issues in actual
hardware it is probably best to play safe.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: move layer rendering to a separate helper

This helps with reducing nesting level after adding the loop
to handle layered rendering.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: support rendering to multi-layered framebuffers

When doing layered rendering the binning stage will prepare per-tile
lists for each layer in the framebuffer, so we need to make sure
we allocate enough space for them .

We also need to emit the NUMBER_OF_LAYERS packet. This is required
even when the number of layers is only 1, otherwise the simulator
detects buffer overflows in the tile_state BO during some CTS test
cases involving layered FBOs.

When rendering, we need to emit commands for each layer of the
framebuffer separately and make sure we address the correct layers for
each one.

v2: fixed typo in comment (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: do not limit new CL space allocations with branch to 4096 bytes

For layered rendering we need to emit per layer rendering commands
lists so we we can end up requiring a fairly large buffer for this
if the number of layers is large enough.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>

v3d: remove obsolete assertion

OES_geometry_shader introduced the concept of layered framebuffers.
Removing this assertion gets a bunch of CTS tests to pass. We will
also need layered images to implement layered rendering with geometry
shaders.

v2: fix typo in commit message (Alejandro)

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>