Clifford Wolf [Sun, 23 Dec 2018 14:44:19 +0000 (15:44 +0100)]
Merge branch 'master' of github.com:YosysHQ/yosys
Clifford Wolf [Sat, 22 Dec 2018 19:12:18 +0000 (20:12 +0100)]
Merge pull request #757 from whitequark/manual_mem
manual: document $meminit cell and memory_* passes
whitequark [Fri, 21 Dec 2018 01:26:08 +0000 (01:26 +0000)]
manual: make description of $meminit ports match reality.
Clifford Wolf [Fri, 21 Dec 2018 16:56:43 +0000 (17:56 +0100)]
Merge pull request #758 from whitequark/tcl_script_args
tcl: add support for passing arguments to scripts
Clifford Wolf [Fri, 21 Dec 2018 16:39:52 +0000 (17:39 +0100)]
Merge pull request #759 from whitequark/memory_collect_init_x
memory_collect: do not truncate 'x from \INIT
whitequark [Fri, 21 Dec 2018 02:01:27 +0000 (02:01 +0000)]
memory_collect: do not truncate 'x from \INIT.
The semantics of an RTLIL constant that has less bits than its
declared bit width is zero padding. Therefore, if the output of
memory_collect will be used for simulation, truncating 'x from
the end of \INIT will produce incorrect simulation results.
whitequark [Thu, 20 Dec 2018 07:59:40 +0000 (07:59 +0000)]
manual: fix typos.
whitequark [Thu, 20 Dec 2018 07:29:46 +0000 (07:29 +0000)]
tcl: add support for passing arguments to scripts.
whitequark [Thu, 20 Dec 2018 04:37:28 +0000 (04:37 +0000)]
manual: document $meminit cell and memory_* passes.
Clifford Wolf [Wed, 19 Dec 2018 18:52:31 +0000 (19:52 +0100)]
Merge pull request #752 from Icenowy/anlogic-lut-cost
Anlogic: let LUT5/6 have more cost than LUT4-
Clifford Wolf [Wed, 19 Dec 2018 18:51:10 +0000 (19:51 +0100)]
Merge pull request #753 from Icenowy/anlogic-makefile-fix
anlogic: fix Makefile.inc
Clifford Wolf [Wed, 19 Dec 2018 18:48:54 +0000 (19:48 +0100)]
Merge pull request #749 from Icenowy/anlogic-dram-fix
anlogic: fix dbits of Anlogic Eagle DRAM16X4
Icenowy Zheng [Wed, 19 Dec 2018 02:23:58 +0000 (10:23 +0800)]
anlogic: fix Makefile.inc
During the addition of DRAM inferring support, the installation of
eagle_bb.v is accidentally removed.
Fix this issue.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Wed, 19 Dec 2018 01:36:53 +0000 (09:36 +0800)]
Anlogic: let LUT5/6 have more cost than LUT4-
According to the datasheet of Anlogic Eagle FPGAs, The LUTs natively
in an Anlogic FPGA is LUT4 (in MSLICEs) and "Enhanced LUT5" (in
LSLICEs). An "Enhanced LUT5" can be divided into two LUT4s.
So a LUT5 will cost around 2x resource of a LUT4, and a LUT6 will cost
2x resource of a LUT5.
Change the -lut parameter passed to the abc command to pass this cost
info to the ABC process.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Tue, 18 Dec 2018 19:02:39 +0000 (20:02 +0100)]
Minor style fixes
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 18 Dec 2018 18:59:29 +0000 (19:59 +0100)]
Merge pull request #748 from makaimann/add-btor-ops
Add btor ops for $mul, $div, $mod and $concat
Clifford Wolf [Tue, 18 Dec 2018 18:55:42 +0000 (19:55 +0100)]
Merge pull request #751 from daveshah1/fix_589
memory_dff: Fix typo when checking init value
David Shah [Tue, 18 Dec 2018 17:40:01 +0000 (17:40 +0000)]
memory_dff: Fix typo when checking init value
Signed-off-by: David Shah <davey1576@gmail.com>
Clifford Wolf [Tue, 18 Dec 2018 16:49:38 +0000 (17:49 +0100)]
Fix segfault in AST simplify
(as proposed by Dan Gisselquist)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 18 Dec 2018 15:01:22 +0000 (16:01 +0100)]
Improve src tagging (using names and attrs) of cells and wires in verific front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Icenowy Zheng [Tue, 18 Dec 2018 06:38:44 +0000 (14:38 +0800)]
anlogic: fix dbits of Anlogic Eagle DRAM16X4
The dbits of DRAM16X4 is wrong set to 2, which leads to waste of DRAM
bits.
Fix the dbits number in the RAM configuration.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
makaimann [Mon, 5 Nov 2018 19:49:31 +0000 (11:49 -0800)]
Add btor ops for $mul, $div, $mod and $concat
Clifford Wolf [Mon, 17 Dec 2018 16:16:10 +0000 (17:16 +0100)]
Merge pull request #746 from Icenowy/anlogic-dram
Support for DRAM inferring on Anlogic FPGAs
Clifford Wolf [Mon, 17 Dec 2018 15:35:56 +0000 (16:35 +0100)]
Merge pull request #742 from whitequark/changelog
Update CHANGELOG to mention my improvements
Clifford Wolf [Mon, 17 Dec 2018 15:29:25 +0000 (16:29 +0100)]
Merge pull request #741 from whitequark/ilang_slice_sigspec
read_ilang: allow slicing all sigspecs, not just wires
Clifford Wolf [Mon, 17 Dec 2018 15:26:57 +0000 (16:26 +0100)]
Merge pull request #744 from whitequark/write_verilog_$shift
write_verilog: handle the $shift cell
Icenowy Zheng [Fri, 14 Dec 2018 08:50:37 +0000 (16:50 +0800)]
anlogic: add support for Eagle Distributed RAM
The MSLICEs on the Eagle series of FPGA can be configured as Distributed
RAM.
Enable to synthesis to DRAM.
As the Anlogic software suite doesn't support any 'bx to exist in the
initializtion data of DRAM, do not enable the initialization support of
the inferred DRAM.
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Icenowy Zheng [Fri, 14 Dec 2018 08:46:01 +0000 (16:46 +0800)]
Revert "Leave only real black box cells"
This reverts commit
43030db5fff285de85096aaf5578b0548659f6b7.
For a synthesis tool, generating EG_LOGIC cells are a good choice, as
they can be furtherly optimized when PnR, although sometimes EG_LOGIC is
not as blackbox as EG_PHY cells (because the latter is more close to the
hardware implementation).
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Clifford Wolf [Sun, 16 Dec 2018 20:27:56 +0000 (21:27 +0100)]
Merge pull request #745 from YosysHQ/revert-714-abc_preserve_naming
Revert "Proof-of-concept: preserve naming through ABC using dress"
Clifford Wolf [Sun, 16 Dec 2018 20:27:31 +0000 (21:27 +0100)]
Revert "Proof-of-concept: preserve naming through ABC using dress"
whitequark [Sun, 16 Dec 2018 18:46:32 +0000 (18:46 +0000)]
write_verilog: handle the $shift cell.
The implementation corresponds to the following Verilog, which is
lifted straight from simlib.v:
module \\$shift (A, B, Y);
parameter A_SIGNED = 0;
parameter B_SIGNED = 0;
parameter A_WIDTH = 0;
parameter B_WIDTH = 0;
parameter Y_WIDTH = 0;
input [A_WIDTH-1:0] A;
input [B_WIDTH-1:0] B;
output [Y_WIDTH-1:0] Y;
generate
if (B_SIGNED) begin:BLOCK1
assign Y = $signed(B) < 0 ? A << -B : A >> B;
end else begin:BLOCK2
assign Y = A >> B;
end
endgenerate
endmodule
whitequark [Sun, 16 Dec 2018 18:25:53 +0000 (18:25 +0000)]
Update CHANGELOG.
whitequark [Sun, 16 Dec 2018 17:50:36 +0000 (17:50 +0000)]
read_ilang: allow slicing sigspecs.
Clifford Wolf [Sun, 16 Dec 2018 15:45:49 +0000 (16:45 +0100)]
Merge pull request #736 from whitequark/select_assert_list
select: print selection if a -assert-* flag causes an error
whitequark [Thu, 13 Dec 2018 04:31:58 +0000 (04:31 +0000)]
select: print selection if a -assert-* flag causes an error.
Clifford Wolf [Sun, 16 Dec 2018 15:36:19 +0000 (16:36 +0100)]
Rename "fine:" label to "map:" in "synth_ice40"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 16 Dec 2018 15:31:37 +0000 (16:31 +0100)]
Merge pull request #704 from webhat/feature/fix-awk
Using awk rather than gawk
whitequark [Thu, 13 Dec 2018 04:36:02 +0000 (04:36 +0000)]
write_verilog: add a missing newline.
Clifford Wolf [Sun, 16 Dec 2018 15:05:14 +0000 (16:05 +0100)]
Merge pull request #738 from smunaut/issue_737
verilog_parser: Properly handle recursion when processing attributes
Clifford Wolf [Sun, 16 Dec 2018 15:02:21 +0000 (16:02 +0100)]
Merge pull request #735 from daveshah1/trifixes
deminout fixes
Clifford Wolf [Sun, 16 Dec 2018 15:01:13 +0000 (16:01 +0100)]
Merge pull request #739 from whitequark/patch-1
Add .editorconfig file
whitequark [Sun, 16 Dec 2018 14:57:43 +0000 (14:57 +0000)]
Add .editorconfig file.
See https://editorconfig.org/ for details.
Clifford Wolf [Sun, 16 Dec 2018 14:57:28 +0000 (15:57 +0100)]
Fix equiv_opt indenting
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 16 Dec 2018 14:54:26 +0000 (15:54 +0100)]
Merge pull request #724 from whitequark/equiv_opt
equiv_opt: new command, for verifying optimization passes
Clifford Wolf [Sun, 16 Dec 2018 14:53:44 +0000 (15:53 +0100)]
Merge pull request #734 from grahamedgecombe/fix-shuffled-bram-initdata
memory_bram: Fix initdata bit order after shuffling
Clifford Wolf [Sun, 16 Dec 2018 14:50:42 +0000 (15:50 +0100)]
Merge pull request #730 from smunaut/ffssr_dont_touch
ice40: Honor the "dont_touch" attribute in FFSSR pass
Clifford Wolf [Sun, 16 Dec 2018 14:50:16 +0000 (15:50 +0100)]
Merge pull request #729 from whitequark/write_verilog_initial
write_verilog: correctly map RTLIL `sync init`
Clifford Wolf [Sun, 16 Dec 2018 14:42:04 +0000 (15:42 +0100)]
Merge pull request #725 from olofk/ram4k-init
Only use non-blocking assignments of SB_RAM40_4K for yosys
Clifford Wolf [Sun, 16 Dec 2018 14:41:30 +0000 (15:41 +0100)]
Merge pull request #714 from daveshah1/abc_preserve_naming
Proof-of-concept: preserve naming through ABC using dress
Clifford Wolf [Sun, 16 Dec 2018 14:30:08 +0000 (15:30 +0100)]
Merge pull request #723 from whitequark/synth_ice40_map_gates
synth_ice40: split `map_gates` off `fine`
Clifford Wolf [Sun, 16 Dec 2018 14:28:29 +0000 (15:28 +0100)]
Merge pull request #722 from whitequark/rename_src
rename: add -src, for inferring names from source locations
Clifford Wolf [Sun, 16 Dec 2018 14:27:23 +0000 (15:27 +0100)]
Merge pull request #720 from whitequark/master
lut2mux: handle 1-bit INIT constant in $lut cells
Sylvain Munaut [Thu, 13 Dec 2018 17:47:05 +0000 (18:47 +0100)]
verilog_parser: Properly handle recursion when processing attributes
Fixes #737
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
David Shah [Wed, 12 Dec 2018 17:17:36 +0000 (17:17 +0000)]
deminout: Consider $tribuf cells
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 12 Dec 2018 16:50:46 +0000 (16:50 +0000)]
deminout: Don't demote constant-driven inouts to inputs
Signed-off-by: David Shah <dave@ds0.me>
Graham Edgecombe [Sat, 8 Dec 2018 09:59:56 +0000 (09:59 +0000)]
memory_bram: Fix initdata bit order after shuffling
In some cases the memory_bram pass shuffles the order of the bits in a
memory's RD_DATA port. Although the order of the bits in the WR_DATA and
WR_EN ports is changed to match the RD_DATA port, the order of the bits
in the initialization data is not.
This causes reads of initialized memories to return invalid data (until
the initialization data is overwritten).
This commit fixes the bug by shuffling the initdata bits in exactly the
same order as the RD_DATA/WR_DATA/WR_EN bits.
Clifford Wolf [Mon, 10 Dec 2018 02:43:07 +0000 (03:43 +0100)]
Add yosys-smtbmc support for btor witness
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Sylvain Munaut [Sat, 8 Dec 2018 21:46:28 +0000 (22:46 +0100)]
ice40: Honor the "dont_touch" attribute in FFSSR pass
This is useful if you want to place FF manually ... can't merge SR in those
because it might make the manual placement invalid
Signed-off-by: Sylvain Munaut <tnt@246tNt.com>
Clifford Wolf [Sat, 8 Dec 2018 05:59:27 +0000 (06:59 +0100)]
Add "yosys-smtbmc --btorwit" skeleton
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 8 Dec 2018 05:21:31 +0000 (06:21 +0100)]
Fix btor init value handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Fri, 7 Dec 2018 18:48:06 +0000 (18:48 +0000)]
write_verilog: correctly map RTLIL `sync init`.
whitequark [Fri, 7 Dec 2018 16:58:33 +0000 (16:58 +0000)]
equiv_opt: pass -D EQUIV when techmapping.
This allows avoiding techmap crashes e.g. because of large memories
in white-box cell models.
whitequark [Thu, 6 Dec 2018 14:28:20 +0000 (14:28 +0000)]
equiv_opt: new command, for verifying optimization passes.
David Shah [Fri, 7 Dec 2018 17:17:26 +0000 (17:17 +0000)]
Merge pull request #727 from whitequark/opt_lut
opt_lut: leave intact LUTs with cascade feeding module outputs
whitequark [Fri, 7 Dec 2018 17:13:52 +0000 (17:13 +0000)]
opt_lut: leave intact LUTs with cascade feeding module outputs.
whitequark [Fri, 7 Dec 2018 17:04:41 +0000 (17:04 +0000)]
opt_lut: show original truth table for both cells.
whitequark [Fri, 7 Dec 2018 16:31:15 +0000 (16:31 +0000)]
opt_lut: add -limit option, for debugging misoptimizations.
Olof Kindgren [Thu, 6 Dec 2018 20:45:59 +0000 (21:45 +0100)]
Only use non-blocking assignments of SB_RAM40_4K for yosys
In an initial statement, blocking assignments are normally used
and e.g. verilator throws a warning if non-blocking ones are used.
Yosys cannot however properly resolve the interdependencies if
blocking assignments are used in the initialization of SB_RAM_40_4K
and thus this has been used.
This patch will change to use non-blocking assignments only for yosys
David Shah [Tue, 4 Dec 2018 14:17:47 +0000 (14:17 +0000)]
abc: Preserve naming through ABC using 'dress' command
Signed-off-by: David Shah <dave@ds0.me>
whitequark [Thu, 6 Dec 2018 12:02:42 +0000 (12:02 +0000)]
synth_ice40: split `map_gates` off `fine`.
Clifford Wolf [Thu, 6 Dec 2018 06:29:37 +0000 (07:29 +0100)]
Add missing .gitignore
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 6 Dec 2018 06:29:21 +0000 (07:29 +0100)]
Bugfix in opt_expr handling of a<0 and a>=0
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 6 Dec 2018 06:21:50 +0000 (07:21 +0100)]
Verific updates
Signed-off-by: Clifford Wolf <clifford@clifford.at>
whitequark [Wed, 5 Dec 2018 20:34:53 +0000 (20:34 +0000)]
rename: add -src, for inferring names from source locations.
whitequark [Wed, 5 Dec 2018 19:27:48 +0000 (19:27 +0000)]
lut2mux: handle 1-bit INIT constant in $lut cells.
This pass already handles INIT constants shorter than 2^width, but
that was not done for the recursion base case.
whitequark [Wed, 5 Dec 2018 19:12:02 +0000 (19:12 +0000)]
opt_lut: simplify type conversion. NFC.
Clifford Wolf [Wed, 5 Dec 2018 17:19:44 +0000 (09:19 -0800)]
Merge pull request #709 from smunaut/issue_708
Make return value of $clog2 signed
Clifford Wolf [Wed, 5 Dec 2018 17:16:35 +0000 (09:16 -0800)]
Merge pull request #718 from whitequark/gate2lut
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs
whitequark [Wed, 5 Dec 2018 05:24:15 +0000 (05:24 +0000)]
synth_ice40: add -noabc option, to use built-in LUT techmapping.
This should be combined with -relut to get sensible results.
whitequark [Wed, 5 Dec 2018 04:50:38 +0000 (04:50 +0000)]
gate2lut: new techlib, for converting Yosys gates to FPGA LUTs.
whitequark [Wed, 5 Dec 2018 04:32:01 +0000 (04:32 +0000)]
Fix typo.
Clifford Wolf [Wed, 5 Dec 2018 17:08:30 +0000 (09:08 -0800)]
Merge pull request #713 from Diego-HR/master
Changes in GoWin synth commands and ALU primitive support
Clifford Wolf [Wed, 5 Dec 2018 17:08:04 +0000 (09:08 -0800)]
Merge pull request #712 from mmicko/anlogic-support
Initial support for Anlogic FPGA
Clifford Wolf [Wed, 5 Dec 2018 17:03:58 +0000 (18:03 +0100)]
Rename opt_lut.cpp to opt_lut.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 5 Dec 2018 17:02:13 +0000 (09:02 -0800)]
Merge pull request #717 from whitequark/opt_lut
Add a new opt_lut pass, which combines inefficiently packed LUTs
Clifford Wolf [Wed, 5 Dec 2018 16:59:21 +0000 (08:59 -0800)]
Merge pull request #716 from whitequark/ice40_unlut
Extract ice40_unlut pass from ice40_opt
whitequark [Wed, 5 Dec 2018 15:26:40 +0000 (15:26 +0000)]
opt_lut: add -dlogic, to avoid disturbing logic such as carry chains.
whitequark [Wed, 5 Dec 2018 13:14:44 +0000 (13:14 +0000)]
opt_lut: always prefer to eliminate 1-LUTs.
These are always either buffers or inverters, and keeping the larger
LUT preserves more source-level information about the design.
whitequark [Wed, 5 Dec 2018 12:35:27 +0000 (12:35 +0000)]
opt_lut: collect and display statistics.
whitequark [Wed, 5 Dec 2018 12:26:41 +0000 (12:26 +0000)]
opt_lut: refactor to use a worker. NFC.
whitequark [Wed, 5 Dec 2018 00:28:03 +0000 (00:28 +0000)]
synth_ice40: add -relut option, to run ice40_unlut and opt_lut.
whitequark [Wed, 5 Dec 2018 00:23:22 +0000 (00:23 +0000)]
opt_lut: new pass, to combine LUTs for tighter packing.
whitequark [Tue, 4 Dec 2018 19:43:33 +0000 (19:43 +0000)]
Extract ice40_unlut pass from ice40_opt.
Currently, `ice40_opt -unlut` would map SB_LUT4 to $lut and convert
them back to logic immediately. This is not desirable if the goal
is to operate on $lut cells. If this is desirable, the same result
as `ice40_opt -unlut` can be achieved by running simplemap and opt
after ice40_unlut.
Serge Bazanski [Wed, 5 Dec 2018 16:22:14 +0000 (17:22 +0100)]
Merge pull request #719 from YosysHQ/q3k/flailing-around-trying-to-fix-osx
Fix Travis on OSX
Sergiusz Bazanski [Wed, 5 Dec 2018 10:50:58 +0000 (11:50 +0100)]
travis/osx: fix, use clang instead of gcc
Clifford Wolf [Tue, 4 Dec 2018 22:30:23 +0000 (23:30 +0100)]
Fix typo
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 4 Dec 2018 22:29:21 +0000 (14:29 -0800)]
Merge pull request #702 from smunaut/min_ce_use
Add option to only use DFFE is the resulting E signal would be use > N times
Diego H [Tue, 4 Dec 2018 02:08:35 +0000 (20:08 -0600)]
Changes in GoWin synth commands and ALU primitive support
Miodrag Milanovic [Sun, 2 Dec 2018 10:57:50 +0000 (11:57 +0100)]
Leave only real black box cells
Miodrag Milanovic [Sat, 1 Dec 2018 17:28:54 +0000 (18:28 +0100)]
Initial support for Anlogic FPGA