Sebastien Bourdeauducq [Wed, 4 Nov 2015 08:37:33 +0000 (16:37 +0800)]
Merge 'new' branch
Sebastien Bourdeauducq [Wed, 4 Nov 2015 06:57:48 +0000 (14:57 +0800)]
integration/builder: add gateware toolchain path command line switch
Sebastien Bourdeauducq [Tue, 3 Nov 2015 16:31:53 +0000 (00:31 +0800)]
software/makefiles: remove dependency system, make all always a phony target
Sebastien Bourdeauducq [Tue, 3 Nov 2015 16:29:56 +0000 (00:29 +0800)]
targets/pipistrello: add argparse functions consistent with kc705
Sebastien Bourdeauducq [Tue, 3 Nov 2015 10:46:34 +0000 (18:46 +0800)]
targets/kc705: export generic argparse code
Sebastien Bourdeauducq [Tue, 3 Nov 2015 10:45:58 +0000 (18:45 +0800)]
targets/kc705: make SDRAM controller type configurable
Sebastien Bourdeauducq [Tue, 3 Nov 2015 10:45:23 +0000 (18:45 +0800)]
interconnect/wishbone: fix CSRBank init
Sebastien Bourdeauducq [Tue, 3 Nov 2015 02:37:31 +0000 (10:37 +0800)]
wishbone: add read/write simulation methods
Sebastien Bourdeauducq [Mon, 2 Nov 2015 04:30:52 +0000 (12:30 +0800)]
Revert "conda: try to hack conda into checking out new branch directly"
This reverts commit
1b11b7fa862852e95a80c98bae0de9fe9169560b.
Sebastien Bourdeauducq [Mon, 2 Nov 2015 04:28:43 +0000 (12:28 +0800)]
conda: try to hack conda into checking out new branch directly
Sebastien Bourdeauducq [Mon, 2 Nov 2015 03:52:42 +0000 (11:52 +0800)]
travis: add dummy script
Sebastien Bourdeauducq [Mon, 2 Nov 2015 03:52:28 +0000 (11:52 +0800)]
conda: consistent version numbering
Sebastien Bourdeauducq [Mon, 2 Nov 2015 03:20:26 +0000 (11:20 +0800)]
add travis.yml
Sebastien Bourdeauducq [Sun, 1 Nov 2015 16:03:10 +0000 (00:03 +0800)]
add conda build scripts
Sebastien Bourdeauducq [Sun, 1 Nov 2015 14:38:06 +0000 (22:38 +0800)]
cores/dvi_sampler: fix imports
Sebastien Bourdeauducq [Sun, 1 Nov 2015 14:15:28 +0000 (22:15 +0800)]
interconnect/stream: add Converter (needs cleanup)
Sebastien Bourdeauducq [Sat, 24 Oct 2015 14:54:44 +0000 (22:54 +0800)]
compiler_rt: add comparesf2
Florent Kermarrec [Fri, 23 Oct 2015 18:29:04 +0000 (20:29 +0200)]
cores/liteeth_mini: adapt all phys to new migen
Florent Kermarrec [Fri, 23 Oct 2015 18:23:33 +0000 (20:23 +0200)]
com/liteethmini/phy: remove use of FlipFlop in MII
Florent Kermarrec [Fri, 23 Oct 2015 18:09:54 +0000 (20:09 +0200)]
cores: fix liteeth
Sebastien Bourdeauducq [Mon, 19 Oct 2015 08:30:41 +0000 (16:30 +0800)]
MANIFEST.in: fix lm32 data directory
Sebastien Bourdeauducq [Mon, 19 Oct 2015 03:33:21 +0000 (11:33 +0800)]
software: do not build libdyld and libunwind for lm32. Closes #22
Sebastien Bourdeauducq [Wed, 14 Oct 2015 13:45:36 +0000 (21:45 +0800)]
integration/builder: escape backslash in makefile defines
Sebastien Bourdeauducq [Wed, 14 Oct 2015 03:11:06 +0000 (11:11 +0800)]
Merge branch 'new' of github.com:m-labs/misoc into new
Sebastien Bourdeauducq [Wed, 14 Oct 2015 03:09:53 +0000 (11:09 +0800)]
integration/builder: fix building for SoCSDRAM-based targets when SDRAM is disabled
Reported by Florent Kermarrec
Florent Kermarrec [Tue, 13 Oct 2015 16:13:00 +0000 (18:13 +0200)]
software/bios: move romboot after serialboot and netboot
On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
Florent Kermarrec [Tue, 13 Oct 2015 15:49:29 +0000 (17:49 +0200)]
software/bios: move romboot after serialboot and netboot
On designs using romboot (firmware embedded in ram blocks), we generally upload new firmwares with serialboot and netboot for prototyping.
Moving romboot after serialboot and netboot avoid manual interrupts of the boot sequence.
Sebastien Bourdeauducq [Mon, 5 Oct 2015 04:07:55 +0000 (12:07 +0800)]
setup: include software and Verilog files
Broken on Python 3.5
error: can't copy 'misoc/software': doesn't exist or not a regular file
Florent Kermarrec [Sun, 4 Oct 2015 22:10:55 +0000 (00:10 +0200)]
interconnect/stream: add missing part of Demultiplexer
Sebastien Bourdeauducq [Sun, 4 Oct 2015 16:45:02 +0000 (00:45 +0800)]
setup: add entry points
Sebastien Bourdeauducq [Sun, 4 Oct 2015 16:44:50 +0000 (00:44 +0800)]
setup: fix readme
Sebastien Bourdeauducq [Fri, 2 Oct 2015 03:17:47 +0000 (11:17 +0800)]
sdram: cleanup
Sebastien Bourdeauducq [Wed, 30 Sep 2015 12:17:37 +0000 (20:17 +0800)]
liteeth_mini: fix imports, replace Counter and FlipFlop
Sebastien Bourdeauducq [Wed, 30 Sep 2015 11:43:14 +0000 (19:43 +0800)]
interconnect/stream: add multiplexer and demultiplexer
Sebastien Bourdeauducq [Wed, 30 Sep 2015 08:40:34 +0000 (16:40 +0800)]
interconnect/stream: remove param, do not depend on FIFO Record support
Sebastien Bourdeauducq [Wed, 30 Sep 2015 08:40:04 +0000 (16:40 +0800)]
lasmicon: do not depend on FIFO Record support
Sebastien Bourdeauducq [Tue, 29 Sep 2015 10:14:54 +0000 (18:14 +0800)]
command line options support, CSR CSV, all targets building
Sebastien Bourdeauducq [Tue, 29 Sep 2015 10:14:19 +0000 (18:14 +0800)]
flterm: cleanup
Sebastien Bourdeauducq [Tue, 29 Sep 2015 10:13:59 +0000 (18:13 +0800)]
cores/gpio: fix import
Sebastien Bourdeauducq [Tue, 29 Sep 2015 02:19:42 +0000 (10:19 +0800)]
soc_core: simplify settings (assume CPU and CSR present)
Sebastien Bourdeauducq [Tue, 29 Sep 2015 02:19:00 +0000 (10:19 +0800)]
minor fixes
Sebastien Bourdeauducq [Mon, 28 Sep 2015 12:40:37 +0000 (20:40 +0800)]
Merge branch 'master' of github.com:m-labs/misoc
Sebastien Bourdeauducq [Mon, 28 Sep 2015 12:40:31 +0000 (20:40 +0800)]
Revert "Sort constants in csr generation."
This reverts commit
d628c147ecb92c871cc68e2f29511c600861fcb9.
Sebastien Bourdeauducq [Mon, 28 Sep 2015 12:33:37 +0000 (20:33 +0800)]
basic out-of-tree build support (OK on PPro)
whitequark [Mon, 28 Sep 2015 09:37:55 +0000 (12:37 +0300)]
Fix typo.
Sebastien Bourdeauducq [Mon, 28 Sep 2015 05:02:13 +0000 (13:02 +0800)]
move software into misoc
Tim 'mithro' Ansell [Sat, 26 Sep 2015 07:57:43 +0000 (17:57 +1000)]
Sort constants in csr generation.
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.
With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
CSR=software/include/generated/csr.h
for i in 1 2 3 4 5 6; do
rm -f $CSR; python make.py build-headers
cp $CSR $CSR.$i
done
md5sum $CSR.*
```
Tim 'mithro' Ansell [Sat, 26 Sep 2015 07:57:43 +0000 (17:57 +1000)]
Sort constants in csr generation.
Previously the order of constant output depended on Python's hashing order
which changes every run. This caused the file to change every run.
With this change the csr.h file will always be the same. This can be verified
this with the following;
```bash
CSR=software/include/generated/csr.h
for i in 1 2 3 4 5 6; do
rm -f $CSR; python make.py build-headers
cp $CSR $CSR.$i
done
md5sum $CSR.*
```
Sebastien Bourdeauducq [Sat, 26 Sep 2015 13:55:11 +0000 (21:55 +0800)]
Revert "Use shutil rather then rm -rf command."
This reverts commit
d8fd4fe7257eea9efe252376305b716b2f51840f.
Sebastien Bourdeauducq [Sat, 26 Sep 2015 13:54:19 +0000 (21:54 +0800)]
Revert "Use shutil rather then rm -rf command."
This reverts commit
d8fd4fe7257eea9efe252376305b716b2f51840f.
Sebastien Bourdeauducq [Sat, 26 Sep 2015 13:51:22 +0000 (21:51 +0800)]
sdram working on PPro
Sebastien Bourdeauducq [Sat, 26 Sep 2015 10:50:11 +0000 (18:50 +0800)]
replace flen with len
Sebastien Bourdeauducq [Sat, 26 Sep 2015 08:44:06 +0000 (16:44 +0800)]
add stream, fix CPUs and more imports. simple target boots on ppro.
Sebastien Bourdeauducq [Fri, 25 Sep 2015 10:43:20 +0000 (18:43 +0800)]
fix most imports
Sebastien Bourdeauducq [Thu, 24 Sep 2015 12:48:18 +0000 (20:48 +0800)]
interconnect: add bus/bank components from Migen
Sebastien Bourdeauducq [Thu, 24 Sep 2015 08:01:08 +0000 (16:01 +0800)]
lasmicon: enable refresh at all times
Sebastien Bourdeauducq [Thu, 24 Sep 2015 07:59:55 +0000 (15:59 +0800)]
break down sdram, improve consistency of core names
Sebastien Bourdeauducq [Thu, 24 Sep 2015 01:05:10 +0000 (09:05 +0800)]
cores directory
Sebastien Bourdeauducq [Wed, 23 Sep 2015 16:18:27 +0000 (00:18 +0800)]
reorganization WIP: flatten core structure (SDRAM still needs to be done)
Sebastien Bourdeauducq [Wed, 23 Sep 2015 01:52:12 +0000 (09:52 +0800)]
setup: cleanup
Sebastien Bourdeauducq [Wed, 23 Sep 2015 01:50:31 +0000 (09:50 +0800)]
setup: convert to unix eols
Sebastien Bourdeauducq [Tue, 22 Sep 2015 16:57:36 +0000 (00:57 +0800)]
CONTRIBUTING.md->rst
Sebastien Bourdeauducq [Tue, 22 Sep 2015 16:36:47 +0000 (00:36 +0800)]
migen.fhdl.std -> migen
Sebastien Bourdeauducq [Tue, 22 Sep 2015 16:35:02 +0000 (00:35 +0800)]
misoclib -> misoc
Rohit Kumar Singh [Mon, 21 Sep 2015 15:39:48 +0000 (21:09 +0530)]
Add init file in sdram/phy dir
Without __init__.py file, when using setup.py, setuptools' find_package() function does not find the files in sdram/phy package. Hence .egg file entirely misses sdram/phy directory
More info here: https://bitbucket.org/pypa/setuptools/issues/97
Florent Kermarrec [Mon, 21 Sep 2015 07:04:59 +0000 (09:04 +0200)]
uart/software: remove litescope dependency
Tim 'mithro' Ansell [Sun, 20 Sep 2015 13:09:16 +0000 (23:09 +1000)]
Adding --help option to flterm.
Florent Kermarrec [Thu, 10 Sep 2015 18:51:10 +0000 (20:51 +0200)]
dvisampler/edid: fix sda sampling, needs to be similar to scl.
Video sources with high scl frequency were not able to access EDID information through I2C.
I2C start was not detected correctly and was randomly reseting the fsm during transfers.(seen with litescope)
Tim 'mithro' Ansell [Tue, 8 Sep 2015 15:15:15 +0000 (08:15 -0700)]
Allow installing tools to a prefix.
(Defaults to /usr/local.)
Florent Kermarrec [Mon, 7 Sep 2015 22:58:03 +0000 (00:58 +0200)]
create liteethmini and move liteeth to a separate repo (https://github.com/enjoy-digital/liteeth)
LiteEthMini is a subset of LiteEth intended to be used with a CPU and a software stack.
Florent Kermarrec [Mon, 7 Sep 2015 11:19:12 +0000 (13:19 +0200)]
remove litepcie_phy_wrappers submodule
Florent Kermarrec [Mon, 7 Sep 2015 10:46:37 +0000 (12:46 +0200)]
targets: remove USBSoC from minispartan6 (example available here: https://github.com/enjoy-digital/scarab-soc)
Florent Kermarrec [Mon, 7 Sep 2015 10:44:47 +0000 (12:44 +0200)]
move liteusb to a separate repo (https://github.com/enjoy-digital/liteusb)
Florent Kermarrec [Mon, 7 Sep 2015 10:26:52 +0000 (12:26 +0200)]
move litesata to a separate repo (https://github.com/enjoy-digital/litesata)
Florent Kermarrec [Mon, 7 Sep 2015 10:01:48 +0000 (12:01 +0200)]
move litescope to a separate repo (https://github.com/enjoy-digital/litescope)
Florent Kermarrec [Mon, 7 Sep 2015 09:11:43 +0000 (11:11 +0200)]
move litepcie to a separate repo (https://github.com/enjoy-digital/litepcie)
Florent Kermarrec [Tue, 1 Sep 2015 14:57:50 +0000 (16:57 +0200)]
misoclib/soc: fix add_constant when used for strings
Florent Kermarrec [Wed, 26 Aug 2015 20:36:48 +0000 (22:36 +0200)]
litecores: remove unneeded AutoCSR inheritance in example designs (thanks William D. Jones)
Florent Kermarrec [Mon, 24 Aug 2015 18:12:39 +0000 (20:12 +0200)]
litescope/core/port: fix missing self.comb...
Florent Kermarrec [Mon, 24 Aug 2015 17:40:53 +0000 (19:40 +0200)]
litescope/core/port: fix EdgeDetector CSRs names
Florent Kermarrec [Mon, 24 Aug 2015 16:15:13 +0000 (18:15 +0200)]
litescope/core/port: fix LiteScopeEdgeDetector (refactoring issues)
Florent Kermarrec [Sat, 22 Aug 2015 14:30:42 +0000 (16:30 +0200)]
liteth/phy: simplify clk_freq in LiteEthPHY autodetect function (thanks Sebastien)
Florent Kermarrec [Sat, 22 Aug 2015 10:50:41 +0000 (12:50 +0200)]
sdram/phy/s6ddrphy: fix comment on S6QuarterRateDDRPHY
Florent Kermarrec [Sat, 22 Aug 2015 10:42:44 +0000 (12:42 +0200)]
sdram/module: add P3R1GE4JGF DDR2 (Atlys) and MT41J128M16 DDR3 (Opsis, Novena) modules.
Florent Kermarrec [Sat, 22 Aug 2015 10:15:53 +0000 (12:15 +0200)]
sdram/phy/s6ddrphy: add S6QuarterRateDDRPHY to run DDR3 at higher frequencies.
Built on top of S6HalfRateDDRPHY, exposes a 4 phases DFI interface to the controller with a 2x slower clock.
Validated on the Numato Lab opsis board (50MHz sys_clk/ DDR400), should also work on the Novena laptop (same DDR3 module).
Florent Kermarrec [Sat, 22 Aug 2015 10:08:49 +0000 (12:08 +0200)]
liteeth/phy: fix autodetect (clk_freq not necessary passed in kwargs)
Florent Kermarrec [Sat, 22 Aug 2015 09:47:26 +0000 (11:47 +0200)]
sdram/phy/s6ddrphy: rename S6DDRPHY to S6HalfRateDDRPHY and use ORed wrdata_en/rddata_en (the controller already manages that)
Florent Kermarrec [Sat, 22 Aug 2015 09:39:54 +0000 (11:39 +0200)]
README: small update
Florent Kermarrec [Thu, 20 Aug 2015 20:15:06 +0000 (22:15 +0200)]
sdram/module: cleanup indent
Florent Kermarrec [Tue, 18 Aug 2015 23:06:48 +0000 (01:06 +0200)]
litecores: add -Ob option to make.py (allow to build with yosys for example)
Florent Kermarrec [Tue, 18 Aug 2015 23:07:41 +0000 (01:07 +0200)]
liteeth/phy: only use clk_freq for LiteEthPHYGMIIMII in autodetect
Florent Kermarrec [Tue, 18 Aug 2015 13:47:09 +0000 (15:47 +0200)]
tools/flterm: replace int(a, 16) with int(a, 0) for --kernel-adr
Florent Kermarrec [Thu, 13 Aug 2015 11:24:39 +0000 (13:24 +0200)]
tools/flterm.py: cleanup kernel-adr argument parsing
Tim 'mithro' Ansell [Wed, 12 Aug 2015 11:28:50 +0000 (12:28 +0100)]
Use shutil rather then rm -rf command.
Tim 'mithro' Ansell [Wed, 12 Aug 2015 11:28:49 +0000 (12:28 +0100)]
Use shell for globbing in clean.
Tim 'mithro' Ansell [Wed, 12 Aug 2015 11:28:48 +0000 (12:28 +0100)]
All commands run should be checked.
Florent Kermarrec [Wed, 12 Aug 2015 09:41:08 +0000 (11:41 +0200)]
tools/flterm.py: some cleanup and fix last frame data that was not transmitted
whitequark [Mon, 10 Aug 2015 13:23:02 +0000 (16:23 +0300)]
unwinder: update.
whitequark [Sat, 8 Aug 2015 12:21:09 +0000 (15:21 +0300)]
libdyld: add const qualifiers.
whitequark [Sat, 8 Aug 2015 09:16:27 +0000 (12:16 +0300)]
libbase: add const qualifiers.