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Clifford Wolf [Wed, 27 Feb 2013 16:26:32 +0000 (17:26 +0100)]
Added extract -verbose and -map ilang support
Clifford Wolf [Wed, 27 Feb 2013 15:27:20 +0000 (16:27 +0100)]
Implemented basic functionality of "extract" pass
Clifford Wolf [Wed, 27 Feb 2013 12:35:30 +0000 (13:35 +0100)]
Added support for constant signals in "extract" pass
Clifford Wolf [Wed, 27 Feb 2013 12:25:18 +0000 (13:25 +0100)]
Added "extract" pass (not functional yet)
Clifford Wolf [Wed, 27 Feb 2013 09:36:17 +0000 (10:36 +0100)]
Added some additional TODO items
Clifford Wolf [Wed, 27 Feb 2013 08:45:09 +0000 (09:45 +0100)]
Fixed typo in README
Clifford Wolf [Wed, 27 Feb 2013 08:41:04 +0000 (09:41 +0100)]
Added copyright statement to readme file
Clifford Wolf [Wed, 27 Feb 2013 08:32:19 +0000 (09:32 +0100)]
Moved stand-alone libs to libs/ directory and added libs/subcircuit
Clifford Wolf [Tue, 26 Feb 2013 12:18:22 +0000 (13:18 +0100)]
Added support for verilog genblock[index].member syntax
Clifford Wolf [Sun, 24 Feb 2013 08:08:07 +0000 (00:08 -0800)]
Merge pull request #2 from mschmoelzer/master
"fsm_export" pass: fix KISS file generation.
Martin Schmölzer [Sat, 23 Feb 2013 17:22:19 +0000 (18:22 +0100)]
"fsm_export" pass: fix KISS file generation.
The KISS file format now follows the conventions specified in
"Logic Synthesis and Optimization Benchmarks User Guide", Version 3.0
by Saeyang Yang.
This change ensures interoperability with the "trfsmgen" program by Johann
Glaser.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
Clifford Wolf [Wed, 16 Jan 2013 16:32:11 +0000 (17:32 +0100)]
Added support for "always @(*)"
Clifford Wolf [Tue, 8 Jan 2013 10:20:24 +0000 (02:20 -0800)]
Merge pull request #1 from mschmoelzer/master
Add support for "fsm_export" synthesis attributes to fsm_export pass
Martin Schmölzer [Tue, 8 Jan 2013 08:53:40 +0000 (09:53 +0100)]
Merge remote-tracking branch 'upstream/master'
Martin Schmölzer [Tue, 8 Jan 2013 08:31:31 +0000 (09:31 +0100)]
Add support for "fsm_export" synthesis attributes to fsm_export pass.
This allows to specify the file name for exported files directly in the HDL
source via the fsm_export=... attribute on the FSM state register.
Verilog example:
(* fsm_export="my_fsm.kiss2" *)
reg [3:0] state;
The fsm_export pass now also accepts the option "-noauto". This causes only
FSMs with the fsm_export attribute to be exported, any other FSMs are ignored.
Signed-off-by: Martin Schmölzer <martin.schmoelzer@student.tuwien.ac.at>
Clifford Wolf [Sun, 6 Jan 2013 13:40:15 +0000 (14:40 +0100)]
Added "getting started" section to README
Clifford Wolf [Sun, 6 Jan 2013 12:50:30 +0000 (13:50 +0100)]
Improvements in command shell
- Added 'shell' command (run interactive shell from synth script)
- Added support for ; as cmd seperator as in "proc; opt"
- Fixed c++ static initialization order problem with pass register
Clifford Wolf [Sat, 5 Jan 2013 11:27:59 +0000 (12:27 +0100)]
Added a:*=* syntax to select framework
Clifford Wolf [Sat, 5 Jan 2013 11:27:18 +0000 (12:27 +0100)]
Added qtcreator.creator.user to top level .gitignore
Clifford Wolf [Sat, 5 Jan 2013 10:44:47 +0000 (11:44 +0100)]
Copy attributes from state signal to fsm cell
Clifford Wolf [Sat, 5 Jan 2013 10:44:29 +0000 (11:44 +0100)]
More .gitignore and fixed "make mrproper"
Clifford Wolf [Sat, 5 Jan 2013 10:35:52 +0000 (11:35 +0100)]
added more .gitignore files (make test)
Clifford Wolf [Sat, 5 Jan 2013 10:19:11 +0000 (11:19 +0100)]
added .gitignore files
Clifford Wolf [Sat, 5 Jan 2013 10:13:26 +0000 (11:13 +0100)]
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