Clifford Wolf [Mon, 12 Nov 2018 08:09:22 +0000 (09:09 +0100)]
Merge pull request #697 from eddiehung/xilinx_ps7
Add support for PS7 block for Xilinx
Clifford Wolf [Mon, 12 Nov 2018 08:08:49 +0000 (09:08 +0100)]
Merge pull request #695 from daveshah1/ecp5_bb
ecp5: Adding some blackbox cells
Eddie Hung [Sat, 10 Nov 2018 20:37:45 +0000 (12:37 -0800)]
Add support for Xilinx PS7 block
Clifford Wolf [Fri, 9 Nov 2018 20:03:13 +0000 (21:03 +0100)]
Set Verific flag vhdl_support_variable_slice=1
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Fri, 9 Nov 2018 18:25:42 +0000 (18:25 +0000)]
ecp5: Add 'fake' DCU parameters
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 9 Nov 2018 15:18:30 +0000 (15:18 +0000)]
ecp5: Add blackboxes for ancillary DCU cells
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 9 Nov 2018 12:02:49 +0000 (13:02 +0100)]
Merge pull request #696 from arjenroodselaar/verific_darwin
Use appropriate static libraries when building with Verific on MacOS
Clifford Wolf [Thu, 8 Nov 2018 08:58:47 +0000 (09:58 +0100)]
Fix "make ystests" to use correct Yosys binary
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Arjen Roodselaar [Thu, 8 Nov 2018 07:18:47 +0000 (23:18 -0800)]
Use appropriate static libraries when building with Verific on MacOS
Clifford Wolf [Wed, 7 Nov 2018 19:16:40 +0000 (20:16 +0100)]
Merge pull request #693 from YosysHQ/rlimit
improve rlimit handling in smtio.py
David Shah [Wed, 7 Nov 2018 14:56:38 +0000 (14:56 +0000)]
ecp5: Adding some blackbox cells
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Wed, 7 Nov 2018 14:32:34 +0000 (15:32 +0100)]
Limit stack size to 16 MB on Darwin
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Nov 2018 11:21:05 +0000 (12:21 +0100)]
Merge pull request #694 from trcwm/dffmap_expr_fix
DFFLIBMAP: changed 'missing pin' error into a warning.
Niels Moseley [Tue, 6 Nov 2018 11:11:52 +0000 (12:11 +0100)]
DFFLIBMAP: changed 'missing pin' error into a warning with additional reason/info.
Clifford Wolf [Tue, 6 Nov 2018 10:11:05 +0000 (11:11 +0100)]
Run solver in non-incremental mode whem smtio.py is configured for non-incremental solving
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Nov 2018 10:10:27 +0000 (11:10 +0100)]
Update ABC rev to
4d56acf
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Nov 2018 09:09:03 +0000 (10:09 +0100)]
Fix for improved smtio.py rlimit code
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 6 Nov 2018 09:05:23 +0000 (10:05 +0100)]
Improve stack rlimit code in smtio.py
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 5 Nov 2018 11:33:21 +0000 (12:33 +0100)]
Allow square brackets in liberty identifiers
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Mon, 5 Nov 2018 08:19:56 +0000 (09:19 +0100)]
Merge pull request #691 from arjenroodselaar/stacksize
Use conservative stack size for SMT2 on MacOS
Arjen Roodselaar [Mon, 5 Nov 2018 05:58:09 +0000 (21:58 -0800)]
Use conservative stack size for SMT2 on MacOS
Clifford Wolf [Sun, 4 Nov 2018 14:57:17 +0000 (15:57 +0100)]
Add warning for SV "restrict" without "property"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 4 Nov 2018 13:41:28 +0000 (14:41 +0100)]
Add proper error message for when smtbmc "append" fails
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 4 Nov 2018 09:19:32 +0000 (10:19 +0100)]
Various indenting fixes in AST front-end (mostly space vs tab issues)
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sun, 4 Nov 2018 09:08:33 +0000 (10:08 +0100)]
Merge pull request #687 from trcwm/master
Liberty file: error when it contains pin references to non-existing pins
Clifford Wolf [Sun, 4 Nov 2018 09:04:48 +0000 (10:04 +0100)]
Merge pull request #688 from ZipCPU/rosenfell
Make rose and fell dependent upon LSB only
ZipCPU [Sat, 3 Nov 2018 17:39:32 +0000 (13:39 -0400)]
Make and dependent upon LSB only
Niels Moseley [Sat, 3 Nov 2018 17:38:49 +0000 (18:38 +0100)]
Liberty file newline handling is more relaxed. More descriptive error message
Niels Moseley [Sat, 3 Nov 2018 17:07:51 +0000 (18:07 +0100)]
Report an error when a liberty file contains pin references that reference non-existing pins
Clifford Wolf [Thu, 1 Nov 2018 14:25:24 +0000 (15:25 +0100)]
Do not generate "reg assigned in a continuous assignment" warnings for "rand reg"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 1 Nov 2018 10:40:58 +0000 (11:40 +0100)]
Add support for signed $shift/$shiftx in smt2 back-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 31 Oct 2018 14:37:39 +0000 (15:37 +0100)]
Merge branch 'igloo2'
Clifford Wolf [Wed, 31 Oct 2018 14:36:53 +0000 (15:36 +0100)]
Fix sf2 LUT interface
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 31 Oct 2018 14:28:57 +0000 (15:28 +0100)]
Basic SmartFusion2 and IGLOO2 synthesis support
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 30 Oct 2018 10:25:07 +0000 (11:25 +0100)]
Merge pull request #680 from jburgess777/fix-empty-string-back-assert
Avoid assert when label is an empty string
Jon Burgess [Sun, 28 Oct 2018 14:49:09 +0000 (14:49 +0000)]
Avoid assert when label is an empty string
Calling back() on an empty string is not allowed and triggers
an assert with recent gcc:
$ cd manual/PRESENTATION_Intro
$ ../../yosys counter.ys
...
/usr/include/c++/8/bits/basic_string.h:1136: std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::back() [with _CharT = char; _Traits = std::char_traits<char>; _Alloc = std::allocator<char>; std::__cxx11::basic_string<_CharT, _Traits, _Alloc>::reference = char&]: Assertion '!empty()' failed.
802 if (label.back() == ':' && GetSize(label) > 1)
(gdb) p label
$1 = ""
Clifford Wolf [Thu, 25 Oct 2018 11:23:26 +0000 (13:23 +0200)]
Merge pull request #678 from whentze/master
Fix unhandled std::out_of_range in run_frontend() due to integer underflow
Clifford Wolf [Thu, 25 Oct 2018 11:20:00 +0000 (13:20 +0200)]
Fix minor typo in error message
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 25 Oct 2018 11:18:59 +0000 (13:18 +0200)]
Merge pull request #679 from udif/pr_syntax_error
More meaningful SystemVerilog/Verilog parser error messages
Udi Finkelstein [Wed, 24 Oct 2018 23:37:56 +0000 (02:37 +0300)]
Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,
meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.
Clifford Wolf [Tue, 23 Oct 2018 17:18:45 +0000 (19:18 +0200)]
Merge pull request #677 from daveshah1/ecp5_dsp
ecp5: Add blackboxes for MULT18X18D and ALU54B
whentze [Mon, 22 Oct 2018 17:40:22 +0000 (19:40 +0200)]
fix unhandled std::out_of_range when calling yosys with 3-character argument
David Shah [Mon, 22 Oct 2018 15:20:38 +0000 (16:20 +0100)]
ecp5: Remove DSP parameters that don't work
Signed-off-by: David Shah <davey1576@gmail.com>
David Shah [Sun, 21 Oct 2018 18:27:02 +0000 (19:27 +0100)]
ecp5: Add DSP blackboxes
Signed-off-by: David Shah <davey1576@gmail.com>
Clifford Wolf [Sat, 20 Oct 2018 21:48:53 +0000 (23:48 +0200)]
Improve read_verilog range out of bounds warning
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Sat, 20 Oct 2018 21:28:09 +0000 (23:28 +0200)]
Merge pull request #674 from rubund/feature/svinterface_at_top
Support for SystemVerilog interfaces as ports in the top level module + test case
Ruben Undheim [Sat, 20 Oct 2018 10:45:51 +0000 (12:45 +0200)]
Refactor code to avoid code duplication + added comments
Ruben Undheim [Sat, 20 Oct 2018 09:58:25 +0000 (11:58 +0200)]
Support for SystemVerilog interfaces as a port in the top level module + test case
Ruben Undheim [Sat, 20 Oct 2018 09:57:39 +0000 (11:57 +0200)]
Fixed memory leak
Clifford Wolf [Fri, 19 Oct 2018 15:32:42 +0000 (17:32 +0200)]
Merge pull request #673 from daveshah1/ecp5_improve
Small ECP5 improvements
David Shah [Thu, 18 Oct 2018 18:40:02 +0000 (19:40 +0100)]
ecp5: Sim model fixes
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 18 Oct 2018 18:39:48 +0000 (19:39 +0100)]
ecp5: Add latch inference
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 19 Oct 2018 14:09:11 +0000 (16:09 +0200)]
Merge pull request #672 from daveshah1/fix_bram
memory_bram: Reset make_outreg when growing read ports
David Shah [Fri, 19 Oct 2018 13:45:45 +0000 (14:45 +0100)]
memory_bram: Reset make_outreg when growing read ports
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 19 Oct 2018 11:05:51 +0000 (13:05 +0200)]
Merge pull request #671 from rafaeltp/master
adding offset info to memories on verilog output
Clifford Wolf [Fri, 19 Oct 2018 11:03:38 +0000 (13:03 +0200)]
Merge pull request #670 from rubund/feature/basic_svinterface_test
Basic test for checking correct synthesis of SystemVerilog interfaces
rafaeltp [Thu, 18 Oct 2018 23:22:33 +0000 (16:22 -0700)]
adding offset info to memories
rafaeltp [Thu, 18 Oct 2018 23:20:21 +0000 (16:20 -0700)]
adding offset info to memories
Ruben Undheim [Thu, 18 Oct 2018 19:27:04 +0000 (21:27 +0200)]
Basic test for checking correct synthesis of SystemVerilog interfaces
Clifford Wolf [Thu, 18 Oct 2018 10:26:53 +0000 (12:26 +0200)]
Update ABC to git rev
14d985a
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 18 Oct 2018 08:58:47 +0000 (10:58 +0200)]
Merge pull request #659 from rubund/sv_interfaces
Support for SystemVerilog interfaces and modports
Clifford Wolf [Thu, 18 Oct 2018 08:54:03 +0000 (10:54 +0200)]
Merge pull request #657 from mithro/xilinx-vpr
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives when using `-vpr`
Clifford Wolf [Thu, 18 Oct 2018 08:52:07 +0000 (10:52 +0200)]
Merge pull request #664 from tklam/ignore-verilog-protect
Ignore protect endprotect
Clifford Wolf [Wed, 17 Oct 2018 10:23:50 +0000 (12:23 +0200)]
Update ABC to git rev
c5b48bb
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 17 Oct 2018 10:23:36 +0000 (12:23 +0200)]
Minor code cleanups in liberty front-end
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 17 Oct 2018 10:21:17 +0000 (12:21 +0200)]
Merge pull request #660 from tklam/parse-liberty-detect-ff-latch
Handling ff/latch in liberty files
Clifford Wolf [Wed, 17 Oct 2018 10:18:57 +0000 (12:18 +0200)]
Merge pull request #663 from aman-goel/master
Update to .smv backend
Clifford Wolf [Wed, 17 Oct 2018 10:16:23 +0000 (12:16 +0200)]
Merge pull request #658 from daveshah1/ecp5_bram
ECP5 BRAM inference
Clifford Wolf [Wed, 17 Oct 2018 10:15:14 +0000 (12:15 +0200)]
Merge pull request #641 from tklam/master
Fix issue #639
Clifford Wolf [Wed, 17 Oct 2018 10:13:18 +0000 (12:13 +0200)]
Merge pull request #638 from udif/pr_reg_wire_error
Fix issue #630
Clifford Wolf [Tue, 16 Oct 2018 14:51:58 +0000 (16:51 +0200)]
We have 2018 now
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 16 Oct 2018 14:44:58 +0000 (16:44 +0200)]
After release is before release
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Tue, 16 Oct 2018 14:40:10 +0000 (16:40 +0200)]
Merge branch 'yosys-0.8-rc'
Clifford Wolf [Tue, 16 Oct 2018 14:22:16 +0000 (16:22 +0200)]
Yosys 0.8
Signed-off-by: Clifford Wolf <clifford@clifford.at>
argama [Tue, 16 Oct 2018 13:33:37 +0000 (21:33 +0800)]
ignore protect endprotect
Clifford Wolf [Tue, 16 Oct 2018 13:28:37 +0000 (15:28 +0200)]
Update command reference manual
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Tue, 16 Oct 2018 11:48:39 +0000 (12:48 +0100)]
ecp5: Disable LSR inversion
Signed-off-by: David Shah <dave@ds0.me>
Aman Goel [Mon, 15 Oct 2018 17:54:12 +0000 (13:54 -0400)]
Minor update
Ruben Undheim [Sat, 13 Oct 2018 18:48:55 +0000 (20:48 +0200)]
Handle FIXME for modport members without type directly in front
Ruben Undheim [Sat, 13 Oct 2018 18:34:44 +0000 (20:34 +0200)]
Documentation improvements etc.
- Mention new feature in the SystemVerilog section in the README file
- Commented changes much better
- Rename a few signals to make it clearer
- Prevent warning for unused signals in an easier way
- Add myself as copyright holder to 2 files
- Fix one potential memory leak (delete 'wire' if not in modport)
argama [Sat, 13 Oct 2018 17:42:48 +0000 (01:42 +0800)]
detect ff/latch before processing other nodes
tklam [Sat, 13 Oct 2018 15:24:24 +0000 (23:24 +0800)]
stop check_signal_in_fanout from traversing FFs
tklam [Sat, 13 Oct 2018 15:11:19 +0000 (23:11 +0800)]
stop check_signal_in_fanout from traversing FFs
tklam [Sat, 13 Oct 2018 14:52:31 +0000 (22:52 +0800)]
Merge branch 'master' of https://github.com/YosysHQ/yosys
Ruben Undheim [Fri, 12 Oct 2018 20:02:29 +0000 (22:02 +0200)]
Fix build error with clang
Ruben Undheim [Fri, 12 Oct 2018 18:58:37 +0000 (20:58 +0200)]
Support for 'modports' for System Verilog interfaces
Ruben Undheim [Thu, 11 Oct 2018 21:33:31 +0000 (23:33 +0200)]
Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
David Shah [Fri, 12 Oct 2018 13:22:21 +0000 (14:22 +0100)]
BRAM improvements
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 16:18:17 +0000 (17:18 +0100)]
ecp5: Adding BRAM maps for all size options
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 15:35:19 +0000 (16:35 +0100)]
ecp5: First BRAM type maps successfully
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Wed, 10 Oct 2018 15:11:00 +0000 (16:11 +0100)]
ecp5: Script for BRAM IO connections
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Tue, 9 Oct 2018 13:19:04 +0000 (14:19 +0100)]
ecp5: Adding BRAM initialisation and config
Signed-off-by: David Shah <dave@ds0.me>
Tim 'mithro' Ansell [Mon, 8 Oct 2018 23:52:12 +0000 (16:52 -0700)]
xilinx: Still map LUT7/LUT8 to Xilinx specific primitives.
Then if targeting vpr map all the Xilinx specific LUTs back into generic
Yosys LUTs.
Clifford Wolf [Sun, 7 Oct 2018 17:48:42 +0000 (19:48 +0200)]
Improve Verific importer blackbox handling
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Fri, 5 Oct 2018 10:35:59 +0000 (11:35 +0100)]
ecp5: Add blackbox for DP16KD
Signed-off-by: David Shah <dave@ds0.me>
Clifford Wolf [Fri, 5 Oct 2018 07:59:57 +0000 (09:59 +0200)]
Merge pull request #651 from ARandomOWL/stdcells_fix
Fix IdString M in setup_stdcells()
Clifford Wolf [Fri, 5 Oct 2018 07:41:18 +0000 (09:41 +0200)]
Add "write_edif -attrprop"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Fri, 5 Oct 2018 07:29:26 +0000 (09:29 +0200)]
Merge pull request #654 from mithro/patch-1
Fix misspelling in issue_template.md
Clifford Wolf [Fri, 5 Oct 2018 07:26:10 +0000 (09:26 +0200)]
Fix compiler warning in verific.cc
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Tim Ansell [Fri, 5 Oct 2018 00:15:30 +0000 (17:15 -0700)]
Fix misspelling in issue_template.md
It's been bugging me :-P