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whitequark [Thu, 13 Dec 2018 02:04:44 +0000 (02:04 +0000)]
fhdl.ast: add tests for most logic.
whitequark [Thu, 13 Dec 2018 02:04:23 +0000 (02:04 +0000)]
Measure test coverage.
whitequark [Wed, 12 Dec 2018 15:44:54 +0000 (15:44 +0000)]
compat.fhdl.{module,structure}: import/wrap Migen code (WIP).
whitequark [Wed, 12 Dec 2018 14:11:19 +0000 (14:11 +0000)]
compat.fhdl.bitcontainer: import/wrap Migen code.
whitequark [Wed, 12 Dec 2018 14:43:03 +0000 (14:43 +0000)]
fhdl.ast.Signal: implement .like().
whitequark [Wed, 12 Dec 2018 13:00:50 +0000 (13:00 +0000)]
fhdl.ir: fix port threading code.
whitequark [Wed, 12 Dec 2018 12:38:24 +0000 (12:38 +0000)]
fhdl.dsl: comb/sync/sync.pix→d.comb/d.sync/d.pix.
whitequark [Wed, 12 Dec 2018 12:37:30 +0000 (12:37 +0000)]
fhdl.ast.Signal: fix typo.
whitequark [Wed, 12 Dec 2018 11:02:13 +0000 (11:02 +0000)]
fhdl.ast.Signal: implement attrs field.
whitequark [Wed, 12 Dec 2018 10:52:32 +0000 (10:52 +0000)]
genlib.cdc.MultiReg: self.regs should be a private field.
whitequark [Wed, 12 Dec 2018 10:43:09 +0000 (10:43 +0000)]
fhdl.ast.Signal: implement width derivation from min/max.
whitequark [Wed, 12 Dec 2018 10:12:35 +0000 (10:12 +0000)]
genlib.cdc.MultiReg: pull in from Migen.
whitequark [Wed, 12 Dec 2018 10:11:16 +0000 (10:11 +0000)]
fhdl.ast.Signal: implement reset_less signals.
whitequark [Wed, 12 Dec 2018 10:08:56 +0000 (10:08 +0000)]
fhdl.ast.Signal: assign an internal name if tracer fails.
whitequark [Wed, 12 Dec 2018 10:00:00 +0000 (10:00 +0000)]
fhdl.dsl: allow f.sync["dom"] as a synonym of f.sync.dom.
whitequark [Wed, 12 Dec 2018 09:49:02 +0000 (09:49 +0000)]
ClockDomain.{rst→reset}, for consistency with ResetInserter.
nmigen.compat.ClockDomain would alias this, for Migen compatibility.
whitequark [Tue, 11 Dec 2018 20:50:56 +0000 (20:50 +0000)]
Initial commit.
projects / nmigen.git / log