bugzilla-daemon [Wed, 27 May 2020 19:43:34 +0000 (19:43 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 19:25:25 +0000 (19:25 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:56:53 +0000 (18:56 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:48:12 +0000 (18:48 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Luke Kenneth Casson Leighton [Wed, 27 May 2020 18:42:10 +0000 (19:42 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 18:40:38 +0000 (18:40 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 18:38:26 +0000 (18:38 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:33:52 +0000 (18:33 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:24:09 +0000 (18:24 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 18:08:15 +0000 (18:08 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 17:58:34 +0000 (17:58 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Wed, 27 May 2020 17:56:04 +0000 (17:56 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 17:46:10 +0000 (17:46 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 17:42:40 +0000 (17:42 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 17:40:44 +0000 (17:40 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
Tobias Platen [Wed, 27 May 2020 17:29:39 +0000 (19:29 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 17:26:36 +0000 (17:26 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 16:45:13 +0000 (16:45 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Wed, 27 May 2020 16:35:04 +0000 (09:35 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 16:06:19 +0000 (16:06 +0000)]
[libre-riscv-dev] [Bug 305] Create Pipelined ALU similar to alu_hier.py
bugzilla-daemon [Wed, 27 May 2020 14:57:34 +0000 (14:57 +0000)]
[libre-riscv-dev] [Bug 348] POWER9 SPR pipeline needed
bugzilla-daemon [Wed, 27 May 2020 14:49:42 +0000 (14:49 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:48:07 +0000 (14:48 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:21:21 +0000 (14:21 +0000)]
[libre-riscv-dev] [Bug 340] formal proof of POWER9 SHIFTROT pipeline needed
bugzilla-daemon [Wed, 27 May 2020 14:43:44 +0000 (14:43 +0000)]
[libre-riscv-dev] [Bug 325] create POWER9 TRAP pipeline
bugzilla-daemon [Wed, 27 May 2020 14:27:54 +0000 (14:27 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:21:21 +0000 (14:21 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:09:09 +0000 (14:09 +0000)]
[libre-riscv-dev] [Bug 343] compalu_multi write requests need to hook into Data.ok
bugzilla-daemon [Wed, 27 May 2020 14:09:09 +0000 (14:09 +0000)]
[libre-riscv-dev] [Bug 332] Formal correctness proof needed for CR pipeline
bugzilla-daemon [Wed, 27 May 2020 14:06:22 +0000 (14:06 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Wed, 27 May 2020 14:01:40 +0000 (14:01 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
bugzilla-daemon [Wed, 27 May 2020 13:34:21 +0000 (13:34 +0000)]
[libre-riscv-dev] [Bug 306] Formal Correctness Proof for ALU pipeline
Luke Kenneth Casson Leighton [Wed, 27 May 2020 13:12:34 +0000 (14:12 +0100)]
[libre-riscv-dev] POWER9 formal correctness proofs collaboration
Luke Kenneth Casson Leighton [Wed, 27 May 2020 12:25:06 +0000 (13:25 +0100)]
[libre-riscv-dev] daily kan-ban update 27may2020
bugzilla-daemon [Wed, 27 May 2020 11:14:46 +0000 (11:14 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 11:10:54 +0000 (11:10 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Wed, 27 May 2020 04:12:44 +0000 (04:12 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Wed, 27 May 2020 00:46:38 +0000 (00:46 +0000)]
[libre-riscv-dev] [Bug 354] idea/optimisation: make FP CMP also do INT CMP
bugzilla-daemon [Wed, 27 May 2020 00:46:22 +0000 (00:46 +0000)]
[libre-riscv-dev] [Bug 354] New: idea/optimisation: make FP CMP also do INT CMP
bugzilla-daemon [Wed, 27 May 2020 00:41:24 +0000 (00:41 +0000)]
[libre-riscv-dev] [Bug 345] define POWER9 regfiles
bugzilla-daemon [Tue, 26 May 2020 23:20:17 +0000 (23:20 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 23:20:17 +0000 (23:20 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Tue, 26 May 2020 23:17:56 +0000 (23:17 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
Jacob Lifshay [Tue, 26 May 2020 22:24:44 +0000 (15:24 -0700)]
Re: [libre-riscv-dev] funny article about Rust and technical interviews
bugzilla-daemon [Tue, 26 May 2020 22:20:33 +0000 (22:20 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
Cole Poirier [Tue, 26 May 2020 22:03:24 +0000 (15:03 -0700)]
Re: [libre-riscv-dev] funny article about Rust and technical interviews
bugzilla-daemon [Tue, 26 May 2020 21:30:49 +0000 (21:30 +0000)]
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
Luke Kenneth Casson Leighton [Tue, 26 May 2020 21:25:15 +0000 (22:25 +0100)]
Re: [libre-riscv-dev] funny article about Rust and technical interviews
Jacob Lifshay [Tue, 26 May 2020 20:15:43 +0000 (13:15 -0700)]
[libre-riscv-dev] funny article about Rust and technical interviews
bugzilla-daemon [Tue, 26 May 2020 20:12:45 +0000 (20:12 +0000)]
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
Luke Kenneth Casson Leighton [Tue, 26 May 2020 20:00:19 +0000 (21:00 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Tobias Platen [Tue, 26 May 2020 19:54:26 +0000 (21:54 +0200)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Luke Kenneth Casson Leighton [Tue, 26 May 2020 19:51:40 +0000 (20:51 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Luke Kenneth Casson Leighton [Tue, 26 May 2020 19:46:44 +0000 (20:46 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Jacob Lifshay [Tue, 26 May 2020 19:13:38 +0000 (12:13 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Cole Poirier [Tue, 26 May 2020 18:00:19 +0000 (11:00 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Michael Nolan [Tue, 26 May 2020 17:57:29 +0000 (13:57 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
bugzilla-daemon [Tue, 26 May 2020 17:52:49 +0000 (17:52 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
Luke Kenneth Casson Leighton [Tue, 26 May 2020 17:49:25 +0000 (18:49 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
bugzilla-daemon [Tue, 26 May 2020 17:35:49 +0000 (17:35 +0000)]
[libre-riscv-dev] [Bug 342] formal proof of soc.fu.compunits.FunctionUnitBaseSingle needed
Luke Kenneth Casson Leighton [Tue, 26 May 2020 17:35:02 +0000 (18:35 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Cole Poirier [Tue, 26 May 2020 17:29:50 +0000 (10:29 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Luke Kenneth Casson Leighton [Tue, 26 May 2020 17:24:05 +0000 (18:24 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
bugzilla-daemon [Tue, 26 May 2020 17:22:35 +0000 (17:22 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Tue, 26 May 2020 17:08:39 +0000 (18:08 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Luke Kenneth Casson Leighton [Tue, 26 May 2020 17:07:14 +0000 (18:07 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Cole Poirier [Tue, 26 May 2020 17:02:23 +0000 (10:02 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Michael Nolan [Tue, 26 May 2020 16:47:04 +0000 (12:47 -0400)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
Cesar Strauss [Tue, 26 May 2020 16:44:34 +0000 (13:44 -0300)]
Re: [libre-riscv-dev] daily kan-ban update 26may2020
bugzilla-daemon [Tue, 26 May 2020 16:41:00 +0000 (16:41 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 16:29:34 +0000 (16:29 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Tue, 26 May 2020 16:01:01 +0000 (16:01 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
Luke Kenneth Casson Leighton [Tue, 26 May 2020 14:40:00 +0000 (15:40 +0100)]
[libre-riscv-dev] daily kan-ban update 26may2020
bugzilla-daemon [Tue, 26 May 2020 12:54:41 +0000 (12:54 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 12:50:12 +0000 (12:50 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Tue, 26 May 2020 10:24:38 +0000 (10:24 +0000)]
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
bugzilla-daemon [Tue, 26 May 2020 10:15:16 +0000 (10:15 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Tue, 26 May 2020 10:01:25 +0000 (10:01 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Tue, 26 May 2020 09:00:27 +0000 (09:00 +0000)]
[libre-riscv-dev] [Bug 155] a PLL is needed for the SoC
Paul Mackerras [Tue, 26 May 2020 05:44:30 +0000 (15:44 +1000)]
Re: [libre-riscv-dev] [OpenPOWER-HDL-Cores] Power ISA v3.1 bug - parityw
bugzilla-daemon [Tue, 26 May 2020 04:07:09 +0000 (04:07 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 03:55:20 +0000 (03:55 +0000)]
[libre-riscv-dev] [Bug 324] create POWER9 DIV pipeline
bugzilla-daemon [Tue, 26 May 2020 02:09:17 +0000 (02:09 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 02:08:46 +0000 (02:08 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 02:03:56 +0000 (02:03 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 01:45:41 +0000 (01:45 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 01:34:13 +0000 (01:34 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 01:18:36 +0000 (01:18 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Tue, 26 May 2020 00:13:19 +0000 (00:13 +0000)]
[libre-riscv-dev] [Bug 353] formal proof of soc.regfile classes RegFile and RegFileArray needed
bugzilla-daemon [Tue, 26 May 2020 00:13:10 +0000 (00:13 +0000)]
[libre-riscv-dev] [Bug 353] New: formal proof of soc.regfile classes RegFile and RegFileArray needed
Cole Poirier [Tue, 26 May 2020 00:11:25 +0000 (17:11 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 23:55:07 +0000 (23:55 +0000)]
[libre-riscv-dev] [Bug 351] create a "block" (mass) regfile port (read and write) onto an array-based regfile
bugzilla-daemon [Mon, 25 May 2020 23:41:36 +0000 (23:41 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
Luke Kenneth Casson Leighton [Mon, 25 May 2020 23:40:10 +0000 (00:40 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cole Poirier [Mon, 25 May 2020 23:22:35 +0000 (16:22 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 23:06:24 +0000 (23:06 +0000)]
[libre-riscv-dev] [Bug 336] ALU CompUnit needs to recognise that RA (src1) can be zero
bugzilla-daemon [Mon, 25 May 2020 22:53:02 +0000 (22:53 +0000)]
[libre-riscv-dev] [Bug 337] Convention for register outputs in *OutputData structures is to use "Data"
Luke Kenneth Casson Leighton [Mon, 25 May 2020 22:45:39 +0000 (23:45 +0100)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
Cole Poirier [Mon, 25 May 2020 22:11:16 +0000 (15:11 -0700)]
Re: [libre-riscv-dev] daily kan-ban update 25may2020
bugzilla-daemon [Mon, 25 May 2020 21:36:58 +0000 (21:36 +0000)]
[libre-riscv-dev] [Bug 316] bperm TODO
projects / libre-riscv-dev.git / log