Ian Romanick [Mon, 12 Dec 2016 19:19:20 +0000 (11:19 -0800)]
glsl: Silence unused parameter warning in propagate_invariance.cpp
glsl/propagate_invariance.cpp: In member function ‘virtual ir_visitor_status {anonymous}::ir_invariance_propagation_visitor::visit_leave(ir_assignment*)’:
glsl/propagate_invariance.cpp:86:63: warning: unused parameter ‘ir’ [-Wunused-parameter]
ir_invariance_propagation_visitor::visit_leave(ir_assignment *ir)
^~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 12 Dec 2016 18:56:05 +0000 (10:56 -0800)]
glsl: Minor formatting fixes in link_uniform_blocks.cpp
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 9 Dec 2016 23:38:24 +0000 (15:38 -0800)]
glsl: Fix all the whitespace errors in link_uniform_block_active_visitor.cpp
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 9 Dec 2016 21:44:09 +0000 (13:44 -0800)]
mesa: Silence numerous "unused parameter" warnings in dlist.c
main/dlist.c: In function ‘save_DrawArraysInstancedARB’:
main/dlist.c:1748:36: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawArraysInstancedARB(GLenum mode,
^~~~
main/dlist.c:1749:35: warning: unused parameter ‘first’ [-Wunused-parameter]
GLint first,
^~~~~
main/dlist.c:1750:37: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1751:37: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount)
^~~~~~~~~
main/dlist.c: In function ‘save_DrawElementsInstancedARB’:
main/dlist.c:1759:38: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawElementsInstancedARB(GLenum mode,
^~~~
main/dlist.c:1760:39: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1761:38: warning: unused parameter ‘type’ [-Wunused-parameter]
GLenum type,
^~~~
main/dlist.c:1762:45: warning: unused parameter ‘indices’ [-Wunused-parameter]
const GLvoid *indices,
^~~~~~~
main/dlist.c:1763:39: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount)
^~~~~~~~~
main/dlist.c: In function ‘save_DrawElementsInstancedBaseVertexARB’:
main/dlist.c:1771:48: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawElementsInstancedBaseVertexARB(GLenum mode,
^~~~
main/dlist.c:1772:49: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1773:48: warning: unused parameter ‘type’ [-Wunused-parameter]
GLenum type,
^~~~
main/dlist.c:1774:55: warning: unused parameter ‘indices’ [-Wunused-parameter]
const GLvoid *indices,
^~~~~~~
main/dlist.c:1775:49: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount,
^~~~~~~~~
main/dlist.c:1776:47: warning: unused parameter ‘basevertex’ [-Wunused-parameter]
GLint basevertex)
^~~~~~~~~~
main/dlist.c: In function ‘save_DrawArraysInstancedBaseInstance’:
main/dlist.c:1785:45: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawArraysInstancedBaseInstance(GLenum mode,
^~~~
main/dlist.c:1786:44: warning: unused parameter ‘first’ [-Wunused-parameter]
GLint first,
^~~~~
main/dlist.c:1787:46: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1788:46: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount,
^~~~~~~~~
main/dlist.c:1789:45: warning: unused parameter ‘baseinstance’ [-Wunused-parameter]
GLuint baseinstance)
^~~~~~~~~~~~
main/dlist.c: In function ‘save_DrawElementsInstancedBaseInstance’:
main/dlist.c:1797:47: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawElementsInstancedBaseInstance(GLenum mode,
^~~~
main/dlist.c:1798:48: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1799:47: warning: unused parameter ‘type’ [-Wunused-parameter]
GLenum type,
^~~~
main/dlist.c:1800:52: warning: unused parameter ‘indices’ [-Wunused-parameter]
const void *indices,
^~~~~~~
main/dlist.c:1801:48: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount,
^~~~~~~~~
main/dlist.c:1802:47: warning: unused parameter ‘baseinstance’ [-Wunused-parameter]
GLuint baseinstance)
^~~~~~~~~~~~
main/dlist.c: In function ‘save_DrawElementsInstancedBaseVertexBaseInstance’:
main/dlist.c:1810:57: warning: unused parameter ‘mode’ [-Wunused-parameter]
save_DrawElementsInstancedBaseVertexBaseInstance(GLenum mode,
^~~~
main/dlist.c:1811:58: warning: unused parameter ‘count’ [-Wunused-parameter]
GLsizei count,
^~~~~
main/dlist.c:1812:57: warning: unused parameter ‘type’ [-Wunused-parameter]
GLenum type,
^~~~
main/dlist.c:1813:62: warning: unused parameter ‘indices’ [-Wunused-parameter]
const void *indices,
^~~~~~~
main/dlist.c:1814:58: warning: unused parameter ‘primcount’ [-Wunused-parameter]
GLsizei primcount,
^~~~~~~~~
main/dlist.c:1815:56: warning: unused parameter ‘basevertex’ [-Wunused-parameter]
GLint basevertex,
^~~~~~~~~~
main/dlist.c:1816:57: warning: unused parameter ‘baseinstance’ [-Wunused-parameter]
GLuint baseinstance)
^~~~~~~~~~~~
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Fri, 9 Dec 2016 21:38:44 +0000 (13:38 -0800)]
mesa: Fix all the whitespace errors in dlist.c
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 14 Dec 2016 04:33:08 +0000 (20:33 -0800)]
linker: Accurately mark a uniform block instance array element as used in a stage
Now that information about which array-of-arrays elements are accessed
is tracked, use that information to only mark an instance array element
as used-by-stage if, in fact, it is.
Fixes GL45-CTS.program_interface_query.uniform-block-types.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Thu, 15 Dec 2016 22:26:24 +0000 (14:26 -0800)]
glsl: Walk a list of ir_dereference_array to mark array elements as accessed
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Thu, 15 Dec 2016 22:01:28 +0000 (14:01 -0800)]
glsl: Mark a set of array elements as accessed using a list of array_deref_range
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 14 Dec 2016 04:31:19 +0000 (20:31 -0800)]
glsl: Add structures to track accessed elements of a single array
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Wed, 14 Dec 2016 04:29:23 +0000 (20:29 -0800)]
glsl: Add tracking for elements of an array-of-arrays that have been accessed
If there's a better way to provide access to ir_array_refcount_entry
private members to the test functions, I am very interested to know
about it.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: Francisco Jerez <currojerez@riseup.net>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 12 Dec 2016 21:37:46 +0000 (13:37 -0800)]
glsl: Use simpler visitor to determine which UBO and SSBO blocks are used
Very soon this visitor will get more complicated. The users of the
existing ir_variable_refcount visitor won't need the coming
functionality, and this use doesn't need much of the functionality of
ir_variable_refcount.
v2: ir_array_refcount_visitor::get_variable_entry cannot return NULL, so
don't check it. Suggested by Timothy.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 12 Dec 2016 20:24:18 +0000 (12:24 -0800)]
glsl: Track the linearized array index for each UBO instance array element
v2: Set linearizer_array_index in process_block_array_leaf. Suggested
by Timothy.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 12 Dec 2016 19:58:06 +0000 (11:58 -0800)]
glsl: Fix wonkey indentation left from previous commit
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Ian Romanick [Mon, 12 Dec 2016 19:54:41 +0000 (11:54 -0800)]
glsl: Split process_block_array into two functions
One for the array parts and one for the leaf members. This will
simplify later changes.
The indentation is wonkey after this patch. This was done to make it
more obvious that the function is just getting split. The next patch
will fix the indentation.
Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Sat, 17 Dec 2016 01:03:15 +0000 (17:03 -0800)]
glsl: Fix program interface queries relating to interface blocks.
This fixes 555 dEQP tests (using the nougat-cts-dev branch), Piglit's
arb_program_interface_query/arb_program_interface_query-resource-query,
and GL45-CTS.program_interface_query.separate-programs-{tess-control,
tess-eval,geometry}. Only one dEQP program interface failure remains.
I would have liked to split this up into several distinct changes, but
I wasn't sure how to do that given thet tangled nature of these issues.
So, the issues:
* We need to treat interface blocks declared as an array of instances
as a single block - removing the outer array. The resource list
entry's name should not include the array length. Properties such
as GL_ARRAY_SIZE should refer to the variable inside the block, not
the interface block's array properties.
* We need to do this prefixing even for structure variables.
* We need to do this for built-ins (such as gl_PerVertex.gl_Position).
* After interface array unwrapping, any variable which is an array
should have [0] appended. It doesn't matter if it's a TCS/TES/GS
input or TCS output - that looked like an attempt to unwrap for
per-vertex variables, but that didn't consider per-patch variables,
and as far as I can tell there's nothing to justify this.
Several Mesa developers have suggested that Issue 16 contradicts the
main specification, but I believe that it doesn't - the main spec just
isn't terribly clear. The main ARB_program_interface query spec says:
"* For an active interface block not declared as an array of block
instances, a single entry will be generated, using the block name from
the shader source.
* For an active interface block declared as an array of instances,
separate entries will be generated for each active instance. The name
of the instance is formed by concatenating the block name, the "["
character, an integer identifying the instance number, and the "]"
character."
Issue 16 says that built-ins should be named "gl_PerVertex.gl_Position",
but several people suggested the second bullet above means that it
should be named "gl_PerVertex[array length].gl_Position".
There are two important things to note. Those bullet points say
"an active interface block", while the others say "variable" or "active
shader storage block member". They also don't mention applying the
rules recursively (unlike the other bullets). Both suggest that
these rules apply to blocks themselves, not members of blocks.
In fact, for GL_UNIFORM_BLOCK queries, we do have "block[0]",
"block[1]", ... resource list entries - so those rules are real,
and actually used. So if they don't apply to block members, then how
should members be named? Unfortunately, I don't see any rules outside
of issue 16 - where the rationale is very unclear. I hope to clarify
the spec in the future.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Kenneth Graunke [Fri, 16 Dec 2016 12:54:59 +0000 (04:54 -0800)]
glsl: Drop bogus is_vertex_input from add_shader_variable().
stage_mask is a bitmask of shader stages, so the proper comparison would
be (1 << MESA_SHADER_VERTEX), not MESA_SHADER_VERTEX itself.
But we only care for structure types, and VS inputs cannot be structs.
So we can just drop this entirely.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Kenneth Graunke [Sun, 18 Dec 2016 04:04:32 +0000 (20:04 -0800)]
mesa/get: Convert stencil values to TYPE_UINT.
These are listed as Z+ in the GL spec, and often have values of
0xFFFFFFFF. For glGetFloat, we should return
4294967295.0 rather than
-1.0. Similarly, for glGetInteger64v, we should return 0xFFFFFFFF, not
the sign extended 0xFFFFFFFFFFFFFFFF.
Fixes 6 dEQP tests matching the pattern
dEQP-GLES3.functional.state_query.integers.stencil*value*mask*getfloat
when run in a single process (with state reset code happening between
tests, which makes dEQP set the stencil value mask to 0xFFFFFFFF).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Sun, 18 Dec 2016 03:55:53 +0000 (19:55 -0800)]
mesa/get: Add TYPE_UINT for casting through a GLuint.
The "State Tables" section of the OpenGL specification lists many values
as belonging to Z+ (non-negative integers), not Z (all integers).
For ordinary glGetInteger queries, this doesn't matter. However, when
accessing Z+ values via glGetFloat or glGetInteger64, we need to treat
the source value as an unsigned value. Otherwise, we'll produce a
negative number when bit 31 is set.
This commit merely adds the plumbing. It doesn't convert any values.
v2: Gotta catch 'em all (add missing cases caught by Ilia)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Kenneth Graunke [Sun, 18 Dec 2016 03:47:38 +0000 (19:47 -0800)]
mesa/get: Make GetFloat/GetDouble of TYPE_INT_N not normalize things.
GetFloat of integer valued things is supposed to perform a simple
int -> float conversion. INT_TO_FLOAT is not that. Instead, it
converts [-
2147483648,
2147483647] to a normalized [-1.0, 1.0] float.
This is only used for COMPRESSED_TEXTURE_FORMATS, which nobody in
their right mind would try and access via glGetFloat(), but we may
as well fix it.
Found by inspection.
v2: Gotta catch 'em all (fix another case of this caught by Ilia)
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Michel Dänzer [Fri, 16 Dec 2016 03:11:30 +0000 (12:11 +0900)]
Revert "cso: don't release sampler states that are bound"
This reverts commit
6dc96de303290e8d1fc294da478c4f370be98dea. No longer
necessary with the previous change.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Fri, 16 Dec 2016 02:17:44 +0000 (11:17 +0900)]
cso: Make sanitize_hash safe for samplers
Remove currently bound sampler states from the hash table before pruning
entries from the hash table, so they cannot accidentally be deleted by
the pruning.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Fri, 16 Dec 2016 02:41:54 +0000 (11:41 +0900)]
cso: Store hash key in struct cso_sampler
Preparation for following changes, no functional change intended.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Fri, 16 Dec 2016 09:00:33 +0000 (18:00 +0900)]
cso: Optimize cso_save/restore_fragment_samplers
Only copy/memset the pointers that actually need to be.
v2:
* Cast info->nr_samplers to int for calculating delta (Nicolai)
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Fri, 16 Dec 2016 02:13:26 +0000 (11:13 +0900)]
cso: Store pointers to struct cso_sampler in struct sampler_info
Preparation for following changes, no functional change intended.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Michel Dänzer [Fri, 16 Dec 2016 09:05:58 +0000 (18:05 +0900)]
cso: Don't restore nr_samplers in cso_restore_fragment_samplers
If info->nr_samplers > ctx->nr_fragment_samplers_saved, the assignment
would prevent cso_single_sampler_done from unbinding the no longer used
samplers from the driver, which could result in use-after-free. This is
probably unlikely to happen in practice though.
Cc: "12.0 13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Liu Zhiquan [Fri, 9 Dec 2016 11:29:56 +0000 (19:29 +0800)]
EGL/android: Enhance pbuffer implementation
Some dri drivers will pass multiple bits in buffer_mask parameter
to droid_image_get_buffer(), more than the actual supported buffer
type combination. For such case, will go through all the bits, and
will not return error when unsupported buffer is requested, only
return error when the allocation for supported buffer failed.
v2: coding style and log changes
v3: coding style changes and update patch format
Signed-off-by: Liu Zhiquan <zhiquan.liu@intel.com>
Signed-off-by: Long, Zhifang <zhifang.long@intel.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
Bas Nieuwenhuizen [Sun, 18 Dec 2016 20:09:28 +0000 (21:09 +0100)]
radv: Use correct workgroup size limits.
Not sure where the 16k comes from, but pretty sure 2k is the max.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 04:08:10 +0000 (04:08 +0000)]
radv: expose the compute queue
v2: Don't expose the SDMA queue and use the CIK check also in the
second if. (Bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Sun, 18 Dec 2016 13:05:19 +0000 (14:05 +0100)]
radv: Only emit PFP ME syncs for DMA on the GFX queue.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 17 Dec 2016 20:53:38 +0000 (21:53 +0100)]
radv: Create an empty CS per ring type.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 17 Dec 2016 20:25:32 +0000 (21:25 +0100)]
radv: Don't enable CMASK on compute queues.
We can't fast clear on compute queues.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Sat, 17 Dec 2016 12:27:37 +0000 (13:27 +0100)]
radv: Use RELEASE_MEM packet for MEC timestamp query.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 12 Dec 2016 07:45:21 +0000 (08:45 +0100)]
radv: Implement indirect dispatch for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 12 Dec 2016 07:42:44 +0000 (08:42 +0100)]
radv: update vkCmdUpdateBuffer for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Bas Nieuwenhuizen [Mon, 12 Dec 2016 07:38:00 +0000 (08:38 +0100)]
radv: Implement cache flushing for the MEC.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 1 Dec 2016 01:52:31 +0000 (01:52 +0000)]
radv: add semaphore support
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 1 Dec 2016 01:14:49 +0000 (01:14 +0000)]
radv: pass queue index into winsys submission
This is so we can submit on separate queues if needed
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 1 Dec 2016 00:15:23 +0000 (00:15 +0000)]
radv: init compute queue and avoid initing transfer queues
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Sat, 17 Dec 2016 18:10:35 +0000 (19:10 +0100)]
radv/winsys: Make WaitIdle queue aware.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Wed, 30 Nov 2016 03:10:28 +0000 (03:10 +0000)]
radv/meta: update header info
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 30 Nov 2016 03:09:01 +0000 (03:09 +0000)]
radv: hook compute clears into clear image api.
These aren't used yet but we will want to use them when we
implement a separate compute queue.
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 30 Nov 2016 01:45:24 +0000 (01:45 +0000)]
radv: clear image implementation for compute queue
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 30 Nov 2016 02:56:59 +0000 (02:56 +0000)]
radv/meta: split clear image out into a separate layer clear function
This will make it easier to add support for clears on compute queues.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 30 Nov 2016 00:26:47 +0000 (00:26 +0000)]
radv: implement image->image copies using compute shader
This is required for having a separate compute queue, we
probably can't use this on GFX queue due to DCC.
v2: Set coord_components = 2 for itoi texture fetch. (Bas)
Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Tue, 29 Nov 2016 23:52:55 +0000 (23:52 +0000)]
radv: add a compute shader implementation for buffer to image
This implements the reverse of the current buffer->image path
and can be used when we need to do image transfer on compute queues
This just adds the code turned off as we don't support separate
computes queues yet, and we don't want to use this path on the GFX
queues for DCC reasons.
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Sun, 18 Dec 2016 12:28:04 +0000 (13:28 +0100)]
radv: Use correct pitch for views with different block size.
Needed when accessing a comrpessed texture as R32G32B32A32 from a shader. This
was not encountered previously, as we used the CB for the reinterpretation, which
does not use this pitch.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Dave Airlie [Thu, 1 Dec 2016 00:05:29 +0000 (00:05 +0000)]
radv: Store queue family in command buffers.
v2: Added helper (Bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Wed, 30 Nov 2016 04:30:06 +0000 (04:30 +0000)]
radv: start fixing up queue allocate for multiple queues
v2: Fix error handling and zero init the device (Bas)
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Fri, 25 Nov 2016 00:15:43 +0000 (00:15 +0000)]
radv/winsys: start adding support for DMA/compute queue
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Sat, 17 Dec 2016 18:20:08 +0000 (19:20 +0100)]
radv/winsys: Expose number of compute/dma rings.
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Rob Clark [Thu, 15 Dec 2016 22:27:56 +0000 (17:27 -0500)]
freedreno/a5xx: border color support
Not 100% sure it works if you have border color in VS.. but it might be
right.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 12 Dec 2016 21:06:55 +0000 (16:06 -0500)]
freedreno/a5xx: use MRT0 to import linear zs
A bit of a hack, but we need to do this until we can do tiled zs in
sysmem (and associated tile/until blits for transfer_map).
Fixes xonotic and glmark2 "refract", when reorder wasn't enabled.
(reorder would paper over the issue by avoiding the extra round-
trip to system memory and back to gmem.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Mon, 12 Dec 2016 21:59:09 +0000 (16:59 -0500)]
freedreno: fdN_gmem_restore_format() is not gen specific
Refactor out into a common helper, since this is the same across
generations when we need equiv z/s gmem restore format.
Next patch needs this in a5xx, rather than creating yet another
helper push this into core.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 9 Dec 2016 23:23:10 +0000 (18:23 -0500)]
freedreno/a5xx: cargo-cult end-batch sequence more faithfully
Fixes some issues at least with GMEM bypass mode, where we'd sometimes
end up with some FS quads not hitting memory.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 9 Dec 2016 18:12:51 +0000 (13:12 -0500)]
freedreno/a5xx: misc fix
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Fri, 9 Dec 2016 18:10:03 +0000 (13:10 -0500)]
freedreno/a5xx: fix (at least some) vtx formats
Swap/component-order doesn't seem to be quite what that is. At least
blob was always setting it to XYZW ('11') but we weren't. Causing
problems w/ formats like sint16.. Hard-coding this instead at least
seems to get glamor working.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Thu, 8 Dec 2016 19:39:58 +0000 (14:39 -0500)]
freedreno/a5xx: more formats
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 22:15:43 +0000 (17:15 -0500)]
freedreno/a5xx: fixup caps
Might not be 100% accurate, mostly just copy from a4xx to get started.
We are defn lying about occlusion query at this point (not implemented
yet) but need it to expose anything higher than gl1.4 (glamor needs
gl2.1)
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 20:21:56 +0000 (15:21 -0500)]
freedreno/a5xx: fix random faults on first sysmem draw
Not sure what this event is, but blob writes it.. and it seems to solve
random write faults at mystery address that would sometimes happen on
first BYPASS draw.
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 20:20:48 +0000 (15:20 -0500)]
freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
Rob Clark [Wed, 7 Dec 2016 15:17:17 +0000 (10:17 -0500)]
freedreno/a5xx: fix stride/size for mem->gmem blits
<brownpaperbag>these should be the in-GMEM dimensions</brownpaperbag>
Signed-off-by: Rob Clark <robdclark@gmail.com>
Dave Airlie [Wed, 30 Nov 2016 03:29:05 +0000 (03:29 +0000)]
radv/winsys: consolidate request->fence code
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Dave Airlie [Thu, 1 Dec 2016 00:44:45 +0000 (00:44 +0000)]
radv: handle fence allocation failing
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Bas Nieuwenhuizen [Fri, 16 Dec 2016 22:10:31 +0000 (23:10 +0100)]
radv: Don't bail out on pipeline create failure.
The spec says we have to try to create all, and only set failed
pipelines to VK_NULL_HANDLE. If one of them fails, we have to return
an error, but as far as I can see, the spec does not care which of
the suberrors.
Fixes
dEQP-VK.api.object_management.alloc_callback_fail_multiple.compute_pipeline
dEQP-VK.api.object_management.alloc_callback_fail_multiple.graphics_pipeline
Signed-off-by: Bas Nieuwenhuizen <basni@google.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Ilia Mirkin [Sun, 27 Nov 2016 21:09:55 +0000 (16:09 -0500)]
spirv/nir: add support for ImageGatherExtended
The strategy is to do the same thing that the GLSL lower_offset_arrays
pass does - create 4 separate texture gather ops, one per offset, and
read in the results from each gather's w component to recreate the
desired result.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Francisco Jerez [Thu, 15 Dec 2016 21:34:02 +0000 (13:34 -0800)]
anv: Fix uniform and storage buffer offset alignment limits.
This fixes a regression in a bunch of image store vulkan CTS tests
from commit
ad38ba113491869ab0dffed937f7b3dd50e8a735, which started
using OWORD block read messages to implement UBO loads. The reason
for the failure is that we were giving bogus buffer alignment limits
to the application (1B), so the CTS would happily come back with
descriptor sets pointing at not even word-aligned uniform buffer
addresses.
Surprisingly the sampler messages used to fetch pull constants before
that commit were able to cope with the non-texel aligned addresses,
but the dataport messages used to fetch pull constants after that
commit and the ones used to access storage buffers (before and after
the same commit) aren't as permissive with unaligned addresses.
Cc: <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99097
Reported-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Thomas Helland [Thu, 15 Dec 2016 22:36:54 +0000 (23:36 +0100)]
nir: Remove nir_array from lower_locals_to_regs
We do nothing but initialize it, add to it, and delete it.
This is a fallout from removing constant initializer support.
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Bruce Cherniak [Tue, 13 Dec 2016 01:24:59 +0000 (19:24 -0600)]
swr: Implement fence attached work queues for deferred deletion.
Work can now be added to fences and triggered by fence completion. This
allows for deferred resource deletion, and other asynchronous tasks.
Reviewed-by: George Kyriazis <george.kyriazis@intel.com>
Timothy Arceri [Thu, 15 Dec 2016 23:17:33 +0000 (10:17 +1100)]
nir: Turn imov/fmov of undef into undef
Reverting the previous attempt at this
a5502a721fd30fd resulted in
the following Vulkan test failing.
dEQP-VK.glsl.return.return_in_dynamic_loop_dynamic_vertex
This time we use the num_components from the alu dest rather than
num_inputs to the op to determine the size of the undef.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99100
Eric Engestrom [Thu, 8 Dec 2016 00:30:34 +0000 (00:30 +0000)]
egl/x11: cleanup init code
No functional change, just rewriting it in an easier-to-understand way.
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Iago Toral Quiroga [Wed, 14 Dec 2016 09:05:44 +0000 (10:05 +0100)]
nir/lower_tex: fix number of components in replace_gradient_with_lod()
We should make the dest in the textureLod() operation have the same number
of components as the destination in the original textureGrad()
Fixes regression in ES3-CTS.gtf.GL3Tests.shadow
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=99072
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Timothy Arceri [Thu, 15 Dec 2016 05:51:13 +0000 (16:51 +1100)]
Revert "nir: Turn imov/fmov of undef into undef."
This reverts commit
6aa730000fea84a14b49828a4bb30761d43903bf.
This was changing the size of the undef to always be 1 (the number of inputs
to imov and fmov) which is wrong, we could be moving a vec4 for example.
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Kenneth Graunke [Wed, 14 Dec 2016 07:47:05 +0000 (23:47 -0800)]
i965/vec4: Fix TCS output reads with non-zero component qualifiers.
We want to perform the URB read to a vec4 temporary, with no writemask,
then issue a MOV to swizzle the data and store it to the actual
destination, using the final writemask.
We were doing this wrong. For example, let's say we wanted to read
a vec2 stored in components 2-3 of a vec4. We would generate a URB
read message of:
SEND <actual destination>.XY <header with mask set to XY>
MOV <actual destination>.XY <actual destination>.ZW
This doesn't work, because the URB message reads the .XY components
of the vec4, rather than the ZW. It writes to the right place, but
with the wrong data. Then the MOV comes along and overwrites it
with data that didn't even come from the URB at all.
Instead we want to do:
SEND <temporary> <header with mask set to ZW>
MOV <actual destination>.XY <temporary>.ZW
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Francisco Jerez [Fri, 9 Dec 2016 06:14:59 +0000 (22:14 -0800)]
i965/disasm: Decode dataport constant cache control fields.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 22 Apr 2015 18:37:46 +0000 (21:37 +0300)]
i965/fs: Remove the FS_OPCODE_SET_SIMD4X2_OFFSET virtual opcode.
Not used anymore. It was just a scalar MOV.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:08:33 +0000 (19:08 -0800)]
i965/fs: Drop useless access mode override from pull constant generator code.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:18:00 +0000 (19:18 -0800)]
i965/fs: Fetch one cacheline of pull constants at a time.
Asking the DC for less than one cacheline (4 owords) of data for
uniform pull constants is suboptimal because the DC cannot request
less than that from L3, resulting in wasted bandwidth and unnecessary
message dispatch overhead, and exacerbating the IVB L3 serialization
bug. The following table summarizes the overall framerate improvement
(with statistical significance of 5% and sample size ~10) from the
whole series up to this patch for several benchmarks and hardware
generations:
| SKL | BDW | HSW
SynMark2 OglShMapPcf | 24.63% ±0.45% | 4.01% ±0.70% | 10.31% ±0.38%
GfxBench4 gl_manhattan31 | 5.93% ±0.35% | 3.92% ±0.31% | 6.62% ±0.22%
GfxBench4 gl_4 | 2.52% ±0.44% | 1.23% ±0.10% | N/A
Unigine Valley | 0.83% ±0.17% | 0.23% ±0.05% | 0.74% ±0.45%
Note that there are two versions of the Manhattan demo shipped with
GfxBench4, one of them is the original gl_manhattan demo which doesn't
use UBOs, so this patch will have no effect on it, and another one is
the gl_manhattan31 demo based on GL 4.3/GLES 3.1, which this patch
benefits as shown above.
I haven't observed any statistically significant regressions in the
benchmarks I have at hand. Note that the comparatively huge
improvement on SKL in the OglShMapPcf test case is due to the combined
effect of this patch and the register pressure benefit on SKL+ of
"i965/fs: Switch to the constant cache for uniform pull constants.",
part of the same series.
Going up to 8 oword blocks would improve performance of pull constants
even more, but at the cost of some additional bandwidth and register
pressure, so it would have to be done on-demand based on the number of
constants actually used by the shader.
v2: Fix for Gen4 and 5.
v3: Non-trivial rebase. Rework to allow the visitor specifiy
arbitrary pull constant block sizes.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 04:05:18 +0000 (20:05 -0800)]
i965/fs: Expose arbitrary pull constant load sizes to the IR.
Change the FS generator to ask the dataport for enough owords worth of
constants to fill the execution size of the instruction -- Which means
that the visitor now needs to set the execution size correctly for
uniform pull constant load instructions, which we were kind of
neglecting until now.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 03:58:25 +0000 (19:58 -0800)]
i965: Factor out oword block read and write message control calculation.
We'll need roughly the same logic in other places and it would be
annoying to duplicate it. Instead factor it out into a function-like
macro that takes the number of dwords per block (which will prove more
convenient than taking the same value in owords or some other unit).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Wed, 26 Oct 2016 21:25:06 +0000 (14:25 -0700)]
i965/fs: Switch to the constant cache for uniform pull constants.
This reverts to using the oword block read messages for uniform pull
constant loads, as used to be the case until
4c1fdae0a01b3f92ec03b61aac1d3df5. There are two important differences
though: Now the L3 cacheability bits are set up correctly for UBOs
(since
11f5d8a5d4fbb861ec161f68593e429cbd65d1cd), and we target the
constant cache instead of the data cache. The latter used to get no
L3 way allocation on boot on all platforms that existed at the time,
so oword read messages wouldn't get cached on L3 regardless of the
MOCS bits, what probably explains the apparent slowness of oword
fetches.
Constant cache loads seem to perform better than SIMD4x2 sampler loads
in a number of cases, they alleviate some of the cache thrashing
caused by the competition with textures for the L1/L2 sampler caches,
and they allow fetching up to 128B worth of constants with a single
oword fetch message.
Note that IVB devices suffer from a hardware bug that leads to
serialization of L3 read requests overlapping the same cacheline as
result of a (on IVB buggy) mechanism of the L3 to preserve coherency.
Since read requests for matching cachelines from any L3 client are not
pipelined, throughput may decrease in cases where there are no
non-overlapping requests left in the queue that can be processed
between them.
This situation should be relatively uncommon as long as we make sure
that we don't use the 1/2 oword messages in cases where the shader
intends to read from any other location of the same cacheline at some
other point. This is generally a good idea anyway on all generations
because using the 1 and 2 oword messages is expected to waste
bandwidth since the minimum L3 request size for the DC is exactly 4
owords (i.e. one cacheline). A future commit will have this effect.
I haven't been able to find any real-world example where this would
still result in a regression on IVB, but if someone happens to find
one it shouldn't be too difficult to add an IVB-specific check to have
it fall back to the sampler cache for pull constant loads.
Note that on SKL+ this change has the additional benefit of reducing
the register footprint of pull constant loads. The following table
summarizes the effect of the whole series on several shader-db stats:
Total instructions Total cycles
BWR:
4571248 ->
4568342 (-0.06%)
123375740 ->
123373296 (-0.00%)
ELK:
3989020 ->
3985402 (-0.09%)
98757068 ->
98754058 (-0.00%)
ILK:
6383591 ->
6376787 (-0.11%)
143649910 ->
143648914 (-0.00%)
SNB:
7528395 ->
7501446 (-0.36%)
103503796 ->
102460370 (-1.01%)
IVB:
6949221 ->
6943317 (-0.08%)
60592262 ->
60584422 (-0.01%)
HSW:
6409753 ->
6403702 (-0.09%)
60609070 ->
60604414 (-0.01%)
BDW:
8043467 ->
7976364 (-0.83%)
68427730 ->
68483042 (0.08%)
CHV:
8045019 ->
7977916 (-0.83%)
68297426 ->
68352756 (0.08%)
SKL:
8204037 ->
7939086 (-3.23%)
66583900 ->
65624378 (-1.44%)
Lost->Gained Total spills Total fills
BWR: 5 -> 5 1488 -> 1488 (0.00%) 1957 -> 1957 (0.00%)
ELK: 5 -> 5 1489 -> 1489 (0.00%) 1958 -> 1958 (0.00%)
ILK: 1 -> 4 1449 -> 1449 (0.00%) 1921 -> 1921 (0.00%)
SNB: 0 -> 0 549 -> 549 (0.00%) 52 -> 52 (0.00%)
IVB: 13 -> 3 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%)
HSW: 11 -> 0 1271 -> 1271 (0.00%) 1162 -> 1162 (0.00%)
BDW: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%)
CHV: 12 -> 0 1340 -> 1340 (0.00%) 1452 -> 1452 (0.00%)
SKL: 0 -> 120 1269 -> 375 (-70.45%) 1563 -> 690 (-55.85%)
v3: Non-trivial rebase.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Thu, 23 Apr 2015 11:36:16 +0000 (14:36 +0300)]
i965: Let the caller of brw_set_dp_write/read_message control the target cache.
brw_set_dp_read_message already had a target_cache argument, but its
interpretation was rather convoluted (on Gen6 the render cache was
used if the caller asked for it, otherwise it was ignored using the
sampler cache instead), and the constant cache wasn't representable at
all. brw_set_dp_write_message used the data cache on Gen7+ except for
RENDER_TARGET_WRITE messages, in which case it would use the render
cache. On Gen6 the render cache was always used.
Instead of the above, provide the shared unit SFID that the caller
expects will be used. Makes no functional changes.
v3: Non-trivial rebase.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Francisco Jerez [Fri, 9 Dec 2016 02:00:17 +0000 (18:00 -0800)]
i965/gen6+: Invalidate constant cache on brw_emit_mi_flush().
In order to make sure that the constant cache is coherent with
previous rendering when we start using it for pull constant loads.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Kenneth Graunke [Mon, 21 Nov 2016 08:11:57 +0000 (00:11 -0800)]
genxml: Make Gen8 3DSTATE_DS SIMD8 enable work like Gen9+.
This will let us avoid ifdefs.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Kenneth Graunke [Mon, 21 Nov 2016 08:09:11 +0000 (00:09 -0800)]
genxml: Rename "DS Function Enable" to "Function Enable".
This makes Gen7/7.5 match Gen8-9.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Chad Versace [Thu, 17 Nov 2016 20:45:26 +0000 (12:45 -0800)]
anv: Reject VkMemoryAllocateInfo::allocationSize == 0
The Vulkan 1.0.33 spec says "allocationSize must be greater than 0".
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Chad Versace [Tue, 13 Dec 2016 22:23:55 +0000 (14:23 -0800)]
egl: Fix crashes in eglCreate*Surface()
Don't dereference a null EGLDisplay.
Fixes tests
dEQP-EGL.functional.negative_api.create_pbuffer_surface
dEQP-EGL.functional.negative_api.create_pixmap_surface
Reviewed-by: Mark Janes <mark.a.janes@intel.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=99038
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 6 Dec 2016 20:03:28 +0000 (12:03 -0800)]
i965/miptree: Use intel_miptree_copy for maps
What we're really doing is copying a texture not blitting it in the sense
of glBlitFramebuffers. Also, the intel_miptree_copy function is capable of
properly handling compressed textures which intel_miptree_blit is not.
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=97473
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Jason Ekstrand [Tue, 6 Dec 2016 20:03:11 +0000 (12:03 -0800)]
i965/blit: Fix the src dimension sanity check in miptree_copy
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Lionel Landwerlin [Thu, 8 Dec 2016 12:26:38 +0000 (12:26 +0000)]
docs: add INTEL_conservative_rasterization to relaese notes for 13.1.0
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 12:11:43 +0000 (12:11 +0000)]
main: add INTEL_conservative_rasterization enum query support
v2: add extra parameter (Ilia)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Fri, 9 Dec 2016 16:51:38 +0000 (16:51 +0000)]
glapi: add missing INTEL_conservative_rasterization
v2: put enum directly in gl_API.xml (Ilia)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 11:00:01 +0000 (11:00 +0000)]
extensions: update INTEL_conservative_rasterization dependencies
Suggested by Ilia.
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Thu, 8 Dec 2016 11:00:00 +0000 (11:00 +0000)]
main: don't error when enabling conservative rasterization on gles
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Lionel Landwerlin [Mon, 12 Dec 2016 12:30:26 +0000 (12:30 +0000)]
main: use new driver flag for conservative rasterization state
Suggested by Marek.
v2: Use new driver flag (Marek)
v3: Fix i965 comments (Lionel)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Iago Toral Quiroga [Mon, 12 Dec 2016 12:43:53 +0000 (13:43 +0100)]
nir/lower_tex: lower gradients on shadow cube maps if lower_txd_shadow is set
Even if lower_txd_cube_map isn't. Suggested by Ken to make the flag more
consistent with its name.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 10:45:59 +0000 (11:45 +0100)]
i965: remove brw_lower_texture_gradients
This has been ported to NIR now so we don'tneed to keep the GLSL IR
lowering any more.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Tue, 13 Dec 2016 09:24:19 +0000 (10:24 +0100)]
i965/nir: enable lowering of texture gradient for shadow samplers
This gets the lowering on the Vulkan driver too, which is required for
hardware that does not have the sample_l_d message (up to IvyBridge).
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 10:31:01 +0000 (11:31 +0100)]
nir/lower_tex: add lowering for texture gradient on shadow samplers
This is ported from the Intel lowering pass that we use with GLSL IR.
This takes care of lowering texture gradients on shadow samplers other
than cube maps. Intel hardware requires this for gen < 8.
v2 (Ken):
- Use the helper function to retrieve ddx/ddy
- Swizzle away size components we are not interested in
v3:
- Get rid of the ddx/ddy helper and use nir_tex_instr_src_index
instead (Ken, Eric)
v4:
- Add a 'continue' statement if the lowering makes progress because it
replaces the original texture instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v3)
Iago Toral Quiroga [Wed, 30 Nov 2016 08:44:20 +0000 (09:44 +0100)]
i965/nir: enable lowering of texture gradient for cube maps
This gets the lowering on the Vulkan driver too.
Fixes Vulkan CTS cube map texture gradient tests in:
dEQP-VK.glsl.texture_functions.texturegrad.*
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Iago Toral Quiroga [Wed, 30 Nov 2016 08:40:43 +0000 (09:40 +0100)]
nir/lower_tex: add lowering for texture gradient on cube maps
This is ported from the Intel lowering pass that we use with GLSL IR.
The NIR pass only handles cube maps, not shadow samplers, which are
also lowered for gen < 8 on Intel hardware. We will add support for
that in a later patch, at which point we should be able to remove
the GLSL IR lowering pass.
v2:
- added a helper to retrieve ddx/ddy parameters (Ken)
- No need to make size.z=1.0, we are only using component x anyway (Iago)
v3:
- Get rid of the ddx/ddy helper and use nir_tex_instr_src_index
instead (Ken, Eric)
v4:
- When emitting the textureLod operation, copy all texture parameters
from the original textureGrad() (except for ddx/ddy) using a loop
- Add a 'continue' statement if the lowering makes progress because it
replaces the original texture instruction
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> (v3)