Eddie Hung [Wed, 11 Mar 2020 13:32:15 +0000 (06:32 -0700)]
Merge pull request #1743 from YosysHQ/eddie/abc9_keep
abc9: improve (* keep *) handling
Eddie Hung [Wed, 11 Mar 2020 13:31:06 +0000 (06:31 -0700)]
Merge pull request #1744 from YosysHQ/eddie/fix1675
Bump ABCREV to receive fix for #1675
David Shah [Tue, 10 Mar 2020 13:51:59 +0000 (13:51 +0000)]
Merge pull request #1753 from YosysHQ/dave/abc9-speedup
Add ScriptPass::run_nocheck and use for abc9
David Shah [Tue, 10 Mar 2020 13:51:40 +0000 (13:51 +0000)]
Merge pull request #1721 from YosysHQ/dave/tribuf-unused
deminout: Don't demote inouts with unused bits
N. Engelhardt [Tue, 10 Mar 2020 12:10:50 +0000 (13:10 +0100)]
Merge pull request #1755 from boqwxp/add_cmd_cleanup
Clean up `passes/cmds/add.cc` code style.
Alberto Gonzalez [Tue, 10 Mar 2020 10:37:10 +0000 (10:37 +0000)]
Clean up passes/cmds/add.cc code style.
Eddie Hung [Mon, 9 Mar 2020 18:51:57 +0000 (11:51 -0700)]
Merge pull request #1747 from YosysHQ/claire/partselfix
Fix partsel expr bit width handling and add test case
David Shah [Mon, 9 Mar 2020 14:34:22 +0000 (14:34 +0000)]
Add ScriptPass::run_nocheck and use for abc9
Signed-off-by: David Shah <dave@ds0.me>
N. Engelhardt [Mon, 9 Mar 2020 10:04:08 +0000 (11:04 +0100)]
Merge pull request #1716 from zeldin/ecp5_fix
ecp5: remove unused parameter from \$__ECP5_PDPW16KD
Claire Wolf [Sun, 8 Mar 2020 15:12:12 +0000 (16:12 +0100)]
Fix partsel expr bit width handling and add test case
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Eddie Hung [Fri, 6 Mar 2020 18:51:47 +0000 (10:51 -0800)]
xaiger: remove some unnecessary operations ...
... since they can not be triggered by (* keep *) anymore
(but could still be triggered by (* abc9_scc *) !?!)
Eddie Hung [Fri, 6 Mar 2020 18:32:48 +0000 (10:32 -0800)]
Bump ABCREV to receive fix for #1675
Eddie Hung [Fri, 6 Mar 2020 18:30:07 +0000 (10:30 -0800)]
abc9: for sccs, create a new wire instead of using entirety of existing
Eddie Hung [Fri, 6 Mar 2020 18:20:30 +0000 (10:20 -0800)]
abc9: (* keep *) wires to be PO only, not PI as well; fix scc handling
Eddie Hung [Fri, 6 Mar 2020 18:09:01 +0000 (10:09 -0800)]
abc: add abc.debug scratchpad option
N. Engelhardt [Fri, 6 Mar 2020 15:45:36 +0000 (16:45 +0100)]
remove unused parameters
Miodrag Milanović [Fri, 6 Mar 2020 15:06:54 +0000 (16:06 +0100)]
Merge pull request #1742 from nakengelhardt/rpc-test-again
More rpc test fixes
N. Engelhardt [Fri, 6 Mar 2020 14:29:01 +0000 (15:29 +0100)]
rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors
Eddie Hung [Thu, 5 Mar 2020 17:41:54 +0000 (09:41 -0800)]
Merge pull request #1739 from YosysHQ/eddie/issue1738
ice40: fix specify for -device {lp,u}
Eddie Hung [Thu, 5 Mar 2020 16:11:49 +0000 (08:11 -0800)]
ice40: fix specify for ICE40_{LP,U}
Eddie Hung [Thu, 5 Mar 2020 16:08:32 +0000 (08:08 -0800)]
tests: extend tests/arch/run-tests.sh for defines
Eddie Hung [Wed, 4 Mar 2020 23:28:17 +0000 (15:28 -0800)]
ice40: fix implicit signal in specify, also clamp negative times to 0
Eddie Hung [Wed, 4 Mar 2020 21:37:09 +0000 (13:37 -0800)]
Merge pull request #1735 from YosysHQ/eddie/abc9_dsp48e1
xilinx: cleanup DSP48E1 handling for abc9
Eddie Hung [Wed, 4 Mar 2020 20:04:02 +0000 (12:04 -0800)]
xilinx: consider DSP48E1.ADREG
Eddie Hung [Wed, 4 Mar 2020 19:28:14 +0000 (11:28 -0800)]
xilinx: cleanup DSP48E1 handling for abc9
Eddie Hung [Wed, 4 Mar 2020 18:51:33 +0000 (10:51 -0800)]
xilinx: improve specify for DSP48E1
Eddie Hung [Wed, 4 Mar 2020 18:32:51 +0000 (10:32 -0800)]
xilinx: missing DSP48E1.PCIN timing from abc9_{map,model}.v
David Shah [Tue, 25 Feb 2020 14:14:45 +0000 (14:14 +0000)]
deminout: Don't demote inouts with unused bits
Signed-off-by: David Shah <dave@ds0.me>
N. Engelhardt [Tue, 3 Mar 2020 18:15:41 +0000 (19:15 +0100)]
Merge pull request #1691 from ZirconiumX/use-flowmap-in-noabc
Add -flowmap option to `synth{,_ice40}`
Claire Wolf [Tue, 3 Mar 2020 16:41:55 +0000 (08:41 -0800)]
Fix bison warning for "pure-parser" option
Signed-off-by: Claire Wolf <claire@symbioticeda.com>
Claire Wolf [Tue, 3 Mar 2020 16:38:32 +0000 (08:38 -0800)]
Merge pull request #1718 from boqwxp/precise_locations
Closes #1717. Add more precise Verilog source location information to AST and RTLIL nodes.
Claire Wolf [Tue, 3 Mar 2020 16:34:31 +0000 (08:34 -0800)]
Merge pull request #1681 from YosysHQ/eddie/fix1663
verilog: instead of modifying localparam size, extend init constant expr
Claire Wolf [Tue, 3 Mar 2020 16:19:06 +0000 (08:19 -0800)]
Merge pull request #1519 from YosysHQ/eddie/submod_po
submod: several bugfixes
Marcelina Kościelnicka [Mon, 2 Mar 2020 20:40:09 +0000 (21:40 +0100)]
iopadmap: Look harder for already-present buffers. (#1731)
iopadmap: Look harder for already-present buffers.
Fixes #1720.
Eddie Hung [Mon, 2 Mar 2020 20:32:27 +0000 (12:32 -0800)]
Merge pull request #1724 from YosysHQ/eddie/abc9_specify
abc9: auto-generate *.lut/*.box files and arrival/required times from specify entries
N. Engelhardt [Mon, 2 Mar 2020 11:31:05 +0000 (12:31 +0100)]
Merge pull request #1729 from rqou/coolrunner2
coolrunner2 buffer cell insertion fixes
R. Ou [Mon, 2 Mar 2020 09:40:57 +0000 (01:40 -0800)]
coolrunner2: Attempt to give wires/cells more meaningful names
R. Ou [Mon, 2 Mar 2020 09:06:03 +0000 (01:06 -0800)]
coolrunner2: Fix invalid multiple fanouts of XOR/OR gates
In some cases where multiple output pins share identical combinatorial
logic, yosys would only generate one $sop cell and therefore one
MACROCELL_XOR cell to try to feed the multiple sinks. This is not valid,
so make the fixup pass duplicate cells when necessary. For example,
fixes the following code:
module top(input a, input b, input clk_, output reg o, output o2);
wire clk;
BUFG bufg0 (
.I(clk_),
.O(clk),
);
always @(posedge clk)
o = a ^ b;
assign o2 = a ^ b;
endmodule
R. Ou [Mon, 2 Mar 2020 08:32:36 +0000 (00:32 -0800)]
coolrunner2: Fix packed register+input buffer insertion
The register will be packed with the input buffer if and only if the
input buffer doesn't have any other loads.
R. Ou [Sun, 1 Mar 2020 14:54:07 +0000 (06:54 -0800)]
coolrunner2: Insert many more required feedthrough cells
Eddie Hung [Sat, 29 Feb 2020 16:15:24 +0000 (08:15 -0800)]
Merge pull request #1727 from YosysHQ/eddie/fix_write_smt2
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
Eddie Hung [Fri, 28 Feb 2020 20:33:55 +0000 (12:33 -0800)]
ystests: fix write_smt2_write_smt2_cyclic_dependency_fail
Eddie Hung [Fri, 28 Feb 2020 18:39:03 +0000 (10:39 -0800)]
Merge pull request #1726 from YosysHQ/eddie/fix1710
ast: fixes #1710; do not generate RTLIL for unreachable ternary branch
Dan Ravensloft [Fri, 28 Feb 2020 14:29:57 +0000 (14:29 +0000)]
Add -flowmap to synth and synth_ice40
Eddie Hung [Fri, 28 Feb 2020 00:55:55 +0000 (16:55 -0800)]
ast: fixes #1710; do not generate RTLIL for unreachable ternary
Eddie Hung [Fri, 28 Feb 2020 00:53:49 +0000 (16:53 -0800)]
Comment out log()
Eddie Hung [Thu, 27 Feb 2020 18:33:04 +0000 (10:33 -0800)]
Remove RAMB{18,36}E1 from cells_xtra.py
Eddie Hung [Thu, 27 Feb 2020 18:29:53 +0000 (10:29 -0800)]
Small fixes
Eddie Hung [Thu, 20 Feb 2020 15:52:08 +0000 (07:52 -0800)]
Fixes for older compilers
Eddie Hung [Wed, 19 Feb 2020 17:47:36 +0000 (09:47 -0800)]
Revert "Fix tests/arch/xilinx/fsm.ys to count flops only"
This reverts commit
68f903c6dd7403a4cf280cf71ee02d20345938b5.
Eddie Hung [Tue, 18 Feb 2020 23:32:56 +0000 (15:32 -0800)]
ast: quiet down when deriving blackbox modules
Eddie Hung [Tue, 18 Feb 2020 22:31:24 +0000 (14:31 -0800)]
abc9_ops: suppress -prep_box warning for abc9_flop
Eddie Hung [Tue, 18 Feb 2020 22:28:52 +0000 (14:28 -0800)]
xilinx: Update RAMB* specify entries
Eddie Hung [Tue, 18 Feb 2020 19:03:59 +0000 (11:03 -0800)]
ice40: add delays to SB_CARRY
Eddie Hung [Tue, 18 Feb 2020 19:03:38 +0000 (11:03 -0800)]
xilinx: add delays to INV
Eddie Hung [Tue, 18 Feb 2020 19:02:28 +0000 (11:02 -0800)]
Make TimingInfo::TimingInfo(SigBit) constructor explicit
Eddie Hung [Tue, 18 Feb 2020 16:41:48 +0000 (08:41 -0800)]
TimingInfo: index by (port_name,offset)
Eddie Hung [Tue, 18 Feb 2020 16:30:41 +0000 (08:30 -0800)]
Fix spacing
Eddie Hung [Sat, 15 Feb 2020 17:13:21 +0000 (09:13 -0800)]
More +/ice40/cells_sim.v fixes
Eddie Hung [Sat, 15 Feb 2020 16:29:10 +0000 (08:29 -0800)]
Cleanup tests
Eddie Hung [Sat, 15 Feb 2020 16:27:41 +0000 (08:27 -0800)]
Update bug1630.ys to use -lut 4 instead of lut file
Eddie Hung [Sat, 15 Feb 2020 02:56:10 +0000 (18:56 -0800)]
Make +/xilinx/cells_sim.v legal
Eddie Hung [Fri, 14 Feb 2020 21:53:28 +0000 (13:53 -0800)]
abc9_ops: still emit delay table even box has no timing
Eddie Hung [Fri, 14 Feb 2020 21:43:34 +0000 (13:43 -0800)]
write_xaiger: add comment about arrival times of flop outputs
Eddie Hung [Fri, 14 Feb 2020 21:26:00 +0000 (13:26 -0800)]
abc9_ops: demote lack of box timing info to warning
Eddie Hung [Fri, 14 Feb 2020 20:54:47 +0000 (12:54 -0800)]
Get rid of (* abc9_{arrival,required} *) entirely
Eddie Hung [Fri, 14 Feb 2020 20:01:03 +0000 (12:01 -0800)]
abc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung [Fri, 14 Feb 2020 19:41:43 +0000 (11:41 -0800)]
abc9_ops: use TimingInfo for -prep_{lut,box} too
Eddie Hung [Fri, 14 Feb 2020 19:11:34 +0000 (11:11 -0800)]
abc9_ops: add and use new TimingInfo struct
Eddie Hung [Fri, 14 Feb 2020 18:31:38 +0000 (10:31 -0800)]
Fix tests/arch/xilinx/fsm.ys to count flops only
Eddie Hung [Fri, 14 Feb 2020 17:17:53 +0000 (09:17 -0800)]
Expand +/xilinx/cells_sim.v to keep ICARUS and non -specify paresr happy
Eddie Hung [Fri, 14 Feb 2020 17:17:20 +0000 (09:17 -0800)]
ice40: fix specify for inverted clocks
Eddie Hung [Thu, 13 Feb 2020 21:43:33 +0000 (13:43 -0800)]
Fix tests by gating some specify constructs from iverilog
Eddie Hung [Thu, 13 Feb 2020 20:13:12 +0000 (12:13 -0800)]
Update simple_abc9 tests
Eddie Hung [Thu, 13 Feb 2020 19:15:59 +0000 (11:15 -0800)]
abc9_ops: ignore (* abc9_flop *) if not '-dff'
Eddie Hung [Thu, 13 Feb 2020 18:30:56 +0000 (10:30 -0800)]
ice40: specify fixes
Eddie Hung [Thu, 13 Feb 2020 18:30:29 +0000 (10:30 -0800)]
abc9_ops: sort LUT delays to be ascending
Eddie Hung [Thu, 13 Feb 2020 17:58:20 +0000 (09:58 -0800)]
ice40: move over to specify blocks for -abc9
Eddie Hung [Thu, 13 Feb 2020 17:56:52 +0000 (09:56 -0800)]
synth_ecp5: use +/abc9_model.v
Eddie Hung [Thu, 13 Feb 2020 17:56:30 +0000 (09:56 -0800)]
Update xilinx for ABC9
Eddie Hung [Thu, 13 Feb 2020 17:56:00 +0000 (09:56 -0800)]
Create +/abc9_model.v for $__ABC9_{DELAY,FF_}
Eddie Hung [Thu, 13 Feb 2020 17:54:40 +0000 (09:54 -0800)]
abc9_ops: output LUT area
Eddie Hung [Thu, 13 Feb 2020 17:50:17 +0000 (09:50 -0800)]
ecp5: remove small LUT entries
Eddie Hung [Thu, 13 Feb 2020 17:48:48 +0000 (09:48 -0800)]
abc9_ops: cope with T_LIMIT{,2}_{MIN,TYP,MAX} and auto-gen small LUTs
Eddie Hung [Thu, 13 Feb 2020 00:06:24 +0000 (16:06 -0800)]
Fix commented out specify statement
Eddie Hung [Wed, 12 Feb 2020 23:25:30 +0000 (15:25 -0800)]
xilinx: improve specify functionality
Eddie Hung [Wed, 12 Feb 2020 19:30:37 +0000 (11:30 -0800)]
ecp5: deprecate abc9_{arrival,required} and *.{lut,box}
Eddie Hung [Tue, 11 Feb 2020 22:22:43 +0000 (14:22 -0800)]
xilinx: use specify blocks in place of abc9_{arrival,required}
Eddie Hung [Tue, 11 Feb 2020 19:38:49 +0000 (11:38 -0800)]
Auto-generate .box/.lut files from specify blocks
Eddie Hung [Tue, 11 Feb 2020 17:18:08 +0000 (09:18 -0800)]
abc9_ops: assert on $specify2 properties
Eddie Hung [Tue, 11 Feb 2020 16:54:13 +0000 (08:54 -0800)]
abc9_ops: -prep_box, to be called once
Eddie Hung [Tue, 11 Feb 2020 16:34:13 +0000 (08:34 -0800)]
abc9_ops: -prep_lut and -write_lut to auto-generate LUT library
Claire Wolf [Thu, 27 Feb 2020 18:05:56 +0000 (19:05 +0100)]
Merge pull request #1709 from rqou/coolrunner2_counter
Improve CoolRunner-II optimization by using extract_counter pass
Claire Wolf [Thu, 27 Feb 2020 18:03:59 +0000 (19:03 +0100)]
Merge pull request #1708 from rqou/coolrunner2-buf-fix
coolrunner2: Separate and improve buffer cell insertion pass
Piotr Binkowski [Thu, 27 Feb 2020 10:21:01 +0000 (11:21 +0100)]
xilinx: mark IOBUFDSE3 IOB pin as external
Miodrag Milanović [Wed, 26 Feb 2020 12:32:49 +0000 (13:32 +0100)]
Merge pull request #1705 from YosysHQ/logger_pass
Logger pass
Miodrag Milanovic [Wed, 26 Feb 2020 08:49:41 +0000 (09:49 +0100)]
Remove tests for now
Alberto Gonzalez [Mon, 24 Feb 2020 02:41:08 +0000 (02:41 +0000)]
Change attribute search value to specify precise location instead of simple line number.
Alberto Gonzalez [Mon, 24 Feb 2020 01:39:36 +0000 (01:39 +0000)]
Change attribute search value to specify precise location instead of simple line number.
Miodrag Milanovic [Sun, 23 Feb 2020 09:56:39 +0000 (10:56 +0100)]
Add tests for logger pass