mem,ext: Integrating DRAMSim3 with gem5

Adding DRAMSim3 source code to the gem5 source code, the original
code was taken from umd-memsys github at https://github.com/umd-memsys/

Change-Id: I32c982206f33b0acf2121f322d15baa064c412c4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31757
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem,ext: Fixed DRAMSim2 Integration

Fixed the way callbacks were used due to changes in
src/sim/callback.hh. Removed author line in SConsript.

Change-Id: I2c2b8dbe13e4f58680806126cd9cf209748e788a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33938
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Relax packet limit in packet queue

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: I4ac24bf18a0aff08a5b33c48179b882b27ef910c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30317
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Add uReset helper to UPCState

This allows to reset without advancing the pc

https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Ied566f4cd5efed5eb500447d3f14388482435475
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30315
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>

arch, mem: Initial Hardware Transactional Memory implementation

Gem5 Hardware Transactional Memory (HTM)

Here we provide a brief note describing HTM support in Gem5 at
a high level.

HTM is an architectural feature that enables speculative concurrency in
a shared-memory system; groups of instructions known as transactions are
executed as an atomic unit. The system allows that transactions be
executed concurrently but intervenes if a transaction's
atomicity/isolation is jeapordised and takes corrective action. In this
implementation, corrective active explicitely means rolling back a
thread's architectural state and reverting any memory updates to a point
just before the transaction began.

This HTM implementation relies on--
(1) A checkpointing mechanism for architectural register state.
(2) Buffering speculative memory updates.

This patch is focusing on the definition of the HTM checkpoint (1)

The checkpointing mechanism is architecture dependent. Each ISA
leveraging HTM support can define a class HTMCheckpoint inhereting from
the generic one (GenericISA::HTMCheckpoint).

Those will need to save/restore the architectural state by overriding
the virtual HTMCheckpoint::save (when starting a transaction) and
HTMCheckpoint::restore (when aborting a transaction).

Instances of this class live in O3's ThreadState and Atomic's
SimpleThread.  It is up to the ISA to populate this instance when
executing an instruction that begins a new transaction.

JIRA: https://gem5.atlassian.net/browse/GEM5-587

Change-Id: Icd8d1913d23652d78fe89e930ab1e302eb52363d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Remove the "fault" parameter from syscall functions.

This parameter was never set or used, just plumbed everywhere,
occasionally with a dummy value. This change removes all of that
plumbing.

Change-Id: I9bc31ffd1fbc4952c5d3096f7f21eab30102300b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33277
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

arch-arm,arch-x86: Added missing overrides

These overrides were missing, causing compilation errors when
compiling with clang 9. Noted here:
https://www.mail-archive.com/gem5-dev@gem5.org/msg35657.html

Change-Id: I6d09a0e57af3131b9172d01468d2cdcf4b444c5d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33817
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Add missing overrides in the *Fault classes

Change-Id: I7a74df78f0f85ccf7fd896f98b301c1f998c1497
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33777
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Make the Value stat's functor method accept lambdas.

This class can already accept a proxy variable and a "functor" which is
a pointer to either a function or an instance of a class with the ()
operator overloaded.

This change adds a FunctorProxy partial specialization which accepts
anything that can be used to construct a std::function<Result()>. The
constructor argument is copied and stored in the proxy which makes it
possible to define a lambda inline without having to keep a copy of it
around for the proxy to point to.

Also, the ValueBase stat's functor method now has a second version which
accepts a const reference rather than just a reference to its argument.
We need both because when accepting a reference to a lambda it needs to
be a const reference, but when accepting a pointer to a functor object,
we don't want it to be const because that would force the () operator to
also be const.

Change-Id: Icb1b3682d51b721f6e16614490ed0fe289cee094
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32901
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>

scons: Make scons aware of changes to cxx_type in param types.

If the cxx_type value changes, then the way the parameter is declared
in the param struct will also change, and the header needs to be
updated. scons would miss this sort of change before because it was only
checking the module the SimObject's source came from. The python names
and types of the parameters could stay the same, but the C++
representation might have changed because of edits somewhere else.

This CL assumes that cxx_type is the only thing that will change and
transparently affect the params struct. I tried making scons sensitive
to the entire ptype which would capture other parameters, but that
didn't work for some reason. This should be pretty safe in general, but
not 100% safe

Issue-on: https://gem5.atlassian.net/browse/GEM5-753
Change-Id: I06774889e60b987f727799f55d7ea2a775b6a319
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33695
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test: Fix unittest cprintftime's build.

This test, which measures the performance of cprintf vs. sprintf, was
missing a couple of includes which were needed for the alarm() and
signal() functions, as well as the SIGALRM constant.

Also, it was using %#x to print the value of a pointer which gcc
complained about when compiling sprintf. This is fixed by changing that
format specifier to %p, the specifier to use when printing pointers.
Apparently either the implicit conversion to an integer value (which %#x
expects) or the size of the type it was converted to weren't good enough
for gcc any more.

Change-Id: I8eca3479bef2c2fa79f8ef4881bb3ff35d7c54ca
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33897
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test: Remove refcnttest from the unittest SConscript.

The test itself was removed, but it was left in the SConscript. If you
tell scons to build everything in that directory, it will try to build
that test and fail.

Change-Id: I1e3923b0de12e891f53dab6f4e6e3e2b6975dc45
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33896
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Added missing header to hsa_driver.cc

`TypedBufferArg`, used in `src/dev/hsa/hsa_driver.cc` is defined in
`src/sim/syscall_emul_buf.hh` yet was not included. This commit adds
this missing header.

Change-Id: I3239a097eb71b6ebdad045eab6525a888a970f08
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33816
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix copy ellision on base compressor

Newer compiler versions have a problem with this move as
it prevents copy elision.

Change-Id: I802703df12e171d6a377b673d0ad7e202456b516
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Remove unused variable pcbb from ThreadInfo

Change-Id: Ib9e46934f1613c98758662cba26a46fcc2a76146
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33776
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Avoid the unsupported option -Wno-c99-designator in MacOS

Change-Id: I4d95c75915b17531bdd6d9161eb266bb91cd7bef
Signed-off-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33775
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Import reduce function in FileSystemConfig

Not sure if this is required due to python3 or something else, but I got
the error "NameError: name 'reduce' is not defined". This fixes that
error.

Change-Id: I2dd71674306abcad1a90311664b18b9eee29b9ac
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32374
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Change request to response in MOESI_AMD_Base-dir.sm

The responseToDMA MessageBuffer in MOESI_AMD_Base-dir.sm
transmits both data and acks, but it's vnet_type is currently
set as request. This should be changed to response.

Signed-off-by: Sampad Mohapatra <sampad.mohapatra@gmail.com>
Change-Id: I0eb9e8fc8e25111849605a710a5150ce5fc3b83b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33755
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Remove the AddLocalOption workaround.

The "append" option of the Help() scons method can be used to avoid
clobbering the built in and local option help.

This has the nice side effect of making it easier to add options in
other files since you now only need the built in AddOption provided by
scons itself, not the custom AddLocalOption version.

Change-Id: Ifa566087797d578df0c90f8f4fca70c8152fbf63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

mem-cache: Use cache's max CR on perfect compressor

Use cache's max_compression_ratio to setup the max_compression_ratio
of the PerfectCompressor.

Change-Id: Ib44aa61975fb2cc52f27f64a86c9df9c5531aa1a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33387
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Explicitly define threshold of BDI's sub-compressors

Allow all sub-compressors of BDI to be successful as long as
they are able to compress. Then, BDI's actual size threshold
acts as the cutting point.

This situation arises on any multi compressor; yet, generalizing
this assumption might be too bold.

Change-Id: Iec5057d16d4a7ba5fb573133a30ea10869bd67e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33386
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Make compression size threshold a percentage

By changing the parameter into a percentage, changing the block
size will automatically reconfigure the size threshold. Also,
change the default percentage to 50% to avoid storing blocks
unlikely to co-allocate in compressed format.

Change-Id: I1458f19db39becc2d40c00269132fea01770016f
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33385
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add stats for failed compressions

Add statistics to keep track of the number of times compression
has failed to provide blocks whose compressed size passes the
size threshold.

Also, update the compressed data's size if compression fails.

Change-Id: If3479572bf114f07911238c602ffef3a90b6a931
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33384
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Handle zero sizes on compression

The size can be zero in special occasions, which would
generate divisions by zero. This patch expands the
stats to support them. It also fixes the compression
factor calculation in the Multi compressor.

As a side effect, now that zero sizes are handled, allow
the Zero compressor to generate it.

Change-Id: I9f7dee76576b09fdc9bef3e1f3f89be3726dcbd9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33383
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add an extra decomp lat to multi compressor

There is extra hardware required when dealing with multi
compressors. As such, add a parameter to allowing increasing
their decompression latency to account for any extra delay.

Change-Id: I153e4c5ab6927ac092e2ebd767fe88974597bb20
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33382
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Store BDI's encoding in tags

According to the original paper the compressors' encodings are
stored in the tag-store (Storage cost analysis section).

Change-Id: I4c34f86022eea6d1ba0ae29dd74d5714bbad367a
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33381
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Add encoding bits to the data of multi compressors

When compressing using a multi-compressor, one must be able to
identify which sub-compressor should be used to decompress data.
This can be achieved by either adding encoding bits to block's
tag or data entry.

It was previously assumed that these encoding bits would be added
to the tag, but now make it a parameter that defaults to the data
entry.

Change-Id: Id322425e7a6ad59cb2ec7a4167a43de4c55c482c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33380
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Standardize data parsing in compressors

The compressors are not able to process a whole line at once,
so they must divide it into multiple same-sized chunks. This
patch makes the base compressor responsible for this division,
so that the derived classes are mostly agnostic to this
translation.

This change has been coupled with a change of the signature
of the public compress() to avoid introducing a temporary
function rename. Previously, this function did not return
the compressed data, under the assumption that everything
related to the compressed data would be handled by the
compressor. However, sometimes the units using the compressor
could need to know or store the compressed data.

For example, when sharing dictionaries the compressed data
must be checked to determine if two blocks can co-allocate
(DISH, Panda et al. 2016).

Change-Id: Id8dbf68936b1457ca8292cc0a852b0f0a2eeeb51
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33379
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Allow inheriting from DitionaryCompressor's comp data

Previously either the compression data was the one declared within
DictionaryCompressor, or the derived class would have to override
the compress() to use a derived compression data.

With this change, the instantiation can be overridden, and thus
any derived class can choose the compression data pointer type
they need to use.

Change-Id: I387936265a3de6785a6096c7a6bd21774202b1c7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33378
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Upgrade Compressor::Multi's stats

Use new style stats API for Compressor::Multi's stats.

Change-Id: Ia0313704cae4e7bd6bc675c71ea75b42a8e542f2
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33377
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Upgrade BaseDictionaryCompressor's stats

Upgrade this compressor's stats to match current stats API.

Change-Id: I1cb69230f8deca053bc860cedafc9e6e78446df7
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33376
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix RepeatedQwords compressor

This compressor does not allocate dictionary entries when there
is a match. This was causing the compressor to always fail.

Change-Id: I50eb56fa284854f3ee87f33af2c6e0a5c5248d7c
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33375
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Fix integer promotion of mask

When applying the bitwise not to a short integer the compiler
automatically promotes it to an integer. For example, if a 8-bit
mask=0xFF, and the compiler decides to promote the mask to 32-bit
to apply the bitwise not, ~mask=0xFFFFFF00, which will yield wrong
results for popcount(): expected=0, got=24.

Change-Id: I95efba5532c27ca004ff6947d4b51a8a14f09741
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33374
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Use VPtr in hsa_driver.cc

This change updates HSADriver::allocateQueue to take in a ThreadContext
pointer as opposed to a PortProxy ref. This allows the TypedBufferArg
to be replaced with VPtr.

This also fixes building GCN3_X86

Change-Id: I1fea26b10c7344daf54a0cb05337e961f834a5fd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33655
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: convert base prefetcher and queued to new style stats

Base and Queued inside src/mem/cache/prefetch converted

Change-Id: I3d5907b58efefc4d8522b89f073507f2548bff2f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33475
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

base: avoid recreating socket at each call to listen()

A new socket was created each time listen() is called,
which is problematic when the bind or listen operation
on it are not successful (mostly because the associated port is
already in use). It can lead gem5 to open too many files and crash
for multicores configurations, a socket being created
for remote GDB for each core. The other way to deal with
this problem would be to close the socket in the case the
function return false. But I find the proposed solution
simpler.

Change-Id: I848955a10c89e1da033bf773c83556a5dc5ef9a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32994
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Set the minimum scons version to 3.0.

Change-Id: Id57a93e819588d2231d2d2d8b28cd62b05fbbe9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33675
Reviewed-by: Steve Reinhardt <stever@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Add parameter for GPU scalar cache mandatory queue size

There was a missing option (--buffers-size) used to set the mandatory
queue size for the scalar controllers. This patch renames the option to
be more clear, and adds it to the argument parser.

Default of 128 taken from the implementation on the GCN staging branch

Change-Id: I58b6b57be07498cdf6e39c0bb85982674ec4caa6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32676
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Fix db_offset calculation

db_offset used to be calculated through pointer arithmetic. Pointer
arithmetic increments the address by the size of the data type the
pointer is pointing at. In the previous db_offset calculation, that
was a uint32_t, which means the input was multiplied by 4, which is
sizeof(uint32_t)

This patch multiplies the input value by sizeof(uint32_t) before
assigning it to db_offset.

Change-Id: I9042560303ae6b8b1054b98e9a16a9da27843bb2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32678
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: set hsaTopology properties from options

This change sets the properties in hsaTopology to the proper values
specified by the user through command-line arguments. This ensures
that if the properties file is read by a program, it will return
the correct values for the simulated hardware.

This change also adds in a command-line argument for the lds size, as
it was the only other property used in hsaTopology that didn't have
a command-line argument. The default value (65536) is taken from
src/gpu-compute/LdsState.py

Change-Id: I17bb812491708f4221c39b738c906f1ad944614d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31995
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

ext: remove libelf

Change-Id: I52eb9a7bb7d9f3522ff565498dc2821a0d1ed0d6
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33318
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

base: Use system libelf instead of ext

The only change needed is to remove EM_SPARC64, which from what I can
tell was removed from elf.h in 1998.

https://sources.debian.org/src/glibc/2.24-11+deb9u1/ChangeLog.8/#L6134

Change-Id: I0dd7e23ea44b19c2ebd9c6eff7cbaedfe69d821b
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33317
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>

util: Updated Dockfiles with the libelf-dev dep

This is required if we eventually remove `ext/libelf` (
https://gem5.atlassian.net/browse/GEM5-752), otherwise our tests will
fail.

The corresponding Docker images have been built and uploaded to:
https://gcr.io/gem5-test/

Change-Id: I1bd069dfb968b56eac4c4da33929b5ff895eaa6f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33596
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Added GCN-GPU to cloudbuild_create_images

This adds the GCN-GPU Docker image to this cloudbuild yaml file. We
use this file to create our Docker images:

```
gcloud builds submit --config \
util/cloudbuild/cloudbuild_create_images.yaml
```

The GCN-GPU docker image can be obtained at:
https://gcr.io/gem5-test/gcn-gpu

Change-Id: I7564db78a9f00507f5acc6cf6098de35f98b6fb1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33595
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Update starter_fs.py for latest Arm FS binaries.

Updated the default kernel and root device names to match the latest
Arm full-system binaries available for download on the gem5 website.

Also added a command line option to allow the root device to be
specified as an optional command line argument.

Change-Id: I27f90ffaf0f4b35c5dcc4c22ac2fbd34f8a040a4
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/30814
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Fix coding style in addressTranslation methods

armFault -> arm_fault

Change-Id: I6263b105f8757b34dd15a06b16abe7289073614d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33434
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Check if PAC is implemented before executing insts

If Armv8.3-PAuth (PAC) extension is not supported, most instrucions
will trigger an Undefined Instruction fault; except for a group of
them living in the HINT space; those should be treated as NOP.

Change-Id: Idec920ed15e0310ec9132a3cb3701cdb7e7cf9d1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33455
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Introduce HavePACExt helper

This will check for presence of pointer authentication extension.
According to the reference manual, Pointer authentication is
implemented if the value of at least one of

ID_AA64ISAR1_EL1.{APA, API, GPA, GPI}

is not 0b0000.

Change-Id: I4e98e65758e8edc953794e5b618d2c6c3f6000ae
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33454
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add support for introspecting scalar stats

This change adds a wrapper for the ScalarInfo stat type to enable
introspection of scalar stats from Python. Due to the slightly
confusing use of proxy objects in the stat system, PyBind11 fails to
automatically cast to the right wrapper type. This is worked around in
the by explicitly casting to the relevant type's Python wrapper.

To make the interface more Python-friendly, this change also changes
the semantics of resolveStat to raise an exception if the stat can't
be found.

Change-Id: If1fc6fe238fc9d69d4e22369a4988a06407d2f7c
Signed-off-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33176
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Use a docker image to build gem5.

This will give us control over what tools and packages are in the image,
instead of relying on what is provided on the kokoro build machines.

Change-Id: I9a9cdedfca4d2e9f31b3e918e01bc660e4d23f64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33647
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: Factor the page size out of the decode cache.

There isn't anything special about using the page size, and it creates
an artificial dependence on the ISA. Instead of being based on pages,
the cache is now based on "chunks" who's size is a template parameter.
It defaults to 4K which is a common page size, but it can be tuned
arbitrarily if necessary.

Some unnecessary includes have been trimmed out as well.

Change-Id: I9fe59a5668d702433a800884fbfbdce20e0ade97
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33204
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Clean up usage of arch/isa_traits.hh.

isa_traits.hh used to have much more in it, but now it only has
PageShift, PageBytes, and (for now) the guest endianness. These values
should only be retrieved from the System class generally speaking, so
only the system class should include arch/isa_traits.hh.

Some gpu compute related files need PageBytes or PageShift. Even though
those files don't advertise their ISA dependence, they are tied to x86.
In those files, they can include arch/x86/isa_traits.hh.

The only other file which legitimately needs arch/isa_traits.hh is the
decoder cache since it uses PageBytes to size an array.

Change-Id: I12686368715623e3140a68a7027c136bd52567b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33203
Reviewed-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Minor cleanup in isa_traits.hh.

Remove unnecessary includes, and an unnecessary/unimplemented function
prototype.

Change-Id: I2230c1ec62734d918f0f6af6f4c1e1a64f25f812
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33201
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv: Fix disassembling of jalr

The 'jalr' instruction of 'format Jump' should have an immediate as
offset, and the Rd register could not be always omitted. This patch
fixes the problem.

Example output:
  jalr ra, -168(ra)
  jalr zero, 0(ra)
  jalr ra, 0(a5)

Note that this does not apply to the other two instructions of the
same format: 'c.jr' and 'c.jalr'.

Change-Id: Ia656c2e8bfafd243bfec221ac291190a84684929
Signed-off-by: Ian Jiang <ianjiang.ict@gmail.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33155
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

riscv: Remove unnecessary includes from arch/riscv/isa_traits.hh.

Change-Id: Iff3e840c5b67fa23ebead337abf323e7add2e6db
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33200
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Tidy up isa_traits.hh and delete the VAddr class.

The VAddr class wasn't used and was just a copy (with style fixes) of
the Alpha version.

Delete unused constants in isa_traits.hh, and remove unnecessary
includes. Replace MachineBytes with sizeof(uint32_t) in
arch/power/process.cc.

Change-Id: Ia4862448c43b2dd07078b1ebbbbfda4636343730
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33199
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-gcn3: Update LmReqsInPipe in atomic flats when execMask=0

In flat instructions, wrLmReqsInPipe/rdLmReqsInPipe are decremented
in the calcAddr() function. However, the calcAddr() function is only
called when execMask != 0.

This patch adds in statements to decrement wrLmReqsInPipe and
rdLmReqsInPipe in all implemented atomic flats when execMask is 0.

This fixes a scenario where vector local memory and flat instructions
are unable to execute due to LocalMemPipeline::isLMReqFIFOWrRdy
always returning false in ScheduleStage::dispatchReady after too many
atomic flats execute with execMask = 0

Change-Id: I081cfd3faf74bbfcf0728445e7160fa2a76a6a7e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32614
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Explicitly decode/encode in utf-8.

The default encoding for python 2 is ascii which can't handle some
characters in, for instance, people's names which have accented letters.
This change explicitly selects the utf-8 encoding which pacifies python
and is mostly equivalent except in these rare cases.

In python 3, the default encoding is utf-8 to begin with, and it's no
longer possible to change it. In this case, explicitly selecting the
encoding is redundant but harmless.

When we support only python 3, then this change can be reverted.

Thanks to Lakin Smith for proposing a related solution and pointing out
some information that led to this one.

Change-Id: I99bd59063c77edd712954ffe90d7de320ade49ea
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33575
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Lakin Smith <lakindsmith@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

gpu-compute: Create CU's ports in the standard way

The CU would initialize its ports in getMasterPort(), which
is not desirable as getMasterPort() may be called several
times for the same port. This can lead to a fatal if the CU
expects to only create a single port of a given type, and may
lead to other issues where stat names are duplicated.

This change instantiates and initializes the CU's ports in the
CU constructor using the CU params.

The index field is also removed from the CU's ports because the
base class already has an ID field, which will be set to the
default value in the base class's constructor for scalar ports.

It doesn't make sense for scalar port's to take an index because
they are scalar, so we let the base class initialize the ID to
the invalid port ID.

Change-Id: Id18386f5f53800a6447d968380676d8fd9bac9df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32836
Reviewed-by: Anthony Gutierrez <anthony.gutierrez@amd.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc: Send response to TLM side if a packet does not need response

A completed TLM transaction includes request and response parts.
Currently, if a gem5 packet does not need a reponse, the bridge would not
send BEGIN_RESP to its upstream. It causes stuck on TLM side.

To fix this problem, the bridge should send BEGIN_RESP by itself in this
case.

Change-Id: I318dec21bc3f291693715c0d70bc624addf05076
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32735
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Fix up the selectFunc syscall to work with g++ 10.2.

This is no longer willing to implicitly cast between the locally defined
Linux::fd_set type and the system fd_set type. That's pretty reasonable
since those types are really independent of one another, and we
shouldn't be using them interchangeably in the first place. That's a
pre-existing condition though, and I just want to get the existing code
to compile for now.

Change-Id: I41d5f3695dfe5f0e406d074d31d13c6e3282df64
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33415
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

systemc,sim: Update port terminology

Change-Id: Iaeafe94245e383fcb1146c99c893fd56fe9bb636
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32316
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev: Update port terminology

Change-Id: I48bd6718471f034f7c3226279efe7ada0d9c81e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32315
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Update port terminology

Change-Id: Ib4fc8cad7139d4971e74930295a69e576f6da3cf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32314
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

gpu-compute: update port terminology

Change-Id: I3121c4afb1e137aebe09c1d694e9484844d02b9b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32313
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Poremba <chesp3@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu: update port terminology

Change-Id: I891e7a74683c1775c75a62454fcfdecb7511b7e9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32312
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arch: update port terminology

Change-Id: Ifcf90534d8e5ff5fc68538ec87dc541517ea404d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32311
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

learning-gem5: update port terminology

Change-Id: I0ca705cf93396b5c34a0ac4dce30411c5c866733
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32310
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Updated port classes & refs to remove slaveBind()/UnBind()

Change-Id: I9106397b8816d8148dd916510bbcf65ed499d303
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32309
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Deprecate SlavePort and MasterPort classes

After this change, if you use these classes or inherit from these
classes, the compiler will now give you a warning that these names are
deprecated. Instead, you should use ResponsePort and RequestPort,
respectively.

This patch simply deprecates these names. The following patches will
convert all of the code in gem5 to use these new names. The first step
is converting the class names and the uses of these classes, then we
will update the variable names to be more precise as well.

Change-Id: I5e6e90b2916df4dbfccdaabe97423f377a1f6e3f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32308
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Add DeprecatedParam type

There are times when we need to change the name of parameter, but this
breaks the external-facing python API used in configuration files. Using
this "type" for a parameter will warn users that they are using the old
name, but allow for backwards compatibility.

Declaring a SimObject parameter of type `DeprecatedParam` allows the
python configuration files to use the old name transparently. This
leverages some of the SimObject magic to remember the names of
deprecated parameters and the DeprecatedParam object stores the
"translation" from old name to new name.

This has been tested with Ports, "normal" parameters, and SimObject
parameters. It has not been tested with checkpointing as there are no
checkpointing tests in gem5 right now. The testing was manually adding
some deprecated params and checking that config scripts still run
correctly that use the old, deprecated, variables.

Change-Id: I0465a748c08a24278d6b1a9d9ee1bcd67baa5b13
Signed-off-by: Jason Lowe-Power <jason@lowepower.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/31954
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Rewrite addressTranslation to use BitUnions

Change-Id: I48877d026213a0dec8b8f96deef59bdbc9a40564
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33356
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Remove deadcode from AArch64 address translation

There's no need to check for CPSR.WIDTH: if the 64 bit version
of the AT instruction/register is used, it means we are already
in AArch64 execution mode

Change-Id: I1263dcfd04e791eb390199546c177a926c71c6d5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-arm: Refactor Address Translation (AT) code

* Removed the nested switch
* Replace warn with warn_once as it's polluting the stdout

Change-Id: Iafbf43b68b7c3382cfcd1884305f8393bc63f981
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33354
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: ignore 32-bit arm dual linux boot tests

As mentioned on the JIRA issue, uncacheable requests done after
cacheable requests had been done to the address make the cache writeback
and write trash data to memory.

We believe that the kernel must be doing earlier invalidation by set and
way earlier on to prevent this, but that is not implemented in gem5 yet.

The problem can be worked around by booting in atomic without caches and
checkpointing after init, because uncacheable accesses are only done on
early stages of CPU bringup, which is the more common use case anyways.

The aarch64 Linux kernel developers have stated that set and way
invalidates are not going to be used in aarch64, which further reduces the
importance of implementing this immediatly

JIRA: https://gem5.atlassian.net/browse/GEM5-640
Change-Id: Ieba31e707dcc09693d7a87ed9d51c3d1ffa3abe0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33015
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

python: Use six's with_metaclass instead of it's add_metaclass.

The decorator creates two versions of a class, adding it to the Params
dict multiple times which generates an annoying warning. Alternatively,
the with_metaclass mechanism sets up an alternative base class which
does not create the extra class and doesn't generate the warning.

It may be the case that this generates extra classes which just don't
lead to a warning? Or in other words, would we then have Params types
with weird, internal names generated by six? Hopefully not, but that may
be preferable to the annoying warnings, especially when running tests
which run gem5 many times.

Change-Id: I9395cde3fc95126c0a0c4db67fc5b0c6bf2dd9ed
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33276
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Clear out isa_traits.hh.

Remove unused constants, move the interrupt related constants to
arch/arm/interrupts.hh, move a paging related constant to
arch/arm/pagetable.hh, and get rid of unnecessary includes.

Change-Id: Ide219f7a8515e010c1dd029db2ef22d8f614d8a1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33198
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Get rid of (some) unused VAddr types.

X86 actually defines and uses a VAddr bitunion, but the ARM, MIPS and
SPARC versions are just stubs and aren't used anywhere.

Change-Id: Iea8d0c8ab04ac1d95f49458f0fc41f291751da1a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33202
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>

util: Fix interworking for the thumb version of the m5 util.

Make sure the m5 op call sight is marked as thumb, and also use an
interworking branch to return from it.

Change-Id: I4f6ec6a0e9e7ff76fc8f256fec9ec410a9959189
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27748
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>

util: Enable neon when building arm/thumb versions of the m5 util.

Apparently the presence of a hardware FPU is no longer implied by
-march=armv7-a (or armv7 I assume), and so adding -mfpu=neon is
necessary when using hardware floating point in gcc/g++.

Change-Id: I59c5b58933fae2e4e5a747b2af128b801acc812e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27747
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

util: Add a unit test for the "inst" call type in the m5 util.

This test does two things. First, it makes sure that the "inst" call
type detects that it's being requested in the command line arguments
correctly.

Second, it detects whether it's running in gem5 or not, really just
detecting an environment variable which tells it whether it is. If it
is, then it attempts to run the "sum" op which it expects to succeed and
give the right answer.

If not, it expects to get a SIGILL signal from the OS when it tries to
execute the otherwise illegal instruction. It sets up a signal handler
to catch it, and in that handler saves off information about what
happened. It then uses siglongjmp to return to sanity (before the
signal) and to examine what happened to see if the right instruction was
attempted.

It looks like, depending on the architecture, Linux will either set
si_code to ILL_ILLOPC (illegal opcode) or ILL_ILLOPN (illegal operand).
The later doesn't seem right since the entire instruction is illegal,
not just some operand, but it is what it is and we need to handle
either.

The test then calls a small function, abi_verify, which takes the
siginfo_t and does any abi specific verification. That includes
extracting fields from the instruction if the instruction trigger the
signal, or checking for architecture specific constants, etc.

Also, to centralize setting the macro which lets a call type know that
it's the default, the call types are now also responsible for setting up
their own tweaks to the environment.

Change-Id: I8710e39e20bd9c03b1375a2dccefb27bd6fe0c10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27689
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

test,arch-riscv: Removed the RISCV Insttests

These tests verify RISCV instructions. This is already one by the
asmtests:
https://gem5.googlesource.com/public/gem5/+/refs/heads/develop/tests/gem5/asmtest/tests.py

The asmtests do this better.

Furthermore, the insttests have some bugs associated with them, which
would require some engineering effort fix:
https://gem5.atlassian.net/browse/GEM5-729
https://gem5.atlassian.net/browse/GEM5-748
https://gem5.atlassian.net/browse/GEM5-749

This patch removes the RISCV insttests.

Change-Id: I9ee3c88d06778823f655ef9222071beb57c6c995
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33147
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-cache: Create Compressor namespace

Creation of the Compressor namespace. It encapsulates all the cache
compressors, and other classes used by them.

The following classes have been renamed:
BaseCacheCompressor -> Base
PerfectCompressor - Perfect
RepeatedQwordsCompressor -> RepeatedQwords
ZeroCompressor -> Zero

BaseDictionaryCompressor and DictionaryCompressor were not renamed
because the there is a high probability that users may want to
create a Dictionary class that encompasses the dictionary contained
by these compressors.

To apply this patch one must force recompilation (e.g., by deleting
it) of build/<arch>/params/BaseCache.hh (and any other files that
were previously using these compressors).

Change-Id: I78cb3b6fb8e3e50a52a04268e0e08dd664d81230
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33294
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mips: Remove unused or misplaced values from isa_traits.hh.

Most of these values were unused, except the interrupt levels which were
moved to the interrupt controller, the only place they were used.
Unnecessary includes were also removed.

Change-Id: I783966413d51391663a9217ed672ec1f2b4719b7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33197
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,cpu,sim: Get rid of the microcode ROM stub code.

This code, including a switching header file, is no longer necessary
because ROM based microops are now handled by the decoder itself.

Change-Id: Ie3ea4a7371dec22993ede80e2acd1df7cd1ecf59
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32899
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu,arch: Delegate fetching ROM microops to the decoder.

In most cases, the microcode ROM doesn't actually do anything. The
structural existence of a microcode ROM doesn't make sense in the
general case, and in architectures that know they have one and need to
interact with it, they can cast their decoder into an arch specific type
and access the ROM that way.

Change-Id: I25b67bfe65df1fdb84eb5bc894cfcb83da1ce64b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32898
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Use default initializers to simplify the decoder constructor.

Change-Id: I76f1fe9a58a26f26c204cb0b9bab050a22d289c9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32895
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Remove unnecessary includes from isa_traits.hh.

These includes are not used in this header file, and if they're needed
by other source it should include them directly.

Change-Id: I7d17d7c7fcc1020d85f1257059d2c2057b0c461d
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33196
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Style fixes in the base Fault classes.

Change-Id: Iff8588aba929b3909ca1b5ec0e494acb8f838543
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33280
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

x86: Style fixes in x86's fault implementations.

Change-Id: I320877a7e753eae5ffba2421e6dfe23b52352664
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33279
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

x86: Replace "is not" with "!=" in fpop.isa.

Some variables were being compared against some constants with "is not",
which is not correct since it will compare for identity rather than
equivalence. There was a long standing build warning from this, but it
wasn't clear where the error was coming from since it was in python
interpreted from a string in the ISA description.

This change replaces "is not" in those two places with "!=".

Change-Id: I0c4d038af6e047ffd79f8171713e8e998e840e3b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33283
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

misc: Replace some includes of arch/isa_traits.hh.

In sim/vma.hh, the include was indirectly getting the definition of
DPRINTF. It was replaced with an include of base/trace.hh which actually
provides that definition.

In the indirect branch predictor, it was being used to get the
definition of TheISA::PCState. This should come from arch/types.hh
instead.

Change-Id: I6de08f196499c85b54edde09d654902cc766c2eb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/33195
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Added .txt file extension to txt files

This is a small improvement. In our Jenkins, https://jenkins.gem5.org,
we archive the `compile-test-out` directory. Opening these `*.stderr`
and `*.stdout` files through the Jenkins interface was problematic. The
`.txt` extension makes these files easier to open.

Change-Id: I4026efec2118179eaed775c7560510cd16f349a6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32154
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Added exit code to the compiler tests

This testing script should return a non-exit code when one of the
compilations fail.

Change-Id: Ie15bc5779372dd31d784eaffdee4b04abb9a1b11
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32097
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

util,tests: Removed GCC 4.8 from compilers tests

We are going to remove support of GCC 4
(https://gem5.atlassian.net/browse/GEM5-218) as part of the gem5 20.1
release.

Change-Id: Ie44b553d35f48118d24b96eba564a927fefdb985
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32096
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-riscv, arch-x86: convert tlb to new style stats

Change-Id: Ie2754d861a658fde0acdda30cbcb91e02029e33a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32835
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-mips, arch-power: removed unused stats

Change-Id: Ic44943eaefab027d6dc665e531f827202b353093
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32834
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86,cpu: Fix bpred by annotating branch instructions in x86

Original Creator: Adria Armejach.

Branch instructions needed to be annotated in x86 as direct/indirect and conditional/unconditional. These annotations where not present causing the branch predictor to misbehave, not using the BTB. In addition, logic to determine the real branch target at decode needed to be added as it was also missing.

Change-Id: I91e707452c1825b9bb4ae75c3f599da489ae5b9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/29154
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removed m5threads tests from .testignore

This commit fixes many problems which were resulting in these tests
not executing correctly. However, the m5thread tests are still failing
with an `fatal:syscall set_tid_address (#166) unimplemented` error,
recorded here: https://gem5.atlassian.net/browse/GEM5-747.

The tests have been removed from .testignore as part of our goal of
removing all tests from the .testignore file:
https://gem5.atlassian.net/browse/GEM5-361

Change-Id: I287d1e126963114a791d7f3aa563a037a89b2cb7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32916
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Added tests/gem5/resources to .gitignore

This is simply a directory used by testlib to store downloaded
resources. It should therefore be ignored.

Change-Id: Iede2234dc512b3bc8bdcccfaef0b14d56dee0a27
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/32915
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>