Gabe Black [Thu, 12 Jun 2008 04:48:15 +0000 (00:48 -0400)]
X86: Make string instructions work when rcx=0.
Gabe Black [Thu, 12 Jun 2008 04:48:02 +0000 (00:48 -0400)]
X86: Have all 8 machine check registers since the kernel assumes they're there.
Gabe Black [Thu, 12 Jun 2008 04:47:25 +0000 (00:47 -0400)]
X86: Bypass unaligned access support for register addressed MSRs.
Gabe Black [Thu, 12 Jun 2008 04:46:22 +0000 (00:46 -0400)]
X86: Remove enforcement of APIC register access alignment. Panic if more than one register is accessed at a time.
Gabe Black [Thu, 12 Jun 2008 04:46:16 +0000 (00:46 -0400)]
X86: Force the kernel to use a certain loops per jiffy instead of calculating it.
Gabe Black [Thu, 12 Jun 2008 04:46:04 +0000 (00:46 -0400)]
X86: Fix the implementation of BSF.
Gabe Black [Thu, 12 Jun 2008 04:45:52 +0000 (00:45 -0400)]
X86: Bit scan forward/reverse were accidentally transposed.
Gabe Black [Thu, 12 Jun 2008 04:45:22 +0000 (00:45 -0400)]
X86: Fix a byte register indexing issue in the sign extending move from memory microcode.
Gabe Black [Thu, 12 Jun 2008 04:45:11 +0000 (00:45 -0400)]
X86: Make the amount of system memory match the hardcoded e820 info.
Gabe Black [Thu, 12 Jun 2008 04:45:01 +0000 (00:45 -0400)]
X86: Make the regular console use the serial port as well.
Gabe Black [Thu, 12 Jun 2008 04:42:52 +0000 (00:42 -0400)]
X86: Update the regressions for the fact that rdtsc does something now.
Gabe Black [Thu, 12 Jun 2008 04:39:10 +0000 (00:39 -0400)]
X86: Add in some support for the tsc register.
Gabe Black [Thu, 12 Jun 2008 04:35:50 +0000 (00:35 -0400)]
CPU: Make the simple cpu trace data for loads/stores.
Ali Saidi [Wed, 11 Jun 2008 14:54:12 +0000 (10:54 -0400)]
X86: Fix building on *BSD hosts
Ali Saidi [Wed, 11 Jun 2008 14:54:08 +0000 (10:54 -0400)]
SCons: Fix more SCons version issues
Nathan Binkert [Wed, 11 Jun 2008 13:50:37 +0000 (09:50 -0400)]
Added tag copyright_update for changeset
60a931b03fb1
Ali Saidi [Tue, 20 May 2008 20:06:56 +0000 (16:06 -0400)]
IGbE: Implement sending packet that is contained in more than 2 descriptors.
--HG--
extra : convert_revision :
8fb7d5fad5cb840f69c31aa8b331dbe09e46ee9d
Stephen Hines [Tue, 20 May 2008 18:04:53 +0000 (14:04 -0400)]
SCons: Fixing SCons bug 2006 issues for non-alpha ISAs
--HG--
extra : convert_revision :
26e3edef06d6f82aaf162825c151d18faadd6e72
Ali Saidi [Thu, 15 May 2008 23:10:26 +0000 (19:10 -0400)]
Make sure that output files are always checked success before they're used.
Make OutputDirectory::resolve() private and change the functions using
resolve() to instead use create().
--HG--
extra : convert_revision :
36d4be629764d0c4c708cec8aa712cd15f966453
Ali Saidi [Tue, 6 May 2008 20:22:14 +0000 (16:22 -0400)]
SCons: More scons fixing for SCons bug 2006
--HG--
extra : convert_revision :
d3656ab1e3c18251d4bcf6f5a31103d4b2dfdc43
Ali Saidi [Thu, 10 Apr 2008 19:38:10 +0000 (15:38 -0400)]
SCons: add comments to SConscript documenting bug workaround
--HG--
extra : convert_revision :
e6cdffe953d56b96c76c7ff14d2dcc3de3ccfcc3
Ali Saidi [Thu, 10 Apr 2008 18:44:52 +0000 (14:44 -0400)]
PhysicalMemory: Add parameter for variance in memory delay.
--HG--
extra : convert_revision :
b931472e81dedb650b7accb9061cb426f1c32e66
Ali Saidi [Tue, 8 Apr 2008 15:08:26 +0000 (11:08 -0400)]
SCons: Manually specifying header only directories with Dir() works around the problem
--HG--
extra : convert_revision :
d9713228d934cf4a45114a972603b8bca2bd27d3
Ali Saidi [Tue, 8 Apr 2008 03:40:24 +0000 (23:40 -0400)]
SCons: Make BATCH options global sticky so libelf is built appropriately.
--HG--
extra : convert_revision :
4bca5c31b8421305d41aac072696964b39d7ff16
Ali Saidi [Tue, 8 Apr 2008 03:40:23 +0000 (23:40 -0400)]
SCons: Add check for SCons version since the latest are broken.
--HG--
extra : convert_revision :
bb0ea1221214e4e34d4223e345956c3febce3dc9
Ali Saidi [Tue, 25 Mar 2008 19:58:54 +0000 (15:58 -0400)]
IGbE: Fix bug that limits wire performance a bit
--HG--
extra : convert_revision :
3f93c17f647a6955dab861da211174de856ee02c
Steve Reinhardt [Tue, 25 Mar 2008 14:04:52 +0000 (10:04 -0400)]
Automated merge with ssh://daystrom.m5sim.org//repo/m5
--HG--
extra : convert_revision :
7922848bb1145bcb2ee07d672d21cfe2dd98fc03
Steve Reinhardt [Tue, 25 Mar 2008 14:01:21 +0000 (10:01 -0400)]
Fix handling of writeback-induced writebacks in atomic mode.
--HG--
extra : convert_revision :
4fa64f8a929f1aa36a9d5a71b8d1816b497aca4c
Gabe Black [Tue, 25 Mar 2008 06:15:23 +0000 (02:15 -0400)]
X86: Put an RTC into the CMOS part of the southbridge.
--HG--
extra : convert_revision :
a614373236fe75db6e6181fc152a02b541a131f3
Gabe Black [Tue, 25 Mar 2008 06:15:06 +0000 (02:15 -0400)]
Devices: Separate out the MC146818 RTC so both Alpha and X86 can use it.
--HG--
extra : convert_revision :
1e7f5185654ed0845678c2169c702d3b977159ed
Gabe Black [Tue, 25 Mar 2008 06:09:18 +0000 (02:09 -0400)]
X86: Turn #defines into consts.
--HG--
extra : convert_revision :
c0416de5d88ca39f54494418768e68a93aa4f2aa
Gabe Black [Tue, 25 Mar 2008 06:08:54 +0000 (02:08 -0400)]
X86: Start implementing the south bridge stuff.
--HG--
extra : convert_revision :
92918c05eb3363155d78889bdab17baa8eae9dca
Gabe Black [Tue, 25 Mar 2008 06:06:53 +0000 (02:06 -0400)]
X86: Change the Opteron platform to be the PC platform.
--HG--
extra : convert_revision :
2c6ffebbad04a21cef6ba3fbc1803218908a6c37
Steve Reinhardt [Mon, 24 Mar 2008 05:08:02 +0000 (01:08 -0400)]
Delete the Request for a no-response Packet
when the Packet is deleted, since the requester
can't possibly do it.
--HG--
extra : convert_revision :
8571b144ecb3c70efc06d09faa8b3161fb58352d
Steve Reinhardt [Mon, 24 Mar 2008 05:08:02 +0000 (01:08 -0400)]
Don't FastAlloc MSHRs since we don't allocate them on the fly.
--HG--
extra : convert_revision :
02775cfb460afe6df0df0938c62cccd93a71e775
Steve Reinhardt [Mon, 24 Mar 2008 05:08:02 +0000 (01:08 -0400)]
Add FAST_ALLOC_DEBUG and FAST_ALLOC_STATS as SConstruct options.
--HG--
extra : convert_revision :
56a7f646f2ac87019c78ba7fa62c5f4bdc00ba44
Steve Reinhardt [Sun, 23 Mar 2008 02:17:15 +0000 (22:17 -0400)]
Fix cache problem with writes to tempBlock
getting wrong writeback address.
--HG--
extra : convert_revision :
023dfb69c227c13a69bfe2744c6af75a45828b0b
Gabe Black [Thu, 20 Mar 2008 06:10:21 +0000 (02:10 -0400)]
MIPS: Check endianness of binaries in SE mode.
--HG--
extra : convert_revision :
e6c4bda6078eb68a26f8834411f744078c6bf5a9
Steve Reinhardt [Tue, 18 Mar 2008 03:07:22 +0000 (23:07 -0400)]
Update long regression stats for semi-recent cache changes.
--HG--
extra : convert_revision :
7fef1e4f684ced37479ed363ebbb3a7485bc0d52
Steve Reinhardt [Mon, 17 Mar 2008 07:08:28 +0000 (03:08 -0400)]
Fix a few Packet memory leaks.
--HG--
extra : convert_revision :
00db19f0698c0786f0dff561eea9217860a5a05a
Steve Reinhardt [Mon, 17 Mar 2008 07:07:38 +0000 (03:07 -0400)]
Restructure bus timing calcs to cope with pkt being deleted by target.
--HG--
extra : convert_revision :
db8497e73a44f2a06aab121e797e88b4c0c31330
Steve Reinhardt [Sat, 15 Mar 2008 12:03:55 +0000 (05:03 -0700)]
Fix subtle cache bug where read could return stale data
if a prior write miss arrived while an even earlier
read miss was still outstanding.
--HG--
extra : convert_revision :
4924e145829b2ecf4610b88d33f4773510c6801a
Ali Saidi [Sun, 16 Mar 2008 02:20:09 +0000 (22:20 -0400)]
Simpoints: Fix regression bug/Don't set process.simpoint, if simpoint doesn't exist
--HG--
extra : convert_revision :
c156c49668815755c4c788f807e8eba32151aa24
Gabe Black [Fri, 7 Mar 2008 02:09:15 +0000 (21:09 -0500)]
Merge
--HG--
extra : convert_revision :
ec5f41b2007ade15f6f4c4a1533e50f9cba2798e
Gabe Black [Fri, 7 Mar 2008 01:37:28 +0000 (20:37 -0500)]
X86: Refine the local APIC.
--HG--
extra : convert_revision :
2789c54ed555fed2f2a333fcc7dc6454f294ebf2
Vilas Sridharan [Thu, 6 Mar 2008 05:27:09 +0000 (00:27 -0500)]
O3CPU: Don't call dumpInsts if DEBUG is not defined
--HG--
extra : convert_revision :
3194bde4c624d118969bfbf92282539963a72245
Gabe Black [Sat, 1 Mar 2008 05:05:12 +0000 (00:05 -0500)]
X86: Don't map the local APIC into the physical address space in SE mode.
--HG--
extra : convert_revision :
b7103974b12130bbf43583c4cb5294b808add208
Ali Saidi [Fri, 29 Feb 2008 23:08:49 +0000 (18:08 -0500)]
Added tag m5_2.0_beta4 for changeset
cad8c2b5d2ec
--HG--
extra : convert_revision :
3012e3c0393b8fd2f83e3532172269a27c0bbb04
Ali Saidi [Fri, 29 Feb 2008 22:59:45 +0000 (17:59 -0500)]
Added tag m5_2.0_beta5 for changeset
fb826c79a385
--HG--
extra : convert_revision :
13e2a028aaf899e2f314e6053266168b274e20fd
Lisa Hsu [Fri, 29 Feb 2008 06:49:36 +0000 (01:49 -0500)]
Error out if -s is used without --caches (instead of saying you must specify a
CPU).
--HG--
extra : convert_revision :
a3b2bfbe7e037146ac08dd08834bf255da692506
Ali Saidi [Fri, 29 Feb 2008 06:23:18 +0000 (01:23 -0500)]
Configs: Make sure options don't conflict
--HG--
extra : convert_revision :
dc9b91cf1d8e33c5e68d7faeb45dbe3e7038d14c
Ali Saidi [Fri, 29 Feb 2008 01:39:01 +0000 (20:39 -0500)]
Configs: Fix some bugs we introduced in the simpoints code
--HG--
extra : convert_revision :
ef22c11cb3242903a484fc05dc0f96d3e5f9af72
Steve Reinhardt [Wed, 27 Feb 2008 23:18:56 +0000 (18:18 -0500)]
Automated merge with ssh://daystrom.m5sim.org//repo/m5
--HG--
extra : convert_revision :
f4bcd342e7abb86ca83840b723e6ab0b861ecf5b
Steve Reinhardt [Wed, 27 Feb 2008 23:17:37 +0000 (18:17 -0500)]
Update outputs for quick tests to reflect fixed cache stats.
Will update long tests later.
--HG--
extra : convert_revision :
79f66b5761a574f0c8049c1c771c353b42942993
Korey Sewell [Wed, 27 Feb 2008 22:50:29 +0000 (17:50 -0500)]
Add comments in code to describe bug conditions.
This should help if somebody gets to the bug
fix before me (or someone else)...
--HG--
extra : convert_revision :
0ae64c58ef4f7b02996f31e9e9e6bfad344719e2
Korey Sewell [Wed, 27 Feb 2008 21:53:08 +0000 (16:53 -0500)]
Fix Load/Store Queue squashing after a SMT thread is removed but ensuring
you are squashing from the current instruction # causing the thread exit.
--HG--
extra : convert_revision :
ccbeece7dd1d5fee43f30ab19370908972113473
Korey Sewell [Wed, 27 Feb 2008 21:48:33 +0000 (16:48 -0500)]
Fix offset in removeThread() function so that float registers start freeing up
from the right point (#32 usually) instead of restarting at 0 and double-freeing.
Commented out assert line in free_list.hh that will check for when double-free condition
goes bad.
--HG--
extra : convert_revision :
08d5f9b6a874736e487d101e85c22aaa67bf59ae
Steve Reinhardt [Wed, 27 Feb 2008 06:03:28 +0000 (22:03 -0800)]
Revamp cache timing access mshr check to make stats sane again.
--HG--
extra : convert_revision :
37009b8ee536807073b5a5ca07ed1d097a496aea
Rick Strong [Wed, 27 Feb 2008 05:35:09 +0000 (00:35 -0500)]
Configs: Make using Simpoints easier with some config files that support them easily
--HG--
extra : convert_revision :
0f21829306eb68b332f03da410e6c341c8595bdd
Gabe Black [Wed, 27 Feb 2008 04:39:53 +0000 (23:39 -0500)]
X86: Put in initial implementation of the local APIC.
--HG--
extra : convert_revision :
1708a93d96b819e64ed456c75dbb5325ac8114a8
Gabe Black [Wed, 27 Feb 2008 04:39:22 +0000 (23:39 -0500)]
X86: Implement the INVLPG instruction and the TIA microop.
--HG--
extra : convert_revision :
31db1ee082f6c3ca5443cba1eb335e408661ead2
Gabe Black [Wed, 27 Feb 2008 04:38:51 +0000 (23:38 -0500)]
TLB: Make a TLB base class and put a virtual demapPage function in it.
--HG--
extra : convert_revision :
cc0e62a5a337fd5bf332ad33bed61c0d505a936f
Gabe Black [Wed, 27 Feb 2008 04:38:01 +0000 (23:38 -0500)]
X86: Get PCI config space to work, and adjust address space prefix numbering scheme.
--HG--
extra : convert_revision :
2b382f478ee8cde3a35aa4c105196f200bc7afa6
Steve Reinhardt [Wed, 27 Feb 2008 04:17:26 +0000 (20:17 -0800)]
Cache: better comments particularly regarding writeback situation.
--HG--
extra : convert_revision :
59ff9ee63ee0fec5a7dfc27b485b737455ccf362
Ali Saidi [Tue, 26 Feb 2008 22:28:31 +0000 (17:28 -0500)]
Update make release, README, and RELEASE_NOTES for b5
--HG--
extra : convert_revision :
a4958e934f599bff24b251507da7c266c89430fc
Gabe Black [Tue, 26 Feb 2008 07:20:40 +0000 (02:20 -0500)]
Bus: Update the stats for the recent bus fix.
--HG--
extra : convert_revision :
dc29f7b5e6fa30a50305193cb0e5aed942f7e407
Gabe Black [Tue, 26 Feb 2008 07:20:08 +0000 (02:20 -0500)]
Bus: Fix the bus timing to be more realistic.
--HG--
extra : convert_revision :
acd70dc98ab840e55b114706fbb6afb2a95e54bc
Vilas Sridharan [Fri, 22 Feb 2008 22:48:10 +0000 (17:48 -0500)]
add instruction count fast forwaing and max instruction options
--HG--
extra : convert_revision :
8fe45e512229cdc3e0dcd23e3e5c54516c445d0f
Stephen Hines [Tue, 19 Feb 2008 21:42:32 +0000 (16:42 -0500)]
Added ARM_SE as a build option.
--HG--
extra : convert_revision :
905e3acfa58bd14f8101e29dadc0de71d23a79cc
Steve Reinhardt [Sat, 16 Feb 2008 19:58:37 +0000 (14:58 -0500)]
Update stats for new writeback behavior.
--HG--
extra : convert_revision :
3e932b5773f5fb9a119822d5bf497f61e9409c14
Steve Reinhardt [Sat, 16 Feb 2008 19:58:03 +0000 (14:58 -0500)]
Make L2+ caches allocate new block for writeback misses
instead of forwarding down the line.
--HG--
extra : convert_revision :
b0d6e7862c92ea7a2d21f817d30398735e7bb8ba
Steve Reinhardt [Sat, 16 Feb 2008 18:53:12 +0000 (13:53 -0500)]
Update stats for some unknown minor x86 changes
(assuming someone just forgot to do this... tsk tsk).
--HG--
extra : convert_revision :
303d7bbf5e2c892d5f4498a9de2e2b82496ccd0e
Ali Saidi [Thu, 14 Feb 2008 21:14:35 +0000 (16:14 -0500)]
CPU: move the PC Events code to a place where the code won't be executed multiple times if an instruction faults.
--HG--
extra : convert_revision :
19c8e46a4eea206517be7ed4131ab9df0fe00e68
Ali Saidi [Thu, 14 Feb 2008 21:13:50 +0000 (16:13 -0500)]
Configs: Change Simulation.py to return a subclass of the CPU models rather than the original class. Without this changes elsewhere in the config script (e.g. the DriveSys frequency can change the TestSys frequency.
--HG--
extra : convert_revision :
f972207c616590a60a6e103daa5de469cf124b44
Ali Saidi [Mon, 11 Feb 2008 17:35:28 +0000 (12:35 -0500)]
Update copyright dates
--HG--
extra : convert_revision :
547e7ddff6b8005a9eaad60970bc51984e84fcd1
Steve Reinhardt [Mon, 11 Feb 2008 16:31:26 +0000 (08:31 -0800)]
Automated merge with file:/home/stever/hg/m5-orig
--HG--
extra : convert_revision :
86a55cd98a9704f756a70aa0cbd2820cf92c821d
Steve Reinhardt [Mon, 11 Feb 2008 16:04:01 +0000 (08:04 -0800)]
EXTRAS now points to src instead of needing 'src' subdir.
--HG--
extra : convert_revision :
8e7e4516ace8c7852eeea3c479bfd567839a8061
Steve Reinhardt [Mon, 11 Feb 2008 15:47:44 +0000 (07:47 -0800)]
Wait to set BUILD_DIR until *after* env is copied.
--HG--
extra : convert_revision :
03153e7aaa1fb2a435900eab08a98ec1a6ce62db
Nicolas Zea [Mon, 11 Feb 2008 00:41:03 +0000 (19:41 -0500)]
Bus: Only update port cache when there is an item to update it with.
--HG--
extra : convert_revision :
84848fd48bb9e6693a0518c862364142b1969aa8
Ali Saidi [Mon, 11 Feb 2008 00:32:12 +0000 (19:32 -0500)]
IGbE: Fix a couple of bugs.
--HG--
extra : convert_revision :
a1f16bd82b6fbd5b6b5dc0f08b9e69858bea86ca
Steve Reinhardt [Sun, 10 Feb 2008 22:45:25 +0000 (14:45 -0800)]
Fix #include lines for renamed cache files.
--HG--
extra : convert_revision :
b5008115dc5b34958246608757e69a3fa43b85c5
Steve Reinhardt [Sun, 10 Feb 2008 22:15:42 +0000 (14:15 -0800)]
Rename cache files for brevity and consistency with rest of tree.
--HG--
rename : src/mem/cache/base_cache.cc => src/mem/cache/base.cc
rename : src/mem/cache/base_cache.hh => src/mem/cache/base.hh
rename : src/mem/cache/cache_blk.cc => src/mem/cache/blk.cc
rename : src/mem/cache/cache_blk.hh => src/mem/cache/blk.hh
rename : src/mem/cache/cache_builder.cc => src/mem/cache/builder.cc
rename : src/mem/cache/miss/mshr.cc => src/mem/cache/mshr.cc
rename : src/mem/cache/miss/mshr.hh => src/mem/cache/mshr.hh
rename : src/mem/cache/miss/mshr_queue.cc => src/mem/cache/mshr_queue.cc
rename : src/mem/cache/miss/mshr_queue.hh => src/mem/cache/mshr_queue.hh
rename : src/mem/cache/prefetch/base_prefetcher.cc => src/mem/cache/prefetch/base.cc
rename : src/mem/cache/prefetch/base_prefetcher.hh => src/mem/cache/prefetch/base.hh
rename : src/mem/cache/prefetch/ghb_prefetcher.cc => src/mem/cache/prefetch/ghb.cc
rename : src/mem/cache/prefetch/ghb_prefetcher.hh => src/mem/cache/prefetch/ghb.hh
rename : src/mem/cache/prefetch/stride_prefetcher.cc => src/mem/cache/prefetch/stride.cc
rename : src/mem/cache/prefetch/stride_prefetcher.hh => src/mem/cache/prefetch/stride.hh
rename : src/mem/cache/prefetch/tagged_prefetcher.cc => src/mem/cache/prefetch/tagged.cc
rename : src/mem/cache/prefetch/tagged_prefetcher.hh => src/mem/cache/prefetch/tagged.hh
rename : src/mem/cache/tags/base_tags.cc => src/mem/cache/tags/base.cc
rename : src/mem/cache/tags/base_tags.hh => src/mem/cache/tags/base.hh
rename : src/mem/cache/tags/Repl.py => src/mem/cache/tags/iic_repl/Repl.py
rename : src/mem/cache/tags/repl/gen.cc => src/mem/cache/tags/iic_repl/gen.cc
rename : src/mem/cache/tags/repl/gen.hh => src/mem/cache/tags/iic_repl/gen.hh
rename : src/mem/cache/tags/repl/repl.hh => src/mem/cache/tags/iic_repl/repl.hh
extra : convert_revision :
ff7a35cc155a8d80317563c45cebe405984eac62
Stephen Hines [Wed, 6 Feb 2008 21:32:40 +0000 (16:32 -0500)]
Make the Event::description() a const function
--HG--
extra : convert_revision :
c7768d54d3f78685e93920069f5485083ca989c0
Stephen Hines [Wed, 6 Feb 2008 04:44:13 +0000 (23:44 -0500)]
Add base ARM code to M5
--HG--
extra : convert_revision :
d811bf87d1a0bfc712942ecd3db1b48fc75257af
Steve Reinhardt [Wed, 6 Feb 2008 01:43:45 +0000 (17:43 -0800)]
Cleaned up os.path imports a bit.
--HG--
extra : convert_revision :
ee75bf9abd249ab053e804739cc50972475cd5b6
Steve Reinhardt [Wed, 6 Feb 2008 01:40:08 +0000 (17:40 -0800)]
Make EXTRAS work for SConsopts too.
Requires pushing source files down into 'src' subdir relative
to directory listed in EXTRAS.
--HG--
extra : convert_revision :
ca04adc3e24c60bd3e7b63ca5770b31333d76729
Gabe Black [Wed, 23 Jan 2008 20:28:54 +0000 (15:28 -0500)]
X86: Put an SMBios/DMI table in memory.
This is basically just the header right now, but there's an untested
mechanism in place to fill out the table and make sure everything is
updated correctly.
--HG--
extra : convert_revision :
c1610c0dfa211b7e0d091a04133695d84f500a1c
Gabe Black [Wed, 23 Jan 2008 13:18:27 +0000 (08:18 -0500)]
X86: Optomize the bit scanning instruction microassembly a little. More can be done.
--HG--
extra : convert_revision :
3cf6e972f0e41e3529a633ecbb31289e1bd17f0f
Gabe Black [Tue, 22 Jan 2008 05:10:33 +0000 (00:10 -0500)]
X86: Implement and attach the BSR and BSF instructions.
--HG--
extra : convert_revision :
be7e11980092e5d1baff0e05d4ec910305966908
Gabe Black [Mon, 21 Jan 2008 21:27:40 +0000 (16:27 -0500)]
X86: Fill out group17 in the decoder.
--HG--
extra : convert_revision :
66ab9c0fc3086f66e3d6d82d47964ecf406c3a8a
Gabe Black [Mon, 21 Jan 2008 09:32:34 +0000 (04:32 -0500)]
X86: Use the existing boot_osflags instead of duplicating it.
--HG--
extra : convert_revision :
e04e438d7d261a61c52b946c23cd126ed648814a
Ali Saidi [Wed, 16 Jan 2008 16:11:55 +0000 (11:11 -0500)]
Update long o3 regressions for o3 change in previous changeset
--HG--
extra : convert_revision :
00242105076eb4466cce21038858f2b9d20b2fe2
Steve Reinhardt [Tue, 15 Jan 2008 18:13:08 +0000 (13:13 -0500)]
Update O3 ref outputs: very minor stats change due to previous cset.
(from Steve on behalf of m5test).
--HG--
extra : convert_revision :
696efdaa3dd7680dfc9c797a6a46a5053238c7d2
Ke Meng [Mon, 14 Jan 2008 16:47:32 +0000 (11:47 -0500)]
The reason is that the event is supposed to put the instructions ready to execute for next cycle. And the FUCompletion event has a lower priority than CPU tick event. It is called after the iew->tick() for current cycle has already been executed and the issueToExecuteQueue has already advanced this time. And assume the issueToExecuteLatency is 1, to catch up, the increasement should be made at access(-1) instead of access(0). Otherwise I found it could increase the actual op_latency of the instructions to execute by 1 cycle and potentially put the simulated CPU into a permanent idle state.
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
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extra : convert_revision :
dafc16814383e8e8f8320845edf6ab2bcfed1e1d
Gabe Black [Sat, 12 Jan 2008 11:41:32 +0000 (06:41 -0500)]
X86: Redo the bit test instructions.
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433c2a9f3675ed02f3be5ce759a440f2686d2ccd
Gabe Black [Sat, 12 Jan 2008 11:40:55 +0000 (06:40 -0500)]
X86: Fix the wrmsr instruction.
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12bc7e71226ebafb8eedadf6a3db82929e15e722
Gabe Black [Sat, 12 Jan 2008 11:40:10 +0000 (06:40 -0500)]
X86: Make the effective segment base shadow the regular one, not the selector.
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498c7c16d664c784b196885b1f35c3c6386c9cfc
Gabe Black [Sat, 12 Jan 2008 11:39:15 +0000 (06:39 -0500)]
X86: Make the IO ports work using extra physical address lines. Add a serial port.
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a14cb4fc9afedfc0ff58b11a7f8fb5516d462cc6
Gabe Black [Sat, 12 Jan 2008 11:37:35 +0000 (06:37 -0500)]
X86: Fix the general IO instructions dataSize.
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9774a52cb6a8e7632d1b1dc0706e5791cc18d238
Geoffrey Blake [Sun, 6 Jan 2008 05:19:45 +0000 (00:19 -0500)]
Temporary fix for ll/sc bug see flyspray task for more info:
http://www.m5sim.org/flyspray/task/197
Signed-off by: Ali Saidi <saidi@eecs.umich.edu>
--HG--
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cdeece7e3163de9abf2c6c7435f1bc93570fab81