radv: calculate non-draw related ia_multi_vgt_param bits in pipeline

This moves a bunch of non-draw dependent calcs into the pipeline code,
to reduce CPU overheads in the draw path.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: move calculating primgroup_size to pipeline.

This moves this out of the draw paths.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: only calculate num_prims when required.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: use upload_data to upload push descriptors.

This is just a reusing code.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: realign vgt flush on hawaii workaround with radeonsi.

This realigns this code with the radeonsi version and fixes
the indirect case to work properly.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: return an error code when resetting a command buffer

If the upload BO allocation failed.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: remove unnecessary goto in radv_create_cmd_buffer()

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: do not pass a pipeline object to radv_emit_graphics_pipeline()

To be consistent with radv_emit_compute_pipeline().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>

radv: add debug flags to zero vram allocations.

We are seeing apps that sometimes rely on Windows behaviour, add
a flag to rule out vram zeroing.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: optimize TCS epilog when invocation 0 writes tess factors

This removes the barrier and LDS stores and loads for tess factors
when it's possible. The removal of the barrier seems more important
to me though.

In one shader, it removes 17 * 4 bytes from the shader binary.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

tgsi/scan: add a new pass that analyzes tess factor writes (v2)

The pass tries to deduce whether tess factors are always written by
all shader invocations.

The implication for radeonsi is that it doesn't have to use a barrier
near the end of TCS, and doesn't have to use LDS for passing the tess
factors to the epilog.

v2: Handle barriers and do the analysis pass for each code segment
    surrounded by barriers separately, and AND results from all
    such segments writing tess factors. The change is trivial in the main
    switch statement.

    Also, the result is renamed to "tessfactors_are_def_in_all_invocs"
    to make the name accurate.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

intel: Remove unused Kabylake pci id

I missed this one in Mesa commit ebc5ccf.

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>

Android: Add LLVM support for Android P

The Android version in AOSP master has changed now to P, so we need to add
LLVM flags for it. Duplicating the lines because I expect the version will
get bumped at some point and diverge from O.

Cc: Chih-Wei Huang <cwhuang@android-x86.org>
Signed-off-by: Rob Herring <robh@kernel.org>

Android: fix undeclared identifier 'gfx9d_reg_table'

Since commit 552aaa11 the compiler complains:

external/mesa/src/amd/common/ac_debug.c:124:51: error: use of undeclared identifier 'gfx9d_reg_table'; did you mean 'sid_reg_table'?
                reg = find_register(gfx9d_reg_table, ARRAY_SIZE(gfx9d_reg_table), offset);
                                                                ^~~~~~~~~~~~~~~
                                                                sid_reg_table

It's because the commit ef97cc0c ("radeonsi/gfx9: add IB parser support")
add gfx9d.h as a recipe of sid_tables.h. But the corresponding Android.mk
was not updated. However, it's not spotted since gfx9d_reg_table is not
really used until commit 552aaa11 was landed.

Fixes: 552aaa11 (ac/debug: take ASIC generation into account when printing registers)
Signed-off-by: Chih-Wei Huang <cwhuang@linux.org.tw>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>

winsys/amdgpu: use the new raw CS API

This also cleans things up.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: implement pipe_context::fence_server_sync

This will be more useful once we have sync_file support.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: factor out some fence dependency code into separate functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: rename fence_dependency functions

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

gallium/radeon: add a proper fail path for calloc in r600_flush_from_st

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: don't allow interprocess resource sharing for IBs

Now we should get IB submissions with bo_list == NULL when DRI buffers
aren't referenced.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: fix interprocess resource sharing on Raven

This kinda fragiile, but it at least unbreaks the driver.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

st/glsl_to_tgsi: only the first (inner-most) array reference can be a 2D index

Don't get distracted by record dereferences between array references.

Fixes dEQP-GLES31.functional.tessellation.user_defined_io.per_vertex_block.*

Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

nir/spirv: fix chain access with different index bit sizes

Currently we support 32-bit indexes/offsets all over the driver, so we
convert them to that bit size.

Fixes dEQP-VK.spirv_assembly.instruction.*.indexing.*

v2: Use u2u32 instead (Jason).

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

r600: handle the non-TXF_LZ support path.

it appears that texcoord.z/w will be 0 in all cases already,
so just put them into the vbo always.

Signed-off-by: Dave Airlie <airlied@redhat.com>

gallium/u_blitter: use UTIL_BLITTER_ATTRIB_NONE (0) instead of 0 directly

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_blitter: don't pass GENERIC in VS if it's not needed

Now, depth-only clears and custom passes don't read memory in VS.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_blitter: use draw_rectangle for all blits except cubemaps

Add ZW coordinates to the draw_rectangle callback and use it.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_blitter: use draw_rectangle callback for layered clears

They are done with instancing.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/u_blitter: add new union blitter_attrib to replace pipe_color_union

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Tested-by: Brian Paul <brianp@vmware.com>

gallium/radeon: use rectangles for 1D and 2D texture blits

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

i965/tex: add missing include

src/mesa/drivers/dri/i965/intel_tex.h:52:40: warning: ‘enum intel_miptree_create_flags’ declared inside parameter list will not be visible outside of this definition or declaration
                 enum intel_miptree_create_flags flags);
                      ^~~~~~~~~~~~~~~~~~~~~~~~~~

Fixes: cadcd89278edcda8aba2 "i965/tex: Change the flags type on
                             create_for_teximage"
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>

radv: Actually check for vm faults.

The code can check for vm faults having happened. If we only do it
on a hang we don't know when the faults happened. This changes the
behavior to when the first VM faults is found, even without a hang.

Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>

llvmpipe, draw: improve shader cache debugging

With GALLIVM_DEBUG=perf set, output the relevant stats for shader cache usage
whenever we have to evict shader variants.
Also add some output when shaders are deleted (but not with the perf setting
to keep this one less noisy).
While here, also don't delete that many shaders when we have to evict. For fs,
there's potentially some cost if we have to evict due to the required flush,
however certainly shader recompiles have a high cost too so I don't think
evicting one quarter of the cache size makes sense (and, if we're evicting
based on IR count, we probably typically evict only very few or just one
shader too). For vs, I'm not sure it even makes sense to evict more than
one shader at a time, but keep the logic the same for now.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Reviewed-by: Brian Paul <brianp@vmware.com>

llvmpipe: enable PIPE_CAP_QUERY_PIPELINE_STATISTICS

This was implemented since forever, but not enabled.
It passes all piglit tests except one, arb_pipeline_statistics_query-frag.
The reason is that the test (for drawing a 10x10 rect) expects between
100 and 150 pixel shader invocations. But since llvmpipe counts this with
4x4 granularity (and due to the rect being 2 tris) we end up with 224
invocations. I believe however what llvmpipe is doing violates neither the
spirit nor the letter of the spec (our fragment shader granularity really
is 4x4 pixels, albeit we will bail out early on 2x2 or 4x2 (the latter
if AVX is available) granularity), the spec allows to count additional
invocations due to implementation reasons.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

gallivm: fix gather implementation a bit

gather is defined in terms of bilinear filtering, just without the filtering
part. However, there's actually some subtle differences required in our
implementation, because we use some tricks to simplify coord wrapping for the
two coords per direction.
For bilinear filtering, we don't care if we end up with an incorrect
texel, as long as the filter weight is 0.0 for it. Likewise, the order of
the texels doesn't actually matter (as long as they still have the correct
filter weight).
But for gather, these tricks lead to incorrect results.
Fix this for CLAMP_TO_EDGE, and add some comments to the other wrap functions
which look broken (the 3 mirror_clamp plus mirror_repeat) (too complex to fix
right now, and noone really seems to care...).

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

docs: update calendar, add news item and link release notes for 17.1.9

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add sha256 checksums for 17.1.9

Signed-off-by: Andres Gomez <agomez@igalia.com>

docs: add release notes for 17.1.9

Signed-off-by: Andres Gomez <agomez@igalia.com>

mesa: whitespace, formatting fixes in teximage.c

Reviewed-by: Eric Anholt <eric@anholt.net>

mesa: provide more info in some texture image error messages

Reviewed-by: Eric Anholt <eric@anholt.net>

svga: abort shader translation upon indirect indexing of temporaries

This patch aborts shader translation upon indirect indexing of temporary
register on non-vgpu10 device. This prevents non-supported feature
sending to the device.

Tested wth MTT-piglit, glretrace.

Reviewed-by: Brian Paul <brianp@vmware.com>

radv: keep track of the disasm string in debug mode only

This will allow to dump the active shaders when a hang is
detected. Only the ASM will be dumped for now.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add shader_variant_create() helper function

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: drop 'dump' parameters from some shader related functions

The device object contains the debug flags.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: move shaders related code to radv_shader.c

Reduce size of radv_pipeline.c and improve code isolation. More
code can probably moved but it's a start.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: fix error code when initializing the push descriptors

malloc() failures are unrelated to the device memory.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: do not update vertex descriptors if the allocation failed

A return code error is stored in the command buffer and should
be returned to the user via EndCommandBuffer().

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: add radv_vertex_elements_info data structure

In my opinion, this improves code readability.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

gallium/tests: use ARRAY_SIZE macro

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

r300: use ARRAY_SIZE macro

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>

glx: use ARRAY_SIZE macro

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Jon Turney <jon.turney@dronecode.org.uk>

radv: add an assertion when pushing meta descriptor sets

Just to make sure we are using the set 0, because it's the
only one which is saved/restored when doing meta operations.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa/st: Fix frontbuffer rendering regression

This fixes a regression introduced with commit
"mesa/st: Reduce the number of frontbuffer flush calls"
where we, after flushing the front buffer marked it as not-rendered-to,
the idea being that it should be marked as "rendered-to" again as soon as
any rendering was touching the front.

Now the latter part never happened, because it was part of a state
validation and we never marked that part of the state as dirty.

So mark the framebuffer state dirty after a frontbuffer flush.
(fdo bugzilla 102496)

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102496
Fixes: eceb671002 (mesa/st: Reduce the number of frontbuffer flush calls)
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Bruce Cherniak <bruce.cherniak@intel.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Tested-by: Bruce Cherniak <bruce.cherniak@intel.com>
Tested-By: Gert Wollny <gw.fossdev@gmail.com>

i965: Don't special case the batchbuffer when reference counting.

We don't need to special case the batch - when we add the batch to the
validation list, we can simply increase the refcount to 2, and when we
make a new batch, we'll drop it back down to 1 (when unreferencing all
buffers in the validation list).  The final reference is still held by
brw->batch.bo, as it was before.

This removes the special case from a bunch of loops.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>

ac: remove bitcast_to_float()

ac_to_float() does a superset of what it does.

Signed-off-by: Dave Airlie <airlied@redhat.com>

ac: move ac_to_integer() and ac_to_float() to ac_llvm_build.c

We'll need to use ac_to_integer() for other stuff in ac_llvm_build.c.

Reviewed-by: Dave Airlie <airlied@redhat.com>

ac: fix ac_get_type_size() for doubles

Reviewed-by: Dave Airlie <airlied@redhat.com>

radv/ac: use ac_get_type_size.

Just moved to newly shared code.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: move the guts of ARB_shader_group_vote emission to ac

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: move si_emit_ballot() to ac

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: move emit_optimization_barrier() to ac

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radeonsi: move llvm_get_type_size() to ac

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/winsys: fix flags vs va_flags thinko.

Fixes: e8d57802f (radv/gfx9: allocate events from uncached VA space)
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: use simpler indirect packet 3 if possible.

This fixes some observed hangs on CIK GPUs.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/gfx9: allocate events from uncached VA space

This copies what amdgpu-pro does, and allocates the memory
for an event with an uncached mtype.

This fixes hangs with:
dEQP-VK.api.command_buffers.record_simul_use_primary

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

radv/winsys: use amdgpu_bo_va_op_raw.

This is a precursor to the gfx9 fix to use uncached for the event
memory. Move to the interface which allows setting the flags,
but wrap it to avoid having to copy it around the place.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>

Revert "st/va: add enviromental variable to disable interlace"

This reverts commit 10dec2de2d9f568675d66d736b48701fa26f7b50.

The environment variable is no longer needed with the previous change

Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: move YUV content to deinterlaced buffer when reallocated for encoder

v2: use deinterlace common function
v3: make sure deinterlace only

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/va: reallocate the buffer if the layout isn't supported

So that it makes more clear for buffer reallocation based
on buffers layout for both decoder and encoder.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl/compositor: make vl_compositor_set_yuv_layer() static

Since it's no longer being called outside of compositor

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

st/omx: use vl/compositor helper function for YUV deinterlacing

v2: separate helper function in different patch

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

vl/compositor: make a helper function for YUV deinterlacing

The similar function is in OMX, and only used by OMX. Now have it
moved to vl/compositor for other state tracker to use later.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>

ac/surface: add radeon_surf::has_stencil for convenience

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st/tests: Fix regressions with libunwind enabled introduced with 7be6d8fe12

Add the according flags to link with libunwind.

Fixes: https://bugs.freedesktop.org/show_bug.cgi?id=102565
Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/st/tests: Fix classic build regressions introduced with 7be6d8fe12

Fixes the build in classic only mode, i.e. the new state tracker tests are
only build when Gallium is enabled.

Tested-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

mesa/main: Fix GetTransformFeedbacki64 for glTransformFeedbackBufferBase

The spec has special rules for querying buffer offsets and sizes
when BindBufferBase is used, described  in the OpenGL 4.6 spec,
section 6.8 Buffer Object State:

   "To query the starting offset or size of the range of a buffer
    object binding in an indexed array, call GetInteger64i_v with
    target set to respectively the starting offset or binding size
    name from table 6.5 for that array. Index must be in the range
    zero to the number of bind points supported minus one. If the
    starting offset or size was not specified when the buffer object
    was bound (e.g. if it was bound with BindBufferBase), or if no
    buffer object is bound to the target array at index, zero is
    returned."

Transform feedback buffer queries should follow the same rules, since
it is the same case for them. There is a CTS test for this.

Fixes:
KHR-GL45.direct_state_access.xfb_buffers

Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>

radeonsi: don't read tcs_out_lds_layout.patch_stride from an SGPR

Same as before, writing TCS outputs to LDS is rare.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't read tcs_out_lds_layout.vertex_size from an SGPR

TCS outputs are usually not written to LDS, so no stats here.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi/gfx9: don't read LS out vertex stride from an SGPR in monolithic HS

-44 bytes in a monolithic LS-HS binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't read the LS output vertex stride from an SGPR in LS

Now it's able to generate ds_write2_b64 instead of ds_write2_b32.

-20 bytes in one shader binary. (having only 1 output)

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't read the number of TCS out vertices from an SGPR in TCS

-16 bytes in one shader binary.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: don't always apply the PrimID instancing bug workaround on SI

It looks like commit 391673af7ad1565a5f6ac8fc2f8c9fcdd1fe9908 that should
have fixed the perf regression didn't really change much if anything.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

radeonsi: remove 2 callbacks from si_shader_context

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

winsys/amdgpu: disable local BOs on Raven

It hangs with a high degree of reproducibility.

Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

disk_cache: make the thread queue resizable and low priority

Acked-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

loader/dri3: Make sure we invalidate a drawable on size change

If we're seeing a drawable size change, in particular after processing a
configure notify event, make sure we invalidate so that the state tracker
picks up the new geometry.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

loader/dri3: Process event after each fence wait

This tries to mimic dri2 behaviour where events are typically processed
while waiting for X replies. Since, during steady-state dri3 rendering, we
seldom wait for xcb replies, and haven't enabled any automatic event
processing, instead check for events after a fence wait.

Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

st/mesa: skip draw calls with pipe_draw_info::count == 0

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102502

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Tested-by: Alexandre Demers <alexandre.f.demers@gmail.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Timothy Arceri <tarceri@itsqueeze.com>

docs: update envvar docs to reflect MESA_NO_ERROR change

I changed the behaviour earlier today, but forgot to update the
corresponding docs.

Fixes: 77713a0acb09f475d29f "mesa: allow user to set MESA_NO_ERROR=0"
Suggested-by: Emil Velikov <emil.l.velikov@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>

radv: do not use a bitfield when dirtying the vertex buffers

Useless to track which one has been updated because we
re-upload all the vertex buffers in one shot.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

radv: remove unused radv_meta_saved_state::vertex_saved field

It's always false.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>

mesa: allow user to set MESA_NO_ERROR=0

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102530
Cc: Michel Dänzer <michel@daenzer.net>
Cc: Alexandre Demers <alexandre.f.demers@gmail.com>
Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>

util: rename include guard to avoid clash

src/mesa/main/debug.h uses the same include guard.

Signed-off-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>

llvmpipe, tgsi: hook up dx10 gather4 opcode

Trivial. We already support tg4 for legacy tex opcodes, so the actual
texture sampling code already handles it.
(Just like TG4, we don't handle additional capabilities and always sample
red channel.)

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

llvmpipe, draw: increase shader cache limits

We're not particularly concerned with memory usage, if the tradeoff is
shader recompiles. And it's common for apps to have a lot of shaders
nowadays (and, since our shaders include a LOT of context state of course
we may create quite a bit more shaders even).
So quadruple the amount of shaders draw will cache (from 128 to 512).
For llvmpipe (fs shaders) quadruple the number of instructions, keep the
number of variants the same for now (only with very simple, non-texturing
shaders the variant limit could really be reached), and simplify the
definition, it's probably easier to just have one different definition
per branch...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>

ac/surface: reduce gfx9_surface_layout size.

152->144.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_amdgpu_winsys struct size.

1168->1160.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_image struct size.

1480->1472.

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_shader_variant struct size.

544->536

Signed-off-by: Dave Airlie <airlied@redhat.com>

radv: reduce radv_cmd_state struct size.

1632->1624.

Signed-off-by: Dave Airlie <airlied@redhat.com>