yosys.git
4 years agoRevert "write_xaiger: only instantiate each whitebox cell type once"
David Shah [Fri, 27 Dec 2019 23:25:20 +0000 (23:25 +0000)]
Revert "write_xaiger: only instantiate each whitebox cell type once"

4 years agofixed invalid char
Miodrag Milanovic [Wed, 25 Dec 2019 19:38:48 +0000 (20:38 +0100)]
fixed invalid char

4 years agoiopadmap: Emit tristate buffers with const OE for some edge cases.
Marcin Kościelnicki [Sun, 22 Dec 2019 00:08:56 +0000 (01:08 +0100)]
iopadmap: Emit tristate buffers with const OE for some edge cases.

4 years agoMerge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen
Marcin Kościelnicki [Wed, 25 Dec 2019 15:18:44 +0000 (16:18 +0100)]
Merge pull request #1593 from YosysHQ/mwk/dsp48a1-pmgen

xilinx_dsp: Initial DSP48A/DSP48A1 support.

4 years agoMinor nit fixes
Marcin Kościelnicki [Wed, 25 Dec 2019 14:39:40 +0000 (15:39 +0100)]
Minor nit fixes

4 years agoAdd DSP cascade tests
Eddie Hung [Mon, 23 Dec 2019 22:58:06 +0000 (14:58 -0800)]
Add DSP cascade tests

4 years agoFix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too
Eddie Hung [Mon, 23 Dec 2019 22:40:59 +0000 (14:40 -0800)]
Fix OPMODE for PCIN->PCOUT cascades in xc6s, check B[01]REG too

4 years agoFix CEA/CEB check
Eddie Hung [Mon, 23 Dec 2019 22:22:13 +0000 (14:22 -0800)]
Fix CEA/CEB check

4 years agoFix checking CE[AB] and for direct connections
Eddie Hung [Mon, 23 Dec 2019 21:41:26 +0000 (13:41 -0800)]
Fix checking CE[AB] and for direct connections

4 years agoSupport unregistered cascades for A and B inputs
Eddie Hung [Mon, 23 Dec 2019 20:38:18 +0000 (12:38 -0800)]
Support unregistered cascades for A and B inputs

4 years agoAdd DSP48A* PCOUT -> PCIN cascade support
Eddie Hung [Mon, 23 Dec 2019 19:42:46 +0000 (11:42 -0800)]
Add DSP48A* PCOUT -> PCIN cascade support

4 years agoxilinx: Test our DSP48A/DSP48A1 simulation models.
Marcin Kościelnicki [Sun, 22 Dec 2019 14:30:04 +0000 (14:30 +0000)]
xilinx: Test our DSP48A/DSP48A1 simulation models.

4 years agoxilinx_dsp: Initial DSP48A/DSP48A1 support.
Marcin Kościelnicki [Sun, 22 Dec 2019 19:43:39 +0000 (20:43 +0100)]
xilinx_dsp: Initial DSP48A/DSP48A1 support.

4 years agoMerge pull request #1588 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung [Fri, 20 Dec 2019 22:56:08 +0000 (14:56 -0800)]
Merge pull request #1588 from YosysHQ/eddie/xaiger_cleanup

write_xaiger: only instantiate each whitebox cell type once

4 years agoAdd abc9_arrival times for RAM{32,64}M
Eddie Hung [Fri, 20 Dec 2019 22:06:59 +0000 (14:06 -0800)]
Add abc9_arrival times for RAM{32,64}M

4 years agoAdd RAM{32,64}M to abc9_map.v
Eddie Hung [Thu, 19 Dec 2019 19:24:39 +0000 (11:24 -0800)]
Add RAM{32,64}M to abc9_map.v

4 years agoPut specify/endspecify inside ``
Eddie Hung [Fri, 20 Dec 2019 21:38:32 +0000 (13:38 -0800)]
Put specify/endspecify inside ``

4 years agoMerge pull request #1585 from YosysHQ/eddie/fix_abc9_lut
Eddie Hung [Fri, 20 Dec 2019 21:09:00 +0000 (13:09 -0800)]
Merge pull request #1585 from YosysHQ/eddie/fix_abc9_lut

Interpret "abc9 -lut" as lut string only if [0-9:]

4 years agowrite_xaiger: only instantiate each whitebox cell type once
Eddie Hung [Fri, 20 Dec 2019 21:07:24 +0000 (13:07 -0800)]
write_xaiger: only instantiate each whitebox cell type once

4 years agoMerge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup
Eddie Hung [Fri, 20 Dec 2019 21:03:48 +0000 (13:03 -0800)]
Merge pull request #1587 from YosysHQ/revert-1558-eddie/xaiger_cleanup

Revert "Optimise write_xaiger"

4 years agoRevert "Optimise write_xaiger"
Eddie Hung [Fri, 20 Dec 2019 20:05:45 +0000 (12:05 -0800)]
Revert "Optimise write_xaiger"

4 years agoFix linking with Python 3.8
Graham Edgecombe [Tue, 19 Nov 2019 19:46:15 +0000 (19:46 +0000)]
Fix linking with Python 3.8

The behaviour of python-config --libs has changed in Python 3.8.

For example, compare the output of it with Python 3.7 and 3.8 on an
ArchLinux system:

    $ python3.7-config --libs
    -lpython3.7m -lcrypt -lpthread -ldl  -lutil -lm
    $ python3.8-config --libs
    -lcrypt -lpthread -ldl  -lutil -lm -lm
    $

The lack of -lpython in the latter case causes the linker to fail when
attempting to build Yosys against Python 3.8.

Passing the new --embed flag to python-config adds -lpython, just like
earlier versions of Python:

    $ python3.8-config --embed --libs
    -lpython3.8 -lcrypt -lpthread -ldl  -lutil -lm -lm
    $

This commit adds code for automatically detecting support for the
--embed flag. If it is supported, it is passed to all python-config
invocations. This fixes building against Python 3.8.

4 years agoAdd PYTHON_CONFIG variable to the Makefile
Graham Edgecombe [Tue, 19 Nov 2019 19:45:59 +0000 (19:45 +0000)]
Add PYTHON_CONFIG variable to the Makefile

4 years agoMerge pull request #1581 from YosysHQ/clifford/fix1565
Eddie Hung [Thu, 19 Dec 2019 17:24:27 +0000 (12:24 -0500)]
Merge pull request #1581 from YosysHQ/clifford/fix1565

Fix sim for assignments with lhs<rhs size

4 years agoMerge pull request #1558 from YosysHQ/eddie/xaiger_cleanup
Eddie Hung [Thu, 19 Dec 2019 17:24:03 +0000 (12:24 -0500)]
Merge pull request #1558 from YosysHQ/eddie/xaiger_cleanup

Optimise write_xaiger

4 years agoMerge pull request #1569 from YosysHQ/eddie/fix_1531
Eddie Hung [Thu, 19 Dec 2019 17:21:33 +0000 (12:21 -0500)]
Merge pull request #1569 from YosysHQ/eddie/fix_1531

verilog: preserve size of $genval$-s in for loops

4 years agoMerge pull request #1571 from YosysHQ/eddie/fix_1570
Eddie Hung [Thu, 19 Dec 2019 17:21:22 +0000 (12:21 -0500)]
Merge pull request #1571 from YosysHQ/eddie/fix_1570

mem_arst.v: do not redeclare ANSI port

4 years agoxilinx: Add simulation models for remaining CLB primitives.
Marcin Kościelnicki [Wed, 27 Nov 2019 17:13:00 +0000 (18:13 +0100)]
xilinx: Add simulation models for remaining CLB primitives.

4 years agoxilinx_dffopt: Keep order of LUT inputs.
Marcin Kościelnicki [Thu, 19 Dec 2019 07:49:21 +0000 (08:49 +0100)]
xilinx_dffopt: Keep order of LUT inputs.

See rationale at https://github.com/YosysHQ/yosys/pull/1557#discussion_r359196549

4 years agoInterpret "abc9 -lut" as lut string only if [0-9:]
Eddie Hung [Wed, 18 Dec 2019 20:21:12 +0000 (12:21 -0800)]
Interpret "abc9 -lut" as lut string only if [0-9:]

4 years agoAdd "scratchpad" to CHANGELOG
Eddie Hung [Wed, 18 Dec 2019 20:09:11 +0000 (12:09 -0800)]
Add "scratchpad" to CHANGELOG

4 years agoMerge branch 'master' of github.com:YosysHQ/yosys
Eddie Hung [Wed, 18 Dec 2019 20:08:38 +0000 (12:08 -0800)]
Merge branch 'master' of github.com:YosysHQ/yosys

4 years agoMerge pull request #1563 from YosysHQ/dave/async-prld
David Shah [Wed, 18 Dec 2019 19:42:17 +0000 (19:42 +0000)]
Merge pull request #1563 from YosysHQ/dave/async-prld

ecp5: Add support for mapping PRLD FFs

4 years agoMerge pull request #1572 from nakengelhardt/scratchpad_pass
Eddie Hung [Wed, 18 Dec 2019 18:55:44 +0000 (13:55 -0500)]
Merge pull request #1572 from nakengelhardt/scratchpad_pass

add a command to read/modify scratchpad contents

4 years agoMerge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test
Eddie Hung [Wed, 18 Dec 2019 17:53:45 +0000 (12:53 -0500)]
Merge pull request #1584 from YosysHQ/mwk/xilinx-flaky-test

tests/xilinx: fix flaky mux test

4 years agotests/xilinx: fix flaky mux test
Marcin Kościelnicki [Wed, 18 Dec 2019 14:53:20 +0000 (15:53 +0100)]
tests/xilinx: fix flaky mux test

4 years agoxilinx: Add xilinx_dffopt pass (#1557)
Marcin Kościelnicki [Wed, 18 Dec 2019 12:42:26 +0000 (13:42 +0100)]
xilinx: Add xilinx_dffopt pass (#1557)

4 years agoxilinx: Improve flip-flop handling.
Marcin Kościelnicki [Thu, 21 Nov 2019 05:30:06 +0000 (06:30 +0100)]
xilinx: Improve flip-flop handling.

This adds support for infering more kinds of flip-flops:

- FFs with async set/reset and clock enable
- FFs with sync set/reset
- FFs with sync set/reset and clock enable

Some passes have been moved (and some added) in order for dff2dffs to
work correctly.

This gives us complete coverage of Virtex 6+ and Spartan 6 flip-flop
capabilities (though not latch capabilities).  Older FPGAs also support
having both a set and a reset input, which will be handled at a later
data.

4 years agoSend people to symbioticeda.com instead of verific.com
Clifford Wolf [Wed, 18 Dec 2019 12:06:34 +0000 (13:06 +0100)]
Send people to symbioticeda.com instead of verific.com

Signed-off-by: Clifford Wolf <clifford@clifford.at>
4 years agouse extra_args
N. Engelhardt [Wed, 18 Dec 2019 11:30:30 +0000 (12:30 +0100)]
use extra_args

4 years agoFix sim for assignments with lhs<rhs size, fixes #1565
Clifford Wolf [Tue, 17 Dec 2019 16:32:48 +0000 (17:32 +0100)]
Fix sim for assignments with lhs<rhs size, fixes #1565

Signed-off-by: Clifford Wolf <clifford@clifford.at>
4 years agoCleanup
Eddie Hung [Tue, 17 Dec 2019 08:25:08 +0000 (00:25 -0800)]
Cleanup

4 years agoMerge pull request #1574 from YosysHQ/eddie/xilinx_lutram
Eddie Hung [Tue, 17 Dec 2019 05:48:21 +0000 (21:48 -0800)]
Merge pull request #1574 from YosysHQ/eddie/xilinx_lutram

xilinx: add LUTRAM rules for RAM32M, RAM64M

4 years agoMerge pull request #1521 from dh73/diego/memattr
Eddie Hung [Tue, 17 Dec 2019 05:48:02 +0000 (21:48 -0800)]
Merge pull request #1521 from dh73/diego/memattr

Adding support for Xilinx memory attribute 'block' in single port mode.

4 years agoEnforce non-existence
Eddie Hung [Tue, 17 Dec 2019 01:06:30 +0000 (17:06 -0800)]
Enforce non-existence

4 years agoUpdate doc
Eddie Hung [Mon, 16 Dec 2019 22:48:53 +0000 (14:48 -0800)]
Update doc

4 years agoAdd another test
Eddie Hung [Mon, 16 Dec 2019 21:57:55 +0000 (13:57 -0800)]
Add another test

4 years agoMore sloppiness, thanks @dh73 for spotting
Eddie Hung [Mon, 16 Dec 2019 21:56:45 +0000 (13:56 -0800)]
More sloppiness, thanks @dh73 for spotting

4 years agoAccidentally commented out tests
Eddie Hung [Mon, 16 Dec 2019 21:31:47 +0000 (13:31 -0800)]
Accidentally commented out tests

4 years agoAdd unconditional match blocks for force RAM
Eddie Hung [Mon, 16 Dec 2019 21:31:15 +0000 (13:31 -0800)]
Add unconditional match blocks for force RAM

4 years agoOops
Eddie Hung [Mon, 16 Dec 2019 21:31:05 +0000 (13:31 -0800)]
Oops

4 years agoMerge blockram tests
Eddie Hung [Mon, 16 Dec 2019 21:01:51 +0000 (13:01 -0800)]
Merge blockram tests

4 years agoUpdate xc7/xcu bram rules
Eddie Hung [Mon, 16 Dec 2019 21:00:58 +0000 (13:00 -0800)]
Update xc7/xcu bram rules

4 years agoImplement 'attributes' grammar
Eddie Hung [Mon, 16 Dec 2019 20:58:13 +0000 (12:58 -0800)]
Implement 'attributes' grammar

4 years agoMerge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr
Eddie Hung [Mon, 16 Dec 2019 20:07:49 +0000 (12:07 -0800)]
Merge branch 'diego/memattr' of https://github.com/dh73/yosys into diego/memattr

4 years agoMerge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram
Eddie Hung [Mon, 16 Dec 2019 20:06:47 +0000 (12:06 -0800)]
Merge branch 'eddie/xilinx_lutram' of github.com:YosysHQ/yosys into eddie/xilinx_lutram

4 years agoPopulate DID/DOD even if unused
Eddie Hung [Mon, 16 Dec 2019 19:56:26 +0000 (11:56 -0800)]
Populate DID/DOD even if unused

4 years agoRename *RAM{32,64}M rules to RAM{32X2,64X1}Q
Eddie Hung [Mon, 16 Dec 2019 18:41:13 +0000 (10:41 -0800)]
Rename *RAM{32,64}M rules to RAM{32X2,64X1}Q

4 years agoFixing compiler warning/issues. Moving test script to the correct place
Diego H [Mon, 16 Dec 2019 16:23:45 +0000 (10:23 -0600)]
Fixing compiler warning/issues. Moving test script to the correct place

4 years agoadd assert option to scratchpad command
N. Engelhardt [Mon, 16 Dec 2019 12:09:31 +0000 (13:09 +0100)]
add assert option to scratchpad command

4 years agoRemoving fixed attribute value to !ramstyle rules
Diego H [Mon, 16 Dec 2019 05:51:58 +0000 (23:51 -0600)]
Removing fixed attribute value to !ramstyle rules

4 years agoMerging attribute rules into a single match block; Adding tests
Diego H [Mon, 16 Dec 2019 05:33:09 +0000 (23:33 -0600)]
Merging attribute rules into a single match block; Adding tests

4 years agoMerge pull request #1575 from rodrigomelo9/master
Eddie Hung [Mon, 16 Dec 2019 03:00:34 +0000 (19:00 -0800)]
Merge pull request #1575 from rodrigomelo9/master

Fixed some missing "verilog_" in documentation

4 years agoMerge pull request #1577 from gromero/for-yosys
Eddie Hung [Mon, 16 Dec 2019 02:59:55 +0000 (18:59 -0800)]
Merge pull request #1577 from gromero/for-yosys

manual: Fix text in Abstract section

4 years agoMerge pull request #1578 from noopwafel/eqneq-debug
Eddie Hung [Mon, 16 Dec 2019 02:59:36 +0000 (18:59 -0800)]
Merge pull request #1578 from noopwafel/eqneq-debug

Fix opt_expr.eqneq.cmpzero debug print

4 years agoFix opt_expr.eqneq.cmpzero debug print
Alyssa Milburn [Sun, 15 Dec 2019 19:40:38 +0000 (20:40 +0100)]
Fix opt_expr.eqneq.cmpzero debug print

4 years agoRefactoring memory attribute matching based on IEEE 1364.1 and Tool specific
Diego H [Fri, 13 Dec 2019 21:43:24 +0000 (15:43 -0600)]
Refactoring memory attribute matching based on IEEE 1364.1 and Tool specific

4 years agoMerge pull request #1533 from dh73/bram_xilinx
Eddie Hung [Fri, 13 Dec 2019 20:01:03 +0000 (12:01 -0800)]
Merge pull request #1533 from dh73/bram_xilinx

Adjust Xilinx xc7/xcu BRAM min bits threshold for RAMB18E1

4 years agoDisable RAM16X1D test
Eddie Hung [Fri, 13 Dec 2019 18:28:13 +0000 (10:28 -0800)]
Disable RAM16X1D test

4 years agoDisable RAM16X1D match rule; carry-over from LUT4 arches
Eddie Hung [Fri, 13 Dec 2019 16:59:17 +0000 (08:59 -0800)]
Disable RAM16X1D match rule; carry-over from LUT4 arches

4 years agoRAM64M8 to also have [5:0] for address
Eddie Hung [Fri, 13 Dec 2019 16:54:19 +0000 (08:54 -0800)]
RAM64M8 to also have [5:0] for address

4 years agoRenaming BRAM memory tests for the sake of uniformity
Diego H [Fri, 13 Dec 2019 15:33:18 +0000 (09:33 -0600)]
Renaming BRAM memory tests for the sake of uniformity

4 years agoFixed some missing "verilog_" in documentation
Rodrigo Alejandro Melo [Fri, 13 Dec 2019 13:17:05 +0000 (10:17 -0300)]
Fixed some missing "verilog_" in documentation

4 years agoadd periods and newlines to help message
N. Engelhardt [Fri, 13 Dec 2019 09:28:34 +0000 (10:28 +0100)]
add periods and newlines to help message

4 years agoRemove extraneous synth_xilinx call
Eddie Hung [Fri, 13 Dec 2019 03:00:26 +0000 (19:00 -0800)]
Remove extraneous synth_xilinx call

4 years agoAdd tests for these new models
Eddie Hung [Fri, 13 Dec 2019 02:52:48 +0000 (18:52 -0800)]
Add tests for these new models

4 years agoAdd RAM32X6SDP and RAM64X3SDP modes
Eddie Hung [Fri, 13 Dec 2019 02:52:28 +0000 (18:52 -0800)]
Add RAM32X6SDP and RAM64X3SDP modes

4 years agoFix RAM64M model to have 6 bit address bus
Eddie Hung [Fri, 13 Dec 2019 02:52:03 +0000 (18:52 -0800)]
Fix RAM64M model to have 6 bit address bus

4 years agoAdd #1460 testcase
Eddie Hung [Fri, 13 Dec 2019 01:49:55 +0000 (17:49 -0800)]
Add #1460 testcase

4 years agoAdd memory rules for RAM16X1D, RAM32M, RAM64M
Eddie Hung [Fri, 13 Dec 2019 01:44:59 +0000 (17:44 -0800)]
Add memory rules for RAM16X1D, RAM32M, RAM64M

4 years agoRename memory tests to lutram, add more xilinx tests
Eddie Hung [Fri, 13 Dec 2019 01:44:37 +0000 (17:44 -0800)]
Rename memory tests to lutram, add more xilinx tests

4 years agoFixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.
Diego H [Thu, 12 Dec 2019 23:32:58 +0000 (17:32 -0600)]
Fixing citation in xc7_xcu_brams.txt file. Fixing RAMB36E1 test.

4 years agoabc9_map.v: fix Xilinx LUTRAM
Eddie Hung [Thu, 12 Dec 2019 22:56:15 +0000 (14:56 -0800)]
abc9_map.v: fix Xilinx LUTRAM

4 years agoAdding a note (TODO) in the memory_params.ys check file
Diego H [Thu, 12 Dec 2019 22:06:46 +0000 (16:06 -0600)]
Adding a note (TODO) in the memory_params.ys check file

4 years agoadd test and make help message more verbose
N. Engelhardt [Thu, 12 Dec 2019 19:51:59 +0000 (20:51 +0100)]
add test and make help message more verbose

4 years agoUpdating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1
Diego H [Thu, 12 Dec 2019 19:50:36 +0000 (13:50 -0600)]
Updating RAMB36E1 thresholds. Adding test for both RAMB18E1/RAMB36E1

4 years agoMerge https://github.com/YosysHQ/yosys into bram_xilinx
Diego H [Thu, 12 Dec 2019 19:40:05 +0000 (13:40 -0600)]
Merge https://github.com/YosysHQ/yosys into bram_xilinx

4 years agoMake SV2017 compliant courtesy of @wsnyder
Eddie Hung [Thu, 12 Dec 2019 15:34:07 +0000 (07:34 -0800)]
Make SV2017 compliant courtesy of @wsnyder

4 years agoadd a command to read/modify scratchpad contents
N. Engelhardt [Thu, 12 Dec 2019 15:14:20 +0000 (16:14 +0100)]
add a command to read/modify scratchpad contents

4 years agoStray log_dump
Eddie Hung [Thu, 12 Dec 2019 00:59:00 +0000 (16:59 -0800)]
Stray log_dump

4 years agoPreserve size of $genval$-s in for loops
Eddie Hung [Thu, 12 Dec 2019 00:26:26 +0000 (16:26 -0800)]
Preserve size of $genval$-s in for loops

4 years agoAdd testcase
Eddie Hung [Thu, 12 Dec 2019 00:26:19 +0000 (16:26 -0800)]
Add testcase

4 years agoUpdate README.md :: abc_ -> abc9_
Eddie Hung [Thu, 12 Dec 2019 00:38:43 +0000 (16:38 -0800)]
Update README.md :: abc_ -> abc9_

4 years agoFix bitwidth mismatch; suppresses iverilog warning
Eddie Hung [Wed, 11 Dec 2019 21:02:07 +0000 (13:02 -0800)]
Fix bitwidth mismatch; suppresses iverilog warning

4 years agomanual: Fix text in Abstract section
Gustavo Romero [Wed, 11 Dec 2019 11:09:48 +0000 (08:09 -0300)]
manual: Fix text in Abstract section

4 years agoMerge pull request #1564 from ZirconiumX/intel_housekeeping
David Shah [Wed, 11 Dec 2019 08:46:10 +0000 (08:46 +0000)]
Merge pull request #1564 from ZirconiumX/intel_housekeeping

Intel housekeeping

4 years agosynth_intel: a10gx -> arria10gx
Dan Ravensloft [Tue, 10 Dec 2019 13:40:32 +0000 (13:40 +0000)]
synth_intel: a10gx -> arria10gx

4 years agosynth_intel: cyclone10 -> cyclone10lp
Dan Ravensloft [Tue, 10 Dec 2019 13:31:45 +0000 (13:31 +0000)]
synth_intel: cyclone10 -> cyclone10lp

4 years agoMerge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr
Eddie Hung [Tue, 10 Dec 2019 01:38:48 +0000 (17:38 -0800)]
Merge pull request #1545 from YosysHQ/eddie/ice40_wrapcarry_attr

Preserve SB_CARRY name and attributes when using $__ICE40_CARRY_WRAPPER

4 years agoice40_opt to restore attributes/name when unwrapping
Eddie Hung [Mon, 9 Dec 2019 22:29:29 +0000 (14:29 -0800)]
ice40_opt to restore attributes/name when unwrapping