yosys.git
8 years agoOptionally use ${CC} when compiling test utils.
Sergey Kvachonok [Fri, 25 Mar 2016 05:47:45 +0000 (08:47 +0300)]
Optionally use ${CC} when compiling test utils.

Default to gcc when not set.

8 years agoAllow redefining pkg-config Makefile command.
Sergey Kvachonok [Thu, 24 Mar 2016 13:07:05 +0000 (16:07 +0300)]
Allow redefining pkg-config Makefile command.

Example usage:

$ make CXX=i686-w64-mingw32-g++ PKG_CONFIG=i686-w64-mingw32-pkg-config

8 years agoAllow redefining binary and data install locations.
Sergey Kvachonok [Thu, 24 Mar 2016 09:18:21 +0000 (12:18 +0300)]
Allow redefining binary and data install locations.

Add three more Makefile variables in addition to PREFIX:

$ make BINDIR=/.../bin LIBDIR=/.../lib DATDIR=/.../share/yosys

The defaults are:

BINDIR = $(PREFIX)/bin
LIBDIR = $(PREFIX)/lib
DATDIR = $(PREFIX)/share/yosys

8 years agoDo not set "nosync" on task outputs, fixes #134
Clifford Wolf [Thu, 24 Mar 2016 11:16:32 +0000 (12:16 +0100)]
Do not set "nosync" on task outputs, fixes #134

8 years agoFixed handling of inverters (aka 1-input luts) in nlutmap
Clifford Wolf [Wed, 23 Mar 2016 07:56:08 +0000 (08:56 +0100)]
Fixed handling of inverters (aka 1-input luts) in nlutmap

8 years agoAdded GP_DFFS, GP_DFFR, and GP_DFFSR
Clifford Wolf [Wed, 23 Mar 2016 07:46:10 +0000 (08:46 +0100)]
Added GP_DFFS, GP_DFFR, and GP_DFFSR

8 years agoAdded GP_DFF INIT parameter
Clifford Wolf [Wed, 23 Mar 2016 07:12:54 +0000 (08:12 +0100)]
Added GP_DFF INIT parameter

8 years agoAdded ast.h to exported headers
Clifford Wolf [Tue, 22 Mar 2016 13:46:10 +0000 (14:46 +0100)]
Added ast.h to exported headers

8 years agoCleanup abstract modules at end of "hierarchy -top"
Clifford Wolf [Mon, 21 Mar 2016 15:33:34 +0000 (16:33 +0100)]
Cleanup abstract modules at end of "hierarchy -top"

8 years agoSupport for abstract modules in chparam
Clifford Wolf [Mon, 21 Mar 2016 15:30:55 +0000 (16:30 +0100)]
Support for abstract modules in chparam

8 years agoAdded support for $stop system task
Clifford Wolf [Mon, 21 Mar 2016 15:19:51 +0000 (16:19 +0100)]
Added support for $stop system task

8 years agoImprovements in synth_greenpak4, added -part option
Clifford Wolf [Mon, 21 Mar 2016 08:44:52 +0000 (09:44 +0100)]
Improvements in synth_greenpak4, added -part option

8 years agoImprovements in ABCEXTERNAL handling
Clifford Wolf [Sat, 19 Mar 2016 19:02:40 +0000 (20:02 +0100)]
Improvements in ABCEXTERNAL handling

8 years agoMerge pull request #130 from ravenexp/master
Clifford Wolf [Sat, 19 Mar 2016 18:46:27 +0000 (19:46 +0100)]
Merge pull request #130 from ravenexp/master

Support calling out to an external ABC.

8 years agoSupport calling out to an external ABC.
Sergey Kvachonok [Sat, 19 Mar 2016 15:36:18 +0000 (18:36 +0300)]
Support calling out to an external ABC.

$ make ABCEXTERNAL=my-abc && make ABCEXTERNAL=my-abc install

configures yosys to use an external ABC executable instead of
building and installing the in-tree ABC copy (yosys-abc).

8 years agoAdded $display %m support, fixed mem leak in $display, fixes #128
Clifford Wolf [Sat, 19 Mar 2016 10:51:13 +0000 (11:51 +0100)]
Added $display %m support, fixed mem leak in $display, fixes #128

8 years agoAdded black box modules for all the 7-series design elements (as listed in ug953)
Clifford Wolf [Sat, 19 Mar 2016 10:09:10 +0000 (11:09 +0100)]
Added black box modules for all the 7-series design elements (as listed in ug953)

8 years agoFixed localparam signdness, fixes #127
Clifford Wolf [Fri, 18 Mar 2016 11:15:00 +0000 (12:15 +0100)]
Fixed localparam signdness, fixes #127

8 years agoSet "nosync" attribute on internal task/function wires
Clifford Wolf [Fri, 18 Mar 2016 09:53:29 +0000 (10:53 +0100)]
Set "nosync" attribute on internal task/function wires

8 years agoFixed Verilog parser fix and more similar improvements
Clifford Wolf [Tue, 15 Mar 2016 11:22:31 +0000 (12:22 +0100)]
Fixed Verilog parser fix and more similar improvements

8 years agoUse left-recursive rule for cell_port_list in Verilog parser.
Andrew Becker [Mon, 14 Mar 2016 18:28:34 +0000 (19:28 +0100)]
Use left-recursive rule for cell_port_list in Verilog parser.

8 years agoBugfix in write_verilog for RTLIL processes
Clifford Wolf [Mon, 14 Mar 2016 12:03:28 +0000 (13:03 +0100)]
Bugfix in write_verilog for RTLIL processes

8 years agoCleanups and improvements in examples/cmos/
Clifford Wolf [Fri, 11 Mar 2016 10:30:01 +0000 (11:30 +0100)]
Cleanups and improvements in examples/cmos/

8 years agoMerge commit 'b34385ec924b6067c1f82bdbae923f8062518956'
Clifford Wolf [Fri, 11 Mar 2016 10:10:44 +0000 (11:10 +0100)]
Merge commit 'b34385ec924b6067c1f82bdbae923f8062518956'

8 years agoFixed typos in verilog_defaults help message
Clifford Wolf [Thu, 10 Mar 2016 10:14:51 +0000 (11:14 +0100)]
Fixed typos in verilog_defaults help message

8 years agoAdded "write_edif -nogndvcc"
Clifford Wolf [Tue, 8 Mar 2016 20:30:45 +0000 (21:30 +0100)]
Added "write_edif -nogndvcc"

8 years agoAdded examples/cxx-api/evaldemo.cc
Clifford Wolf [Tue, 8 Mar 2016 15:54:15 +0000 (16:54 +0100)]
Added examples/cxx-api/evaldemo.cc

8 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Mon, 7 Mar 2016 10:17:44 +0000 (11:17 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys

8 years agoUsing "mfs" and "lutpack" in ABC lut mapping
Clifford Wolf [Mon, 7 Mar 2016 10:14:11 +0000 (11:14 +0100)]
Using "mfs" and "lutpack" in ABC lut mapping

8 years agoCompleted ngspice digital example with verilog tb
Uros Platise [Sat, 5 Mar 2016 07:34:05 +0000 (08:34 +0100)]
Completed ngspice digital example with verilog tb

8 years agoAdded digital (xspice) example code to examples/cmos/
Clifford Wolf [Wed, 2 Mar 2016 11:07:57 +0000 (12:07 +0100)]
Added digital (xspice) example code to examples/cmos/

8 years agoBe more conservative with net names in spice output
Clifford Wolf [Wed, 2 Mar 2016 11:02:59 +0000 (12:02 +0100)]
Be more conservative with net names in spice output

8 years agoMerge pull request #119 from SebKuzminsky/spelling-fixes
Clifford Wolf [Mon, 29 Feb 2016 09:18:50 +0000 (10:18 +0100)]
Merge pull request #119 from SebKuzminsky/spelling-fixes

user-facing spelling fixes

8 years agouser-facing spelling fixes
Sebastian Kuzminsky [Sun, 28 Feb 2016 22:14:01 +0000 (15:14 -0700)]
user-facing spelling fixes

"speciefied" -> "specified"
"unkown" -> "unknown"

8 years agoWe are now in 0.6+ development
Clifford Wolf [Fri, 26 Feb 2016 16:24:31 +0000 (17:24 +0100)]
We are now in 0.6+ development

8 years agoYosys 0.6 yosys-0.6
Clifford Wolf [Fri, 26 Feb 2016 15:55:21 +0000 (16:55 +0100)]
Yosys 0.6

8 years agoFixed BLIF parser for empty port assignments
Clifford Wolf [Wed, 24 Feb 2016 08:16:43 +0000 (09:16 +0100)]
Fixed BLIF parser for empty port assignments

8 years agoUse easyer-to-read unoptimized ceil_log2()
Clifford Wolf [Mon, 15 Feb 2016 22:06:18 +0000 (23:06 +0100)]
Use easyer-to-read unoptimized ceil_log2()

see here for details on the optimized version:
http://svn.clifford.at/handicraft/2016/esbmc/ceilog2.c

8 years agoUpdated ABC to ae7d65e71adc
Clifford Wolf [Mon, 15 Feb 2016 14:30:46 +0000 (15:30 +0100)]
Updated ABC to ae7d65e71adc

8 years agoUpdated command reference in manual
Clifford Wolf [Sun, 14 Feb 2016 10:02:11 +0000 (11:02 +0100)]
Updated command reference in manual

8 years agoChangelog for upcoming 0.6 release
Clifford Wolf [Sun, 14 Feb 2016 09:50:19 +0000 (10:50 +0100)]
Changelog for upcoming 0.6 release

8 years agoFixed more visual studio warnings
Clifford Wolf [Sun, 14 Feb 2016 08:35:25 +0000 (09:35 +0100)]
Fixed more visual studio warnings

8 years agoFixed some visual studio warnings
Clifford Wolf [Sat, 13 Feb 2016 16:31:24 +0000 (17:31 +0100)]
Fixed some visual studio warnings

8 years agoMerge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sat, 13 Feb 2016 16:01:29 +0000 (17:01 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys

8 years agoAdded "int ceil_log2(int)" function
Clifford Wolf [Sat, 13 Feb 2016 15:52:16 +0000 (16:52 +0100)]
Added "int ceil_log2(int)" function

8 years agoFixed MXE ABC build
Clifford Wolf [Sat, 13 Feb 2016 14:43:23 +0000 (15:43 +0100)]
Fixed MXE ABC build

8 years agoRun dffsr2dff in synth_xilinx
Clifford Wolf [Sat, 13 Feb 2016 07:20:19 +0000 (08:20 +0100)]
Run dffsr2dff in synth_xilinx

8 years agoSupport for more Verific primitives (patch I got per email)
Clifford Wolf [Sat, 13 Feb 2016 07:19:30 +0000 (08:19 +0100)]
Support for more Verific primitives (patch I got per email)

8 years agoUpdated ABC
Clifford Wolf [Mon, 8 Feb 2016 00:13:53 +0000 (01:13 +0100)]
Updated ABC

8 years agoWork around DDR dout sim glitches in ice40 SB_IO sim model
Clifford Wolf [Sun, 7 Feb 2016 10:19:48 +0000 (11:19 +0100)]
Work around DDR dout sim glitches in ice40 SB_IO sim model

8 years agoUpdated ABC
Clifford Wolf [Sun, 7 Feb 2016 07:56:32 +0000 (08:56 +0100)]
Updated ABC

8 years agoAdded "stat -liberty" for calculating chip area
Clifford Wolf [Thu, 4 Feb 2016 11:26:13 +0000 (12:26 +0100)]
Added "stat -liberty" for calculating chip area

8 years agoBugfix in Verific front-end
Clifford Wolf [Wed, 3 Feb 2016 07:59:57 +0000 (08:59 +0100)]
Bugfix in Verific front-end

8 years agoUpdated verific build instructions
Clifford Wolf [Tue, 2 Feb 2016 18:50:17 +0000 (19:50 +0100)]
Updated verific build instructions

8 years agoImproved dffsr2dff pass
Clifford Wolf [Tue, 2 Feb 2016 18:42:49 +0000 (19:42 +0100)]
Improved dffsr2dff pass

8 years agoAdded dffsr2dff
Clifford Wolf [Tue, 2 Feb 2016 16:19:01 +0000 (17:19 +0100)]
Added dffsr2dff

8 years agoAdded addBufGate module method
Clifford Wolf [Tue, 2 Feb 2016 10:26:07 +0000 (11:26 +0100)]
Added addBufGate module method

8 years agoUse alphanumerical order instead of idstring idx in opt_clean compare_signals()
Clifford Wolf [Tue, 2 Feb 2016 08:16:18 +0000 (09:16 +0100)]
Use alphanumerical order instead of idstring idx in opt_clean compare_signals()

8 years agoAdded CodeOfConduct
Clifford Wolf [Mon, 1 Feb 2016 15:36:59 +0000 (16:36 +0100)]
Added CodeOfConduct

8 years agoUpdated ABC to hg rev ee212a9e94df
Clifford Wolf [Mon, 1 Feb 2016 14:51:27 +0000 (15:51 +0100)]
Updated ABC to hg rev ee212a9e94df

8 years agoProgress in cell library documentation
Clifford Wolf [Mon, 1 Feb 2016 12:58:10 +0000 (13:58 +0100)]
Progress in cell library documentation

8 years agoAdded "abc -luts" option, Improved Xilinx logic mapping
Clifford Wolf [Mon, 1 Feb 2016 11:40:32 +0000 (12:40 +0100)]
Added "abc -luts" option, Improved Xilinx logic mapping

8 years agoImprovements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)
Clifford Wolf [Mon, 1 Feb 2016 10:49:11 +0000 (11:49 +0100)]
Improvements in dfflibmap (FFs with Q/QN outputs, DFFs from ADFFs)

8 years agoSigMap performance improvement
Clifford Wolf [Mon, 1 Feb 2016 09:10:20 +0000 (10:10 +0100)]
SigMap performance improvement

8 years agohashlib mfp<> performance improvements
Clifford Wolf [Mon, 1 Feb 2016 09:03:03 +0000 (10:03 +0100)]
hashlib mfp<> performance improvements

8 years agoAdded reserve() method to haslib classes and
Clifford Wolf [Sun, 31 Jan 2016 21:50:34 +0000 (22:50 +0100)]
Added reserve() method to haslib classes and
calculate hashtable size based on entries capacity, not size

8 years agoMerge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys
Clifford Wolf [Sun, 31 Jan 2016 20:53:18 +0000 (21:53 +0100)]
Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys

8 years agoMore clang sanitizer stuff
Clifford Wolf [Sun, 31 Jan 2016 18:55:48 +0000 (19:55 +0100)]
More clang sanitizer stuff

8 years agortlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)
Rick Altherr [Sun, 31 Jan 2016 17:07:21 +0000 (09:07 -0800)]
rtlil: Improve performance of SigSpec::extract(SigSpec, SigSpec*)

Converting to a pool<SigBit> is fairly expensive due to inserts somewhat
frequently causing rehashing.  Instead, walk through the pattern SigSpec
directly on a chunk-by-chunk basis and apply it to this SigSpec's
individual bits.  Using chunks for the pattern minimizes the number of
iterations in the outer loop.

8 years agortlil: speed up SigSpec::sort_and_unify()
Rick Altherr [Sun, 31 Jan 2016 16:55:49 +0000 (08:55 -0800)]
rtlil: speed up SigSpec::sort_and_unify()

std::set<> internally is often a red-black tree which is fairly
expensive to create but fast to lookup.  In the case of
sort_and_unify(), a set<> is constructed as a temporary object to
attempt to speed up lookups.  Being a temporarily, however, the cost of
creation far outweights the lookup improvement and is a net performance
loss.  Instead, sort the vector<> that already exists and then apply
std::unique().

8 years agortlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)
Rick Altherr [Sun, 31 Jan 2016 03:43:29 +0000 (19:43 -0800)]
rtlil: improve performance of SigSpec::replace(SigSpec, SigSpec, SigSpec*)

8 years agogenrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFrom...
Rick Altherr [Sun, 31 Jan 2016 03:26:46 +0000 (19:26 -0800)]
genrtlil: avoid converting SigSpec to set<SigBit> when going through removeSignalFromCaseTree()

8 years agortlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)
Rick Altherr [Sun, 31 Jan 2016 03:25:35 +0000 (19:25 -0800)]
rtlil: improve performance of SigSpec::remove2(SigSpec, SigSpec*)

8 years agoMeaningless coding style change
Clifford Wolf [Sun, 31 Jan 2016 15:12:35 +0000 (16:12 +0100)]
Meaningless coding style change

8 years agoMerge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys
Clifford Wolf [Sun, 31 Jan 2016 15:10:27 +0000 (16:10 +0100)]
Merge branch 'rtlil_remove2_speedup' of https://github.com/kc8apf/yosys

8 years agoAddedd clang sanitizers
Clifford Wolf [Sun, 31 Jan 2016 15:08:21 +0000 (16:08 +0100)]
Addedd clang sanitizers

8 years agortlil: rewrite remove2() to avoid copying
Rick Altherr [Sat, 30 Jan 2016 06:40:45 +0000 (22:40 -0800)]
rtlil: rewrite remove2() to avoid copying

8 years agortlil: duplicate remove2() for std::set<>
Rick Altherr [Sat, 30 Jan 2016 06:03:12 +0000 (22:03 -0800)]
rtlil: duplicate remove2() for std::set<>

8 years agortlil: change IdString comparison operators to take references instead of copies
Rick Altherr [Sat, 30 Jan 2016 06:40:17 +0000 (22:40 -0800)]
rtlil: change IdString comparison operators to take references instead of copies

8 years agoAdded "equiv_struct -fwonly"
Clifford Wolf [Fri, 8 Jan 2016 09:59:16 +0000 (10:59 +0100)]
Added "equiv_struct -fwonly"

8 years agoBugfixes in equiv_struct
Clifford Wolf [Fri, 8 Jan 2016 08:39:27 +0000 (09:39 +0100)]
Bugfixes in equiv_struct

8 years agoAdded "submod -copy"
Clifford Wolf [Fri, 8 Jan 2016 08:08:12 +0000 (09:08 +0100)]
Added "submod -copy"

8 years agoAdded "write_blif -cname" mode
Clifford Wolf [Wed, 6 Jan 2016 13:32:28 +0000 (14:32 +0100)]
Added "write_blif -cname" mode

8 years agoAdded "equiv_struct -maxiter <N>"
Clifford Wolf [Wed, 6 Jan 2016 12:54:54 +0000 (13:54 +0100)]
Added "equiv_struct -maxiter <N>"

8 years agoAdded "equiv_add -try" mode
Clifford Wolf [Wed, 6 Jan 2016 12:54:00 +0000 (13:54 +0100)]
Added "equiv_add -try" mode

8 years agoFixed "splitnets -ports" for hierarchical designs
Clifford Wolf [Tue, 22 Dec 2015 12:25:00 +0000 (13:25 +0100)]
Fixed "splitnets -ports" for hierarchical designs

8 years agoRe-run ice40_opt in "synth_ice40 -abc2"
Clifford Wolf [Tue, 22 Dec 2015 11:19:11 +0000 (12:19 +0100)]
Re-run ice40_opt in "synth_ice40 -abc2"

8 years agoImprovements in ice40_opt
Clifford Wolf [Tue, 22 Dec 2015 11:18:38 +0000 (12:18 +0100)]
Improvements in ice40_opt

8 years agoBugfix in ice40_ffinit
Clifford Wolf [Tue, 22 Dec 2015 11:18:06 +0000 (12:18 +0100)]
Bugfix in ice40_ffinit

8 years agoImproved ice40_ffinit
Clifford Wolf [Tue, 22 Dec 2015 10:15:25 +0000 (11:15 +0100)]
Improved ice40_ffinit

8 years agoRun opt_const before check in default scripts
Clifford Wolf [Tue, 22 Dec 2015 10:15:05 +0000 (11:15 +0100)]
Run opt_const before check in default scripts

8 years agoAdded %R select expression
Clifford Wolf [Sun, 20 Dec 2015 12:35:58 +0000 (13:35 +0100)]
Added %R select expression

8 years agoVarious improvements in BLIF front-end
Clifford Wolf [Sun, 20 Dec 2015 12:12:24 +0000 (13:12 +0100)]
Various improvements in BLIF front-end

8 years agoAdded yosys-smtbmc -S
Clifford Wolf [Sun, 20 Dec 2015 08:58:54 +0000 (09:58 +0100)]
Added yosys-smtbmc -S

8 years agoMerge pull request #110 from scanlime/master
Clifford Wolf [Tue, 15 Dec 2015 18:54:07 +0000 (19:54 +0100)]
Merge pull request #110 from scanlime/master

Trivial changes to fix Mac OS build

8 years agoMac build fix, gsed -> sed
Micah Elizabeth Scott [Tue, 15 Dec 2015 18:22:35 +0000 (10:22 -0800)]
Mac build fix, gsed -> sed

Homebrew is calling its GNU sed just 'sed' now.

8 years agoRemove nonportable "-r" option from xargs
Micah Elizabeth Scott [Tue, 15 Dec 2015 18:13:06 +0000 (10:13 -0800)]
Remove nonportable "-r" option from xargs

On Linux, this avoids an empty "rm -f" call when there's nothing to clean. But it isn't portable, and it causes the build to fail on Mac OS. It doesn't seem to be harmful to remove this option entirely, and it's a step toward fixing the Mac build.

8 years agoAdded "synth_ice40 -abc2"
Clifford Wolf [Tue, 8 Dec 2015 10:16:26 +0000 (11:16 +0100)]
Added "synth_ice40 -abc2"

8 years agoMerge pull request #108 from cseed/master
Clifford Wolf [Mon, 7 Dec 2015 02:32:20 +0000 (03:32 +0100)]
Merge pull request #108 from cseed/master

Added LO to ICESTORM_LC for LUT cascade route.

8 years agoAdded LO to ICESTORM_LC for LUT cascade route.
Cotton Seed [Sun, 6 Dec 2015 22:24:48 +0000 (17:24 -0500)]
Added LO to ICESTORM_LC for LUT cascade route.