Florent Kermarrec [Sat, 20 Apr 2019 22:04:56 +0000 (00:04 +0200)]
boards/platforms/kc705: only keep Vivado support
There is no reason still using ISE on 7-Series.
Florent Kermarrec [Sat, 20 Apr 2019 21:56:27 +0000 (23:56 +0200)]
boards: always define timing constraints the same way (1e9/freq_mhz)
Florent Kermarrec [Sat, 20 Apr 2019 21:47:05 +0000 (23:47 +0200)]
boards/targets/ulx3s: allow running test_targets on it
Florent Kermarrec [Sat, 20 Apr 2019 21:43:44 +0000 (23:43 +0200)]
boards/targets: add keep attribute directly in crg
This makes it systematic and avoid having to add it later.
enjoy-digital [Sat, 20 Apr 2019 10:23:24 +0000 (12:23 +0200)]
Merge pull request #167 from xobs/network-flag-check
litex_server: check socket flags exist before using them
Sean Cross [Sat, 20 Apr 2019 09:28:26 +0000 (17:28 +0800)]
litex_server: check socket flags exist before using them
Some flags are only available on certain platforms. Verify these flags
exist prior to using them when opening a socket.
See
https://stackoverflow.com/questions/
14388706/socket-options-so-reuseaddr-and-so-reuseport-how-do-they-differ-do-they-mean-t
for more information
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Sat, 20 Apr 2019 08:44:53 +0000 (10:44 +0200)]
tools: move from litex.soc.tools to litex.tools and fix usb.core import
enjoy-digital [Fri, 19 Apr 2019 17:16:16 +0000 (19:16 +0200)]
Merge pull request #165 from xobs/vexriscv-cpu-reset-address
Vexriscv cpu reset address
enjoy-digital [Fri, 19 Apr 2019 17:14:15 +0000 (19:14 +0200)]
Merge pull request #164 from xobs/litex-usb-server
Litex usb server support
Sean Cross [Fri, 19 Apr 2019 14:56:39 +0000 (15:56 +0100)]
utils: litex_server: add usb support
Add `--usb` and associated arguments to create a litex bridge over
USB. This makes use of the new CommUSB module.
Signed-off-by: Sean Cross <sean@xobs.io>
Sean Cross [Fri, 19 Apr 2019 14:54:48 +0000 (15:54 +0100)]
tools: remote: add usb communications protocol
This adds a USB communications protocol to the suite of litex-supported
wishbone bridge protocols.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Fri, 19 Apr 2019 10:13:16 +0000 (12:13 +0200)]
soc/interconnect/axi: add AXIBurst2Beat
Converts AXI bursts commands to AXI beats.
Florent Kermarrec [Fri, 19 Apr 2019 09:43:15 +0000 (11:43 +0200)]
soc/interconnect/avalon: add description
Sean Cross [Fri, 19 Apr 2019 08:47:55 +0000 (16:47 +0800)]
Merge branch 'master' of https://github.com/enjoy-digital/litex
Florent Kermarrec [Fri, 19 Apr 2019 08:21:56 +0000 (10:21 +0200)]
soc/integration/soc_zynq: fix HP0 connections
Florent Kermarrec [Fri, 19 Apr 2019 07:18:25 +0000 (09:18 +0200)]
build/xilinx/vivado: only set library for vhdl files (not supported for verilog/system-verilog)
Sean Cross [Fri, 19 Apr 2019 05:04:57 +0000 (13:04 +0800)]
cpu: vexriscv: allow cpu_reset_address to be overridden
Allow the cpu_reset_address value to be overridden, for example allowing
it to be a signal. That way the reset address can be modified after
synthesis, in dual-core or debug situations.
Signed-off-by: Sean Cross <sean@xobs.io>
Florent Kermarrec [Thu, 18 Apr 2019 16:42:29 +0000 (18:42 +0200)]
soc/interconnect: add avalon with converters to/from native streams
enjoy-digital [Wed, 17 Apr 2019 17:01:55 +0000 (19:01 +0200)]
Merge pull request #162 from antmicro/full-conf-vexriscv
Add full and full_debug CPU variant of VexRiscv
enjoy-digital [Wed, 17 Apr 2019 16:59:28 +0000 (18:59 +0200)]
Merge pull request #163 from gsomlo/gls-verilated-cmdargs
build/sim/core: Initialize Verilator commandArgs
Gabriel L. Somlo [Wed, 17 Apr 2019 14:39:35 +0000 (10:39 -0400)]
build/sim/core: Initialize Verilator commandArgs
Required when DUT is using plusargs. Prevents Verilator simulation
from crashing with "Verilog called $test$plusargs or $value$plusargs
without testbench C first calling Verilated::commandArgs(argc,argv)".
Joanna Brozek [Fri, 12 Apr 2019 15:23:23 +0000 (17:23 +0200)]
vexriscv: Add full and full_debug CPU variant
Florent Kermarrec [Tue, 16 Apr 2019 14:57:23 +0000 (16:57 +0200)]
build/altera: switch to sdc constraints, add add_false_path_constraints method
Florent Kermarrec [Mon, 15 Apr 2019 14:48:47 +0000 (16:48 +0200)]
build/xilinx/vivado: set quiet property on MultiReg/AsyncResetSynchronizer constraints
MultiReg/AsyncResetSynchronizer are not necessarily present in all design, set
quiet property to avoid generating false warnings.
Florent Kermarrec [Mon, 15 Apr 2019 09:36:42 +0000 (11:36 +0200)]
soc/cores/clock: add divclk_divide/vco_margin support on S7/Ultrascale
Florent Kermarrec [Mon, 15 Apr 2019 08:57:00 +0000 (10:57 +0200)]
soc/cores/clock: improve presentation
Florent Kermarrec [Mon, 15 Apr 2019 08:51:17 +0000 (10:51 +0200)]
build/xilinx/vivado: round period constraints to lowest picosecond
Vivado will do the opposite if we don't do it, with this change we ensure the applied period constraints will always be >= to the requested constraint.
enjoy-digital [Mon, 15 Apr 2019 06:24:28 +0000 (08:24 +0200)]
Merge pull request #161 from enjoy-digital/litex_server_arguments
litex_server: refactor parameters and to allow setting bind address
Florent Kermarrec [Mon, 15 Apr 2019 06:23:27 +0000 (08:23 +0200)]
litex_server: set socket.SO_REUSEPORT to avoid waiting 60s in case of unclean termination
Florent Kermarrec [Sun, 14 Apr 2019 12:00:35 +0000 (14:00 +0200)]
litex_server: add message and exit when mandarory arguments are missing.
Florent Kermarrec [Sun, 14 Apr 2019 10:11:37 +0000 (12:11 +0200)]
litex_server: allow setting bind port, remove auto-incrementing on bind_port
Florent Kermarrec [Sun, 14 Apr 2019 06:56:51 +0000 (08:56 +0200)]
litex_server: refactor parameters and to allow setting bind address
In some cases, it can be useful to bind to "0.0.0.0" instead of "localhost".
While adding bind address support, parameters passing has also been refactored
to ease adding parameters in the future.
Florent Kermarrec [Fri, 12 Apr 2019 16:10:44 +0000 (18:10 +0200)]
software/libnet/microudp: simplify txbuffer managment
Florent Kermarrec [Fri, 12 Apr 2019 15:15:09 +0000 (17:15 +0200)]
software/libnet/microudp: cleanup eth_init
Florent Kermarrec [Fri, 12 Apr 2019 15:14:07 +0000 (17:14 +0200)]
software/libnet/microudp: simplify rxbuffer managment
Florent Kermarrec [Fri, 12 Apr 2019 15:09:50 +0000 (17:09 +0200)]
software/libnet/microudp: set raw frame size to ETHMAC_SLOT_SIZE
Florent Kermarrec [Fri, 12 Apr 2019 15:08:29 +0000 (17:08 +0200)]
software/libnet: remove use of ethmac_mem.h
Florent Kermarrec [Thu, 11 Apr 2019 20:26:58 +0000 (22:26 +0200)]
bios/sdram: add __attribute__((unused)) on cdelay
Florent Kermarrec [Wed, 10 Apr 2019 16:04:48 +0000 (18:04 +0200)]
litex_setup: add litesata
Florent Kermarrec [Wed, 10 Apr 2019 14:36:49 +0000 (16:36 +0200)]
boards/targets/kcu105: add Ethernet (with 1Gbps SFP adapter)
Florent Kermarrec [Wed, 10 Apr 2019 14:16:47 +0000 (16:16 +0200)]
software/libnet: add #ifdef on eth_init
enjoy-digital [Mon, 8 Apr 2019 12:32:44 +0000 (14:32 +0200)]
Merge pull request #158 from vbuitvydas/altera-contrib
Changes for litepcie support for Altera Cyclone V
vytautasb [Mon, 8 Apr 2019 10:34:59 +0000 (13:34 +0300)]
litex/build/altera/quartus: changes to make top level assigment in .qsf file with build name
vytautasb [Mon, 8 Apr 2019 10:28:25 +0000 (13:28 +0300)]
litex/build/altera/common: added reset synchronizer
Florent Kermarrec [Mon, 1 Apr 2019 12:44:37 +0000 (14:44 +0200)]
integration/soc_zynq: fix missing SoCCore.do_finalize
Signed-off-by: Florent Kermarrec <florent@enjoy-digital.fr>
Florent Kermarrec [Mon, 1 Apr 2019 09:07:30 +0000 (11:07 +0200)]
integration/soc_zynq: add add_hp0 method
Florent Kermarrec [Mon, 1 Apr 2019 08:50:04 +0000 (10:50 +0200)]
integration/soc_zynq: use add methods to add optional peripherals
Florent Kermarrec [Mon, 1 Apr 2019 08:31:33 +0000 (10:31 +0200)]
integration/soc_zynq: connect axi signals that were missing
Florent Kermarrec [Mon, 1 Apr 2019 08:23:05 +0000 (10:23 +0200)]
interconnect/axi: add missing axi signals
enjoy-digital [Sun, 31 Mar 2019 16:46:07 +0000 (18:46 +0200)]
Merge pull request #157 from CBJamo/master
Add ifdef check for MAIN_RAM_SIZE
Caleb Jamison [Sun, 31 Mar 2019 15:33:39 +0000 (10:33 -0500)]
Add ifdef check for MAIN_RAM_SIZE
Florent Kermarrec [Sat, 30 Mar 2019 11:27:06 +0000 (12:27 +0100)]
README: bump copyright year
Florent Kermarrec [Sat, 30 Mar 2019 10:49:39 +0000 (11:49 +0100)]
bios/main: align SoC info, show CPU speed on CPU line, show L2
Florent Kermarrec [Sat, 30 Mar 2019 09:56:17 +0000 (10:56 +0100)]
bios/main: move sdrinit
Florent Kermarrec [Sat, 30 Mar 2019 09:19:00 +0000 (10:19 +0100)]
bios/main: print boot sequence only if sdr_ok
Florent Kermarrec [Fri, 29 Mar 2019 18:40:24 +0000 (19:40 +0100)]
bios/main: remove csr functions (not used and only supported by lm32), improve help presentation
Florent Kermarrec [Thu, 28 Mar 2019 23:51:16 +0000 (00:51 +0100)]
software/bios: improve readibility, add soc informations
enjoy-digital [Thu, 28 Mar 2019 17:27:36 +0000 (18:27 +0100)]
Merge pull request #156 from gsomlo/gls-axi-width
soc/interconnect/axi: address length cleanup
Gabriel L. Somlo [Wed, 27 Mar 2019 20:38:25 +0000 (16:38 -0400)]
soc/interconnect/axi: data/address length cleanup
Instead of hard-coding data and address width to 32, assert that
the AXI and Wishbone interfaces have *matching* address and data
widths.
Florent Kermarrec [Wed, 27 Mar 2019 20:15:14 +0000 (21:15 +0100)]
soc/interconnect/axi: remove dead code (thanks gsomlo)
enjoy-digital [Fri, 22 Mar 2019 16:43:40 +0000 (17:43 +0100)]
Merge pull request #154 from daveshah1/yosys_xilinx_edif
build/xilinx: Update Yosys write_edif parameters
David Shah [Fri, 22 Mar 2019 16:06:52 +0000 (16:06 +0000)]
build/xilinx: Update Yosys write_edif parameters
Florent Kermarrec [Sat, 16 Mar 2019 20:25:02 +0000 (21:25 +0100)]
utils/litex_sim: fix main_ram_size
Florent Kermarrec [Sat, 16 Mar 2019 20:23:36 +0000 (21:23 +0100)]
soc_core/get_mem_data: add json support
example of json file:
{
"vmlinux.bin": "0x00000000",
"vmlinux.dtb": "0x01000000",
"initramdisk.gz": "0x01002000"
}
Florent Kermarrec [Sat, 16 Mar 2019 08:33:16 +0000 (09:33 +0100)]
build/microsemi/libero_soc: add linux build script support
Florent Kermarrec [Fri, 15 Mar 2019 17:16:25 +0000 (18:16 +0100)]
vexriscv: allow user to use an external variant
Florent Kermarrec [Fri, 15 Mar 2019 16:49:39 +0000 (17:49 +0100)]
vexriscv/core: fix min variant
Florent Kermarrec [Wed, 13 Mar 2019 09:56:09 +0000 (10:56 +0100)]
utils/litex_sim: handle cpu_endianness for rom-init/ram-init
Florent Kermarrec [Wed, 13 Mar 2019 09:42:10 +0000 (10:42 +0100)]
utils/litex_sim: increase default integrated_main_ram_size to 256MB, automatically boot on main_ram when ram_init is specified
enjoy-digital [Thu, 7 Mar 2019 20:12:00 +0000 (21:12 +0100)]
Merge pull request #153 from railnova/fix_utils
[fix] utils was omitted when installed from pip
chmousset [Thu, 7 Mar 2019 08:40:58 +0000 (09:40 +0100)]
[fix] utils was not installed from pip
enjoy-digital [Wed, 6 Mar 2019 22:41:20 +0000 (23:41 +0100)]
Merge pull request #152 from gsomlo/gls-trellis-svf
build/lattice/trellis: generate bitstream directly in svf format
Gabriel L. Somlo [Wed, 6 Mar 2019 17:59:49 +0000 (12:59 -0500)]
build/lattice/trellis: also generate bitstream in svf format
Before being able to program the board (e.g., with openocd), one
would have to convert the bitstream file to .svf using a python
script included with the source trellis distribution. However,the
trellis 'ecppack' utility can also generate .svf bitstream files
directly.
Florent Kermarrec [Tue, 5 Mar 2019 17:01:03 +0000 (18:01 +0100)]
software/bios/sdram: use specific ERR_DDRPHY_BITSLIP/NMODULES computation
In the future, the PHYs should generated these constants.
Florent Kermarrec [Tue, 5 Mar 2019 12:23:38 +0000 (13:23 +0100)]
targets/versa_ecp5: update ECP5DDRPHY on BaseSoC, add EthernetSoC
Florent Kermarrec [Tue, 5 Mar 2019 11:26:10 +0000 (12:26 +0100)]
bios/sdram: use burstdet detection for ECP5DDRPHY init
enjoy-digital [Mon, 4 Mar 2019 11:00:44 +0000 (12:00 +0100)]
Merge pull request #150 from daveshah1/trellis_bus_fixes
lattice/common: Fix tristate buses with Trellis
David Shah [Mon, 4 Mar 2019 10:50:56 +0000 (10:50 +0000)]
lattice/common: Fix tristate buses with Trellis
Signed-off-by: David Shah <dave@ds0.me>
Florent Kermarrec [Mon, 4 Mar 2019 08:40:14 +0000 (09:40 +0100)]
boards/ulx3s: add device selection parameter
ULX3S can be populated with LFE5U-45F (default) or LFE5U-85F
Florent Kermarrec [Mon, 4 Mar 2019 08:27:31 +0000 (09:27 +0100)]
targets/ulx3s: use AsyncResetSynchronizer and derivate sys_clk/sys_clk_ps constraints from clk25
Now supported by Trellis/Nextpnr.
Florent Kermarrec [Fri, 1 Mar 2019 14:20:02 +0000 (15:20 +0100)]
build/lattice/trellis: add package support
Florent Kermarrec [Fri, 1 Mar 2019 13:20:00 +0000 (14:20 +0100)]
build/lattice/trellis: basecfg now integrated in nextpnr
Florent Kermarrec [Fri, 1 Mar 2019 12:57:45 +0000 (13:57 +0100)]
boards/targets/ulx3s: allow building with diamond or trellis
Florent Kermarrec [Fri, 1 Mar 2019 08:16:48 +0000 (09:16 +0100)]
soc/software/bios/boot: add vexriscv workaround
Flushing icache was working correctly on previous version of Vexriscv, understand
why it's no longer the case.
Florent Kermarrec [Wed, 27 Feb 2019 21:30:40 +0000 (22:30 +0100)]
soc/integration: add initial SoCZynq SoC
Florent Kermarrec [Wed, 27 Feb 2019 21:26:57 +0000 (22:26 +0100)]
soc/interconnect: add initial axi code with bus definition and AXI2Wishbone
Florent Kermarrec [Wed, 27 Feb 2019 21:24:56 +0000 (22:24 +0100)]
test: add test_axi_lite (with test code from soc/interconnect/axi_lite lightly modified)
Florent Kermarrec [Wed, 27 Feb 2019 21:11:09 +0000 (22:11 +0100)]
soc/interconnect: rename axi to axi_lite
Florent Kermarrec [Wed, 27 Feb 2019 20:44:11 +0000 (21:44 +0100)]
test: add basic test_csr
enjoy-digital [Mon, 25 Feb 2019 18:26:07 +0000 (19:26 +0100)]
Merge pull request #149 from daveshah1/versa_trellis
Add trellis build option to versa_ecp5 and bring trellis support up to date
David Shah [Mon, 25 Feb 2019 18:02:04 +0000 (18:02 +0000)]
versa_ecp5: Add option to build with Trellis
David Shah [Mon, 25 Feb 2019 18:01:35 +0000 (18:01 +0000)]
trellis: Add LPF frequency constraints and remove -nomux
Florent Kermarrec [Mon, 25 Feb 2019 15:12:21 +0000 (16:12 +0100)]
soc/software/sdram: fix compilation on ultrascale
Florent Kermarrec [Mon, 25 Feb 2019 14:27:08 +0000 (15:27 +0100)]
targets/versa_ecp5: integrate DDR3
Florent Kermarrec [Mon, 25 Feb 2019 13:40:47 +0000 (14:40 +0100)]
soc/software/bios/sdram: add ECP5 support
Florent Kermarrec [Mon, 25 Feb 2019 13:38:24 +0000 (14:38 +0100)]
soc/software/bios/sdram: improve write_level robustness
Florent Kermarrec [Mon, 25 Feb 2019 13:37:31 +0000 (14:37 +0100)]
soc/software/bios/sdram: improve sdrlevel readibility
Florent Kermarrec [Mon, 25 Feb 2019 13:36:47 +0000 (14:36 +0100)]
soc/software/bios/sdram: add helpers for rst/inc of delays
enjoy-digital [Fri, 22 Feb 2019 13:32:45 +0000 (14:32 +0100)]
Merge pull request #148 from daveshah1/versa_remove_n
versa_ecp5: Remove negative diff IO pins
David Shah [Fri, 22 Feb 2019 12:12:10 +0000 (12:12 +0000)]
versa_ecp5: Remove negative diff IO pins
In Lattice FPGAs only the positive side of differential pairs should
be specified (unlike Xilinx)
These are a warning on Diamond (which trims unused IO) and an error
with Yosys/nextpnr (which doesn't so they conflict when the positive
pin is 'expanded').
Already this is the case for the clock input, this commit performs
the same change for the DDR3 pins.