aco: sign-extend input/indentity for 32-bit reduce ops on GFX10

Because some 16-bit instructions are already VOP3 on GFX10, we use
the 32-bit variants to remove the temporary VGPR and to use DDP with
the arithmetic instructions.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

aco: allow gfx10_wave64_bpermute with 8-bit/16-bit input

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

aco: allocate a temp VGPR for some 8-bit/16-bit reduction ops on GFX10

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

aco: implement 8-bit/16-bit reductions on GFX10

Some 16-bit instructions are VOP3 on GFX10 and we have to emit a
32-bit DPP mov followed by the ALU instruction.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

aco: fix register allocation for subdword instructions on GFX10

Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>

frontend/dri: Implement mapping individual planes.

It is kinda surprising that

image2 = fromPlanar(image, 2, NULL)
mapImage(..., image2, ...)

does not map the third plane.

This implements that behavior in the case where the DRI frontend
lowers the multi-planar textures.

In the case it doesn't this would need driver support. AFAIU at
least etnaviv is impacted, and while it looks possible, I don't
have the etnaviv knowledge to implement it.

Instead of silently returning weird results (either always plane 0
or possibly something interleaved) this adds an error return on
mapping multi-planar textures otherwise.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5200>

zink: Check fopen result.

Fix warning reported by Coverity.

Dereference null return value (NULL_RETURNS)
dereference: Dereferencing a pointer that might be NULL fp when calling
fwrite.

Fixes: 8d46e35d16e3 ("zink: introduce opengl over vulkan")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5235>

radv/aco: enable VK_EXT_subgroup_size_control

ACO should already support Wave32 on GFX10 with all shader stages
and CTS pass. RADV currently only allows Wave32 with the compute
shader stage.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5056>

freedreno/a6xx: document LRZ flag buffer

Doesn't seem to be a big win, although I could still be missing
something in my implementation.  But might as well add the
documentation.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>

freedreno/a6xx: LRZ fix for alpha-test

Similarly to stencil-test, if alpha-test is enabled, we don't know
necessarily whether the fragment will pass.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3045
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>

util: Initialize pipe_shader_state for passthrough and transform shaders

mesa/st is initializing pipe_shader_state for user define shaders.
This patch intialized pipe_shader_state for all passthough
and transform shaders.

This fixes crashes for several opengl apps. Issue is found in vmware
internal testing

Fixes: f01c0565bb9 ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5240>

iris: Rename iris_seqno to iris_fine_fence

Rename iris_seqno to iris_fine_fence, borrowed from si_fine_fence, to
avoid introducing any confusion with any other seqno used for tracking
pipelines.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5233>

nir: lower_tex: Don't normalize coordinates for TXF with RECT

v2: remove the option to actually request normalization and its
    application in Intel < Gen6 (Jason)

v3: Also don't lower for query operations (Jason)

Fixes: 1ce8060c25c7f2c7a54159fab6a6974c0ba182a8
    nir/lower_tex: support for lowering RECT textures

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5105>

ci: Quick exit qpa extraction for non-matching qpas.

When you're bringing up a new driver in CI with significant number of
failures (or when a CI run breaks a driver), the QPA extraction can easily
take the whole job timeout as we go about processing each QPA (100 of them
in my early VK CI fails) per unexpected result we're saving (50), which
involves reading and each line of the file in shell.  By quickly filtering
out the QPA files not including our test, we can save all that shell
overhead, bringing QPA extract time down to a couple of minutes.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

ci: Move baremetal DEQP_NO_SAVE_RESULTS setup to the yml.

I'm going to want it unset (artifacts enabled) for the cheza jobs.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

ci: Add DEQP_EXPECTED_RENDERER support for VK tests.

I used this to debug what was going on with freedreno VK in CI.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

ci: Auto-detect the architecture for VK ICD filenames.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

ci: Drop old comment about enabling --deqp-watchdog.

The parallel deqp runner does its own 60s watchdog.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

ci: Drop double ".txt" suffix on the unexpected results file.

Just a cosmetic fix in reviewing logs.

Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>

spirv,radv,anv: implement no-op VK_GOOGLE_user_type

This extension only allows HLSL shader compilers to optionally embed
unambiguous type information which can be safely ignored by the driver.

This fixes a crash with the recent Vulkan backend of Path Of Exile
(it uses the extension without checking if it's supported).

Cc: <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Edmondo Tommasina <edmondo.tommasina@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5237>

aco: fix 64-bit shared_atomic_exchange

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

aco: don't reorder barriers in the scheduler

Unless we're reordering it around a barrier of the same type

No shader-db changes.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

aco: preserve more fields when combining additions into SMEM

Totals from 11 (0.01% of 127638) affected shaders:

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa780 ('aco: Initial commit of independent AMD compiler')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

aco: check instruction format before waiting for a previous SMEM store

Totals from 7 (0.01% of 127638) affected shaders:
CodeSize: 40336 -> 40320 (-0.04%)
Instrs: 7807 -> 7803 (-0.05%)
Cycles: 118588 -> 118344 (-0.21%); split: -0.23%, +0.02%
SMEM: 331 -> 339 (+2.42%)

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 1749953ea3 ('aco/gfx10: Wait for pending SMEM stores before loads')
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4880>

aco: consider SDWA during value numbering

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 23ac24f5b1fdde73cf8ec1ef6cbe08d73d6776f5
   ('aco: add missing conversion operations for small bitsizes')

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>

aco: fix interaction with 3f branch workaround and p_constaddr

The offset was incorrect if we inserted a nop before the p_constaddr.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Fixes: 93c8ebfa ('aco: Initial commit of independent AMD compiler')
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5164>

gitlab-ci: Pull in GCC 9 from Debian testing in x86_test-gl/vk images

The GCC 8 packages from buster are no longer compatible with libc6 from
testing. We could use the GCC 8 packages from testing instead, but this
is easier.

v2:
* Update piglit-quick_gl test results, due to the piglit issue fixed by
  https://gitlab.freedesktop.org/mesa/piglit/-/merge_requests/294

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

gitlab-ci: x86_test-base image as common base for x86_test-gl/vk

Making use of the relatively recent FDO_BASE_IMAGE feature of the
templates, the x86_test-base image contents are shared as a separate
layer by the x86_test-gl/vk images (meaning the former only needs to be
downloaded once for either or both of the latter). This should be more
efficient in terms of overall network bandwidth and storage, in
particular if the base image changes less often than the -gl/vk ones.

v2:
* List x86_test-base in needs: along with x86_test-gl/vk (see parent
  commit)
* Always put $STABLE/TESTING_EPHEMERAL on separate lines, will make it
  easier to add any non-ephemeral packages

Reviewed-by: Eric Anholt <eric@anholt.net> # v1
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

gitlab-ci: Also list arm/x86_build in needs: of test jobs

Without this, the test jobs may spuriously run if the arm/x86_build
jobs fail.

Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5186>

intel: Add helper to calculate GPGPU_WALKER::RightExecutionMask

Suggested by Jason.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

iris, i965: Update limits for ARB_compute_variable_group_size

The CS compiler now produces multiple SIMD variants, so the previous
trade-off between "always using SIMD32" and "having a smaller max
invocations" is now gone.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

iris, i965: Drop max_variable_local_size

This was used to decide which SIMD width to generate code for
ARB_compute_variable_group_size.  Now that compiler will generate
multiple SIMD widths, this information is unused.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

intel/fs: Generate multiple CS SIMD variants for variable group size

This will make the GL drivers pick the right SIMD variant for a given
group size set during dispatch.  The heuristic implemented in
brw_cs_simd_size_for_group_size() is the same as in brw_compile_cs().

The cs_prog_data::simd_size field was removed.  The generated SIMD
sizes are marked in a bitmask, which is already used via
brw_cs_simd_size_for_group_size() by the drivers.

When in variable group size, it is OK if larger SIMD shader spill,
since we'd need it for the cases where the smaller one can't hold all
the invocations.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

anv: Use new helper functions to pick SIMD variant for CS

Also combine the existing individual anv helpers into a single one for
all CS related parameters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

iris: Use new helper functions to pick SIMD variant for CS

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

iris: Set CS KernelStatePointer at dispatch

There's an update for INTERFACE_DESCRIPTOR_DATA at dispatch, so we can
just move the KSP assignment there.  This flexibility will later allow
variable group size to pick the right SIMD variant.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

i965: Use new helper functions to pick SIMD variant for CS

Also expand the existing i965 helper to return the other CS related
paramters.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

intel/fs: Add helper to get prog_offset and simd_size

This indirection will be used by the variable group size case in a
later change.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

intel/fs: Support INTEL_DEBUG=no8,no32 in compute shaders

The "no32" flag will have precedence over "do32", like is done for FS.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

intel/fs: Remove min_dispatch_width spilling decision from RA

Move the decision one level up, let brw_compile_*() functions use the
spilling information to decide whether or not a certain width
compilation can spill (passed via run_*() functions).

The min_dispatch_width was used to compare with the dispatch_width and
decide whether "a previous shader is already available, so don't
accept spill".

This is replaced by:

- Not calling run_*() functions if it is know beforehand a smaller width
  already spilled -- since the larger width will spill and fail;

- Explicitly passing whether or not a shader is allowed to spill.  For
  the cases where the smaller width is available and haven't spilled,
  the larger width will be compiled but is only useful if it won't
  spill.

Moving the decision to this level will be useful later for variable
group size, which is a case where we want all the widths to be allowed
to spill.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5142>

docs: update calendar, add news item, and link releases notes for 20.1.0

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>

docs: Add release notes for 20.1.0

Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5234>

zink: always use logical eq ops in ntv with 1bit inputs

integer and float compare ops cannot take boolean types, so the bit size
of the inputs should be checked here so that we can swap to the logical
equality functions if we're being passed a bool value

resolves tons of validator errors in glsl piglit tests

Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5231>

pan/bi: Initialize struct fma_op_info member extended.

Fix warning reported by Coverity Scan.

Uninitialized scalar variable (UNINIT)
uninit_use: Using uninitialized value info. Field info.extended is
uninitialized.

Fixes: 8c79c710d4e1 ("pan/bi: Identify extended FMA opcodes")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5224>

lima/ppir: use a ready list in node_to_instr

After the recent optimizations in ppir lowering that increase options
for combining, node_to_instr now may have multiple options of nodes to
insert and needs to decide which is better.
For example, if an instruction uses both a varying and a texture, there
are two nodes nodes that can be inserted to the load varying slot in the
same instruction (ld_var and ld_coords). It is much more advantageous to
pipeline the load texture coords since that enables the higher precision
path for texture coordinates. However, with the current recursive
expansion, this cannot be influenced.

This simple ready list implementation in node_to_instr allows it to
choose the next node to expand based on a priority score, rather than
relying on the random order coming from the recursive expansion.

Other than preferring nodes with pipeline output (which covers ld_coords
vs ld_var), nodes using later slots in the pipeline are now expanded
first, allowing node_to_instr to make all of the earlier (pipelineable)
nodes available in the ready list so the best one can be chosen when
picking nodes for the earlier slots.

Fixes: 632a921bd0d lima/ppir: optimize tex loads with single successor
Signed-off-by: Erico Nunes <nunes.erico@gmail.com>
Reviewed-by: Vasily Khoruzhick <anarsoul@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5092>

pan/bi: Suppress inf/nan for now

This is a (hopefully temporary) hack. The blob does it for ES2 at any
rate.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Add CSEL.16 packing tests

Passing but let's increase coverage.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Pack compact vertex texturing

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Add f16 TEXC.vtx op

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Allow vertex txl with lod=0 as compact

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Document compute_lod bit for compact tex

At least I assume this works this way.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Also add compact vertex texturing

This implies lod=0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/bi: Add TEX.vtx opcode for vertex texturing

Always has an LOD.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

pan/decode: Decode Bifrost shader flags

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Set MALI_BIFROST_EARLY_Z as necessary

Fixes blending.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Identify MALI_BIFROST_EARLY_Z flag

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Add defines for bifrost unk1 flags

Instead of open-coding.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Document Midgard Inf/NaN suppress bit

We should probably not be setting this..

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Ensure nonlinear strides are 16-aligned

To match how they are encoded.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: bde19c0e7ba ("panfrost: Fix tiled texture "stride"s on Bifrost")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Identify Bifrost texture format swizzle

We don't force w=1 for Bifrost textures. We already compose this into
the swizzle as necessary, so we can just ignore this field I think. But
let's identify it so we don't forget what it is.

The blob uses it to force w=1 for <= 3-channel formats (0x10), as well
as a flag to swap r/b for BGRA (0x4). There are probably other flags
here but it doesn't.. really matter to us.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Set unk2 to accomodate blending

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Share MRT blend flag calculation with Bifrost

As far as I know the field is the same.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Force Z/S tiling on Bifrost

Like we do on SFBD since we don't know the format bits yet.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Tweak Bifrost colour buffer magic

For tiled or linear.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Tweak zsbuf magic numbers for Bifrost

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Adjust null_rt for Bifrost

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

panfrost: Fix Bifrost blending with depth-only FBO

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5232>

ac/gpu_info: Correct Acturus cu bitmap

The cu bitmap in amd gpu info structure is
4x4 size array, and it's usually suitable for Vega
ASICs which has 4*2 SE/SH layout.
But for Arcturus, SE/SH layout is changed to 8*1.
To mostly reduce the impact, we make it compatible
with current bitmap array as below:
SE4,SH0 --> cu_bitmap[0][1]
SE5,SH0 --> cu_bitmap[1][1]
SE6,SH0 --> cu_bitmap[2][1]
SE7,SH0 --> cu_bitmap[3][1]

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5212>

intel/fs: Work around dual-source blending hangs in combination with SIMD16

It was found that dual-source blending hangs with SIMD16 dispatch in some
specific but unknown situation. Which in the wild happen when rgba
anti-aliasing is enabled for fonts.

Cc: <mesa-stable@lists.freedesktop.org>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2183
Signed-off-by: Danylo Piliaiev <danylo.piliaiev@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5037>

zink: use general-layout when blitting to/from same resource

This avoids a validator warning when for instance generating mipmaps.

Fixes: d2bb63c8d4c ("zink: Use optimal layout instead of general. Reduces valid layer warnings. Fixes RADV image noise.")
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5199>

radeonsi/drirc: enable zerovram option for 7 Days to Die

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2686
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5168>

turnip: support VkImageDrmFormatModifierExplicitCreateInfoEXT

This will be used to import images which have different layout from what
turnip uses by default. For example non-UBWC (linear) images from the video
decoder on some hardware have a 512 pitch alignment.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>

freedreno/layout: add explicit offset/pitch argument to fdl6_layout

fdl6_layout will return false when the explicit pitch is not valid.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4596>

glsl: fix slow linking of uniforms in the nir linker

Currently the nir linker resizes the amount of storage needed to hold
uniform information on the fly while linking. As shaders can contain
thousands of uniforms this can be very slow. For example some Godot
shaders can take 30 seconds to compile on some machines.

In this change we count the amount of storage needed before we start
processing the uniforms. This is what the GLSL IR linker does also.

Fixes: 95f555a93a88 ("st/glsl_to_nir: make use of nir linker for linking uniforms")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2996
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5137>

glsl: stop cascading errors if process_parameters() fails

Generally we do not completely stop compilation as soon as we see an error,
instead we continue on to attemp to find any futher errors.

This means we shouldn't be checking state->error to see if any error has
happened during the compilation process, doing so was causing
process_parameters() to fail on completely valid functions if there was
any error found in the shader previously. This then caused the valid
functions not to be found because the paramlist was considered empty,
resulting in the compiler spewing out misleading error messages.

Here we simply add the IR error value to the param list when we have
an issue with processing a parameter, this leads to much better error
messaging.

Fixes: 53e4159eaaf6 ("glsl: stop processing function parameters if error happened")
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5205>

freedreno: Add missing va_end.

Fix warning reported by Coverity Scan.

Missing varargs init or cleanup (VARARGS)
missing_va_end: va_end was not called for ap.

Fixes: a0ca1462f317 ("freedreno: add logging infrastructure")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5221>

nir: Fix sources for image atomic fadd

Somehow we ended up with an extra scalar source up-front.  It doesn't
look like any drivers use this opcode yet so no real harm has been done
by it being wrong.

Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5218>

pan/decode: Dump unknown2

Looks to be 0.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>

pan/decode: Dump missing field on Bifrost

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>

pan/decode: Fix tiler warning

../src/panfrost/pandecode/decode.c:1176:60: warning: taking address of
packed member of ‘struct mali_framebuffer’ may result in an unaligned
pointer value [-Waddress-of-packed-member]
 1176 |
      pandecode_midgard_tiler_descriptor(&fb->tiler, fb->width1 + 1,
fb->height1 + 1, is_fragment, true);

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>

pan/decode: Fix unused variable warning

Check unused for now.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5219>

nouveau: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

etnaviv: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

iris: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

i965: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

intel: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

softpipe: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

panfrost: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

glsl: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

gallium/draw: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

mesa/swrast: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

mesa: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

util/format: Use SATURATE

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

util: Add SATURATE macro

Equivalent to clamp(x, 0.0, 1.0) or fsat in NIR. Useful for format
packing, among other uses given the variety of substituions in-tree.

v2: Drop brackets (Eric).

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5100>

intel/fs: Remove redundant assert()

This is covered by the two previous similar asserts.  Each time `v` is
assigned this is asserted.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>

intel/fs: Early return when can't satisfy explicit group size

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>

intel/fs: Remove unused state from brw_nir_lower_cs_intrinsics

After 2663759af0e ("intel/fs: Add and use a new load_simd_width_intel
intrinsic") the local_workgroup_size is not used anymore except for
assertions at the pass' start, so drop it from state struct.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>

intel/fs: Remove unused emission of load_simd_with_intel

The nir_intrinsic_load_simd_width_intel is always lowered by the
brw_nir_lower_simd() pass before the emission happens.  This is likely
a "leftover" from patch rewriting/squashing that happened when this
intrinsic was added.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5213>

egl/android: Drop unused variable

src/egl/drivers/dri2/platform_android.c:332:29: warning: unused
variable 'dri2_dpy' [-Wunused-variable]

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>

egl/android: Move get_format under HAVE_DRM_GRALLOC guard where it's used

src/egl/drivers/dri2/platform_android.c:159:12: warning: unused
function 'get_format' [-Wunused-function]

Reviewed-by: Rob Clark <robdclark@chromium.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5174>