Update README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

More testing

Fix spacing

Add quick-and-dirty specify tests

Merge remote-tracking branch 'origin/master' into clifford/specify

Rename cells_map.v to prevent clash with ff_map.v

iverilog with simcells.v as well

Merge pull request #969 from YosysHQ/clifford/pmgenstuff

Improve pmgen, Add "peepopt" pass with shift-mul pattern

Merge pull request #984 from YosysHQ/eddie/fix_982

dffinit to do nothing when (* init *) value is 1'bx

Revert "synth_xilinx to call dffinit with -noreinit"

This reverts commit 1f62dc9081feb4852b1848d01951f631853edb38.

If init is 1'bx, do not add to dict as per @cliffordwolf

Revert "dffinit -noreinit to silently continue when init value is 1'bx"

This reverts commit aa081f83c791b1d666214776aaf744a80ce6a690.

Merge pull request #976 from YosysHQ/clifford/fix974

Fix width detection of memory access with bit slice

Merge pull request #985 from YosysHQ/clifford/fix981

Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires

Fix typo in tests/svinterfaces/runone.sh

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #979 from jakobwenzel/svinterfacesTestcase

fail svinterfaces testcases on yosys error exit

Improve opt_expr and opt_clean handling of (partially) undriven and/or unused wires, fixes #981

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Update pmgen documentation

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix typo

Signed-off-by: Clifford Wolf <clifford@clifford.at>

synth_xilinx to call dffinit with -noreinit

dffinit -noreinit to silently continue when init value is 1'bx

fail svinterfaces testcases on yosys error exit

Merge pull request #963 from YosysHQ/eddie/synth_xilinx_fine

Revert synth_xilinx 'fine' label more to how it used to be...

Merge pull request #978 from ucb-bar/fmtfirrtl

Re-indent firrtl.cc:struct memory - no functional change.

Back to passing all xc7srl tests!

Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine

Merge branch 'master' of github.com:YosysHQ/yosys

Re-indent firrtl.cc:struct memory - no functional change.

Merge branch 'clifford/fix883'

Add missing enable_undef to "sat -tempinduct-def", fixes #883

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #977 from ucb-bar/fixfirrtlmem

Fix #938 - Crash occurs in case when use write_firrtl command

Fix #938 - Crash occurs in case when use write_firrtl command
Add missing memory initialization.
Sanity-check memory parameters.
Add Cell pointer to memory object (for error reporting).

Fix floating point exception in qwp, fixes #923

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add splitcmplxassign test case and silence splitcmplxassign warning

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix width detection of memory access with bit slice, fixes #974

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix segfault in wreduce

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Disabled "final loop assignment" feature

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #972 from YosysHQ/clifford/fix968

Add final loop variable assignment when unrolling for-loops

Merge pull request #966 from YosysHQ/clifford/fix956

Drive dangling wires with init attr with their init value

Merge pull request #962 from YosysHQ/eddie/refactor_synth_xilinx

Refactor synth_xilinx to auto-generate doc

Merge branch 'master' into eddie/refactor_synth_xilinx

Merge pull request #973 from christian-krieg/feature/python_bindings

Feature/python bindings cleanup

Include filename in "Executing Verilog-2005 frontend" message, fixes #959

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Fix performance bug in RTLIL::SigSpec::operator==(), fixes #970

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add final loop variable assignment when unrolling for-loops, fixes #968

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add handling of init attributes in "opt_expr -undriven"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge branch 'master' of https://github.com/YosysHQ/yosys into feature/python_bindings

Cleaned up root directory

Add peepopt_muldiv, fixes #930

Signed-off-by: Clifford Wolf <clifford@clifford.at>

pmgen progress

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Run "peepopt" in generic "synth" pass and "synth_ice40"

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Some pmgen reorg, rename peepopt.pmg to peepopt_shiftmul.pmg

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Progress in shiftmul peepopt pattern

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #960 from YosysHQ/eddie/equiv_opt_undef

Add -undef option to equiv_opt, passed to equiv_induct

Merge pull request #967 from olegendo/depfile_esc_spaces

escape spaces with backslash when writing dep file

Add "peepopt" skeleton

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add pmgen support for multiple patterns in one matcher

Signed-off-by: Clifford Wolf <clifford@clifford.at>

fix codestyle formatting

Support multiple pmg files (right now just concatenated together)

Signed-off-by: Clifford Wolf <clifford@clifford.at>

escape spaces with backslash when writing dep file

filenames are sparated by spaces in the dep file.  if a filename in the
dep file contains spaces they must be escaped, otherwise the tool that
reads the dep file will see multiple wrong filenames.

Drive dangling wires with init attr with their init value, fixes #956

Copy with 1'bx padding in $shiftx

WIP

Move neg-pol to pos-pol mapping from ff_map to cells_map.v

Revert synth_xilinx 'fine' label more to how it used to be...

Where did this check come from!?!

Refactor synth_xilinx to auto-generate doc

Cleanup ice40

Add -undef option to equiv_opt, passed to equiv_induct

Misspelling

Add specify support to README

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Improve $specrule interface

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add $specrule cells for $setup/$hold/$skew specify rules

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Preserve $specify[23] cells

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Allow $specify[23] cells in blackbox modules

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Rename T_{RISE,FALL}_AVG to T_{RISE,FALL}_TYP to better match verilog std nomenclature

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add $specify2/$specify3 support to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add support for $assert/$assume/$cover to write_verilog

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add CellTypes support for $specify2 and $specify3

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add InternalCellChecker support for $specify2 and $specify3

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Checking and fixing specify cells in genRTLIL

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Un-break default specify parser

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add specify parser

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Add $specify2 and $specify3 cells to simlib

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #957 from YosysHQ/oai4fix

Fixes for OAI4 cell implementation

Fixes for OAI4 cell implementation

Fixes #955 and the underlying issue in #954

Signed-off-by: David Shah <dave@ds0.me>

Format some names using inline code

Fix spelling

Remove some left-over log_dump()

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge pull request #914 from YosysHQ/xc7srl

synth_xilinx to now infer SRL16E/SRLC32E

Update help message

Merge pull request #952 from YosysHQ/clifford/fix370

Determine correct signedness and expression width in for-loop unrolling

Merge pull request #951 from YosysHQ/clifford/logdebug

Add log_debug() framework

Merge pull request #949 from YosysHQ/clifford/pmux2shimprove

Add full_pmux feature to pmux2shiftx

Merge pull request #953 from YosysHQ/clifford/fix948

Add support for zero-width signals to Verilog back-end

Move 'shregmap -tech xilinx' into map_cells

Add support for zero-width signals to Verilog back-end, fixes #948

Signed-off-by: Clifford Wolf <clifford@clifford.at>

Merge remote-tracking branch 'origin/master' into xc7srl

Determine correct signedness and expression width in for loop unrolling, fixes #370

Signed-off-by: Clifford Wolf <clifford@clifford.at>