Ron Dreslinski [Fri, 20 Oct 2006 00:02:57 +0000 (20:02 -0400)]
Fixes to get single level uni-coherence to work.
Now to try L2 caches in FS.
src/mem/cache/base_cache.hh:
Fix uni-coherence for atomic accesses in coherence protocol access to port
src/mem/cache/cache_impl.hh:
Properly handle uni-coherence
src/mem/cache/coherence/simple_coherence.hh:
Properly forward invalidates (not done for MSI+ protocols (assumed top level for now)
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Properly forward invalidates in atomic/timing uni-coherence
--HG--
extra : convert_revision :
f0f11315e8e7f32c19d92287f6f9c27b079c96f7
Ron Dreslinski [Thu, 19 Oct 2006 23:00:43 +0000 (19:00 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
c6611b32537918f5bf183788227ddf69a9a9a069
Ron Dreslinski [Thu, 19 Oct 2006 23:00:27 +0000 (19:00 -0400)]
Always get the functional access from the highest level of cache first.
src/mem/cache/cache_impl.hh:
Get the read data from the highest level of cache on a functional access
--HG--
extra : convert_revision :
7437ac46fb40f3ea3b42197a1aa8aec62af60181
Ron Dreslinski [Thu, 19 Oct 2006 22:29:42 +0000 (18:29 -0400)]
Also mark the packet as successful.
--HG--
extra : convert_revision :
2c38c209d2f5cb0ee2f8e55fce6ee4400529d547
Ron Dreslinski [Thu, 19 Oct 2006 18:55:54 +0000 (14:55 -0400)]
Properly update the state in the cache block on functional access.
Mark as satisfied for functional snoops.
--HG--
extra : convert_revision :
f75309c3436044a64caff097e2a585363cd004c3
Steve Reinhardt [Thu, 19 Oct 2006 17:33:08 +0000 (13:33 -0400)]
Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/newmem
into zizzer.eecs.umich.edu:/z/stever/bk/newmem-head
--HG--
extra : convert_revision :
8a70922250092c013fa4db6d83254b438ee6c4be
Steve Reinhardt [Thu, 19 Oct 2006 17:32:08 +0000 (10:32 -0700)]
Add "All" compund flag to enable all defined trace flags.
--HG--
extra : convert_revision :
dcc699d8341f762dee659290cd35206e326e1179
Steve Reinhardt [Thu, 19 Oct 2006 17:21:23 +0000 (10:21 -0700)]
Add new event priority for trace enable events so
that tracing gets turned on as the very first thing
in the selected cycle (tick).
--HG--
extra : convert_revision :
c08f749ca42782af1b48e5aa5f0860bf7076bd3c
Steve Reinhardt [Thu, 19 Oct 2006 07:33:33 +0000 (00:33 -0700)]
First cut at LL/SC support in caches (atomic mode only).
configs/example/fs.py:
Add MOESI protocol to caches (uni coherence not quite working w/FS yet).
--HG--
extra : convert_revision :
7bef7d9c5b24bf7241cc810df692408837b06b86
Lisa Hsu [Wed, 18 Oct 2006 22:04:53 +0000 (18:04 -0400)]
how did i not commit this already? the other way doesn't seem to work, need to convert to System ptr first to access System method.
src/python/m5/SimObject.py:
how did i not commit this already? the other way doesn't seem to work.
--HG--
extra : convert_revision :
55737d3d10742a1913a376d1febbc5809f2fab8f
Lisa Hsu [Wed, 18 Oct 2006 22:01:33 +0000 (18:01 -0400)]
need some initializations before doing the loop.
--HG--
extra : convert_revision :
e5e8b16ae4f119c923d8c0d295aa9569d7a8fe5b
Lisa Hsu [Wed, 18 Oct 2006 21:59:11 +0000 (17:59 -0400)]
only do this assert after you know you're not switched out or idle.
--HG--
extra : convert_revision :
0cd0d31db44fe7e8e44bde90e1756873faca422f
Ron Dreslinski [Wed, 18 Oct 2006 20:38:02 +0000 (16:38 -0400)]
Fix WriteInvalidateResp
--HG--
extra : convert_revision :
ac4281944202a9a2f166b305a1eaea507e484bcc
Ron Dreslinski [Wed, 18 Oct 2006 17:34:52 +0000 (13:34 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
9e47881686a6c060fa28e7edfd9a0b556099bf30
Steve Reinhardt [Wed, 18 Oct 2006 15:41:05 +0000 (08:41 -0700)]
Break a lot of overly long lines.
Factor out some asserts that were on both
sides of an if/else.
--HG--
extra : convert_revision :
78f0c2d76a81a98216b2f281159c6b6ea0147731
Steve Reinhardt [Wed, 18 Oct 2006 15:24:24 +0000 (08:24 -0700)]
Get rid of doData() lines (were already commented out).
Reindent due to resulting changes in nesting.
--HG--
extra : convert_revision :
6be099d572efb618efb08fbc06d7e0e4b5b4cab2
Steve Reinhardt [Wed, 18 Oct 2006 15:16:22 +0000 (08:16 -0700)]
Get rid of obsolete in-cache copy support.
--HG--
extra : convert_revision :
a701ed9d078c67718a33f4284c0403a8aaac7b25
Steve Reinhardt [Wed, 18 Oct 2006 06:30:11 +0000 (23:30 -0700)]
Add --caches option to add caches to server CPUs.
--HG--
extra : convert_revision :
6aa97dcc807e175215e73c638faf73be926d4cd4
Steve Reinhardt [Wed, 18 Oct 2006 04:16:17 +0000 (21:16 -0700)]
Include packet_impl.hh (need this on my laptop,
but not on zizzer... g++ 4 thing maybe?)
--HG--
extra : convert_revision :
31c49f1c55fe9daf6365411bfb5bb7f6ccc8032d
Steve Reinhardt [Wed, 18 Oct 2006 04:15:11 +0000 (21:15 -0700)]
Enable MP systems via cmd-line flag in fs.py.
configs/example/fs.py:
Add flag for MP server systems.
src/python/m5/objects/AlphaConsole.py:
src/python/m5/objects/IntrControl.py:
Change CPU from 'any' to 'cpu[0]' to work better with MP sytems.
tests/configs/tsunami-simple-atomic-dual.py:
tests/configs/tsunami-simple-timing-dual.py:
Don't need to set console & intrcontrol cpu
params anymore (default is fixed now).
--HG--
extra : convert_revision :
9417b12b1b395ff7d6a9f2894e4123923c754daf
Ali Saidi [Tue, 17 Oct 2006 23:38:36 +0000 (19:38 -0400)]
add code to serialize se structures. Lisa is working on the python side of things and will test
src/mem/page_table.cc:
src/mem/page_table.hh:
add code to serialize/unserialize page table
src/sim/process.cc:
src/sim/process.hh:
add code to serialize/unserialize process
--HG--
extra : convert_revision :
ee9eb5e2c38c5d317a2f381972c552d455e0db9e
Ron Dreslinski [Tue, 17 Oct 2006 22:50:19 +0000 (18:50 -0400)]
Fixes for uni-coherence in timing mode for FS.
Still a bug in atomic uni-coherence in FS.
src/cpu/o3/fetch_impl.hh:
src/cpu/o3/lsq_impl.hh:
src/cpu/simple/atomic.cc:
src/cpu/simple/timing.cc:
Make CPU models handle coherence requests
src/mem/cache/base_cache.cc:
Properly signal coherence CSHRs
src/mem/cache/coherence/uni_coherence.cc:
Only deallocate once
--HG--
extra : convert_revision :
c4533de421c371c5532ee505e3ecd451511f5c99
Ron Dreslinski [Tue, 17 Oct 2006 20:47:22 +0000 (16:47 -0400)]
Fixes to cache eliminating the assumption that the Packet is still valid after sending out a request.
Still need to rework upgrades into this system, but works for now.
src/mem/cache/base_cache.cc:
Re order code to be more readable
src/mem/cache/base_cache.hh:
Be sure to delete the copy on a bus block
src/mem/cache/cache_impl.hh:
Be sure to remove the copy on a writeback success
src/mem/cache/miss/mshr_queue.cc:
Demorgans to make it easier to understand
src/mem/tport.cc:
Delete writebacks
--HG--
extra : convert_revision :
9519fb37b46ead781d340de29bb342a322a6a92e
Ron Dreslinski [Tue, 17 Oct 2006 19:07:40 +0000 (15:07 -0400)]
Properly chack the pkt pointer on upgrades to insure no segfaults when writebacks delete the packet.
--HG--
extra : convert_revision :
72b1c6296a16319f4d16c62bc7038365654dbc40
Ron Dreslinski [Tue, 17 Oct 2006 19:05:21 +0000 (15:05 -0400)]
Fix it so that the cache does not assume to gave the packet it sent out via sendTiming.
Still need to fix upgrades to use this path
src/mem/cache/base_cache.cc:
Copy the pkt to the MSHR before issuing the sendTiming where it may be changed/consumed
src/mem/cache/cache_impl.hh:
Use copy of packet, because sendTiming may have changed the pkt
Also, delete the copy when the time comes
--HG--
extra : convert_revision :
635cde6b4f08d010affde310c46b1caf50fbe424
Ron Dreslinski [Tue, 17 Oct 2006 18:28:17 +0000 (14:28 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
e33d535feb0c3d975dc043efdc86efe0df05800c
Steve Reinhardt [Tue, 17 Oct 2006 18:08:49 +0000 (11:08 -0700)]
Rename 'Machine' to 'SysConfig'.
Clean up a little.
--HG--
extra : convert_revision :
db5f36776209c76a593205c46b08aa147358f33a
Ron Dreslinski [Tue, 17 Oct 2006 18:05:23 +0000 (14:05 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
c3650273684f3fbdcd2e14e95d09ee3c6de8d6b6
Steve Reinhardt [Sat, 14 Oct 2006 06:09:05 +0000 (02:09 -0400)]
Get rid of unused CacheBlk << output operator.
--HG--
extra : convert_revision :
d5c0aadc35edf5c9495afcd3375f1f64716ef845
Gabe Black [Fri, 13 Oct 2006 23:09:46 +0000 (19:09 -0400)]
Merge 141.212.106.238:/home/gblack/m5/newmem_bus
into zizzer.eecs.umich.edu:/.automount/wexford/x/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
ff15f3805a9ed9aa81e92013d5b57399a30720bb
Gabe Black [Fri, 13 Oct 2006 22:59:29 +0000 (18:59 -0400)]
Fix stats for new bus model
--HG--
extra : convert_revision :
c081754c8eb8fa5b8e7336deb3fefb545789b8ac
Kevin Lim [Fri, 13 Oct 2006 21:35:23 +0000 (17:35 -0400)]
Fix assertion. I haven't tested it fully (I can't reproduce Lisa's error) but I believe it should fix what she's running into (which was definitely a bug).
src/cpu/o3/fetch_impl.hh:
Move assertion to area where it should really always be true. Sometimes you might recvRetry and not necessarily be blocked (if there was a squash).
--HG--
extra : convert_revision :
76ad35357e7f4c44fa544ffed071096a62053018
Ron Dreslinski [Fri, 13 Oct 2006 19:47:35 +0000 (15:47 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
f62790e46a7e3eb88a6f8c7bfaa08526285248a3
Ron Dreslinski [Fri, 13 Oct 2006 19:47:05 +0000 (15:47 -0400)]
Fix for DMA's in FS caches.
Fix CSHR's for flow control.
Fix for Bus Bridges reusing packets (clean flags up)
Now both timing/atomic caches with MOESI in UP fail at same point.
src/dev/io_device.hh:
DMA's should send WriteInvalidates
src/mem/bridge.cc:
Reusing packet, clean flags in the packet set by bus.
src/mem/cache/base_cache.cc:
src/mem/cache/base_cache.hh:
src/mem/cache/cache.hh:
src/mem/cache/cache_impl.hh:
src/mem/cache/coherence/simple_coherence.hh:
src/mem/cache/coherence/uni_coherence.cc:
src/mem/cache/coherence/uni_coherence.hh:
Fix CSHR's for flow control.
src/mem/packet.hh:
Make a writeInvalidateResp, since the DMA expects responses to it's writes
--HG--
extra : convert_revision :
59fd6658bcc0d076f4b143169caca946472a86cd
Ali Saidi [Fri, 13 Oct 2006 18:28:46 +0000 (14:28 -0400)]
fix a bug in CopyStringOut. dprintk appears to work again.
--HG--
extra : convert_revision :
cd0d13a85ddc7599308db8604a8f63a48679cc05
Lisa Hsu [Thu, 12 Oct 2006 22:56:57 +0000 (18:56 -0400)]
Merge zizzer:/bk/newmem
into zed.eecs.umich.edu:/z/hsul/work/m5/newmem
src/cpu/simple/timing.cc:
hand merge
--HG--
extra : convert_revision :
083bf102249ad9bc63c447dbf85d3863f935f647
Ali Saidi [Thu, 12 Oct 2006 19:30:30 +0000 (15:30 -0400)]
replace functional code in tport with fixPacket().
fixPacket() should be used anywhere a functional packet and timing packet are found to have the same address.
--HG--
extra : convert_revision :
783ec438271b24ddb0ae742b4efd1ed7d6be93f3
Korey Sewell [Thu, 12 Oct 2006 19:05:29 +0000 (15:05 -0400)]
Merge zizzer:/bk/newmem
into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo
--HG--
extra : convert_revision :
f02fd56fc1ec658fe2a81d0e0b0d053b7606f7f2
Korey Sewell [Thu, 12 Oct 2006 19:04:14 +0000 (15:04 -0400)]
config file updates
--HG--
extra : convert_revision :
b873e0b436d71d86b87b8d9df7115bcc7ceb2b50
Ron Dreslinski [Thu, 12 Oct 2006 19:02:56 +0000 (15:02 -0400)]
Fix CSHR retrys
--HG--
extra : convert_revision :
caa7664f6c945396fa38ce62fbda018ebed4eaa6
Ali Saidi [Thu, 12 Oct 2006 19:02:50 +0000 (15:02 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
--HG--
extra : convert_revision :
0e184a0784100112db5841c587bd3dd638f8bdc0
Ali Saidi [Thu, 12 Oct 2006 19:02:25 +0000 (15:02 -0400)]
small bus updates for functional accesses
--HG--
extra : convert_revision :
c7a6b199c74ed4b4ffab14bbffb51e72d75b7742
Korey Sewell [Thu, 12 Oct 2006 18:36:41 +0000 (14:36 -0400)]
Merge zizzer:/bk/newmem
into zooks.eecs.umich.edu:/y/ksewell/research/m5-sim/cleanrepo
--HG--
extra : convert_revision :
86abc4dabb7c72edc90fae951314d6a6b5c73705
Korey Sewell [Thu, 12 Oct 2006 18:36:21 +0000 (14:36 -0400)]
Add test binary & inputs
--HG--
extra : convert_revision :
efc0249ae6f51b9f4f49741aafb2cad21e1fb11e
Ron Dreslinski [Thu, 12 Oct 2006 18:31:31 +0000 (14:31 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
fa5b2cfa79d87a0612b8116d407a8b2959d9095a
Ron Dreslinski [Thu, 12 Oct 2006 18:21:25 +0000 (14:21 -0400)]
Remove bus and top level parameters from cache
src/mem/cache/base_cache.hh:
Remove top level param from cache
src/mem/cache/coherence/uni_coherence.cc:
Remove top level parameters from the cache
--HG--
extra : convert_revision :
4437aeedc20866869de7f9ab123dfa7baeebedf0
Ali Saidi [Thu, 12 Oct 2006 18:18:42 +0000 (14:18 -0400)]
Merge zizzer:/bk/newmem
into zeep.pool:/z/saidi/work/m5.newmem.head
src/mem/packet.hh:
hand merge
--HG--
extra : convert_revision :
3f77707360235dc98c6b12a0367ca64a401313df
Ali Saidi [Thu, 12 Oct 2006 18:15:09 +0000 (14:15 -0400)]
add a traceflag for functional accesses
implement fix packet and add the ability to print a packet to a ostream
remove tabs in packet.hh (Could people stop inserting them??!?!?!)
mark const functions in packet.hh as such
src/base/traceflags.py:
add a traceflag for functional accesses
src/mem/packet.cc:
implement fix packet and add the ability to print a packet to a ostream
src/mem/packet.hh:
add the ability to print a packet to an ostream
remove tabs in file
mark const functions as such
--HG--
extra : convert_revision :
4297bce5e1d3abbab48be5bd9eb9e982b751fc7c
Ron Dreslinski [Thu, 12 Oct 2006 17:59:03 +0000 (13:59 -0400)]
Check the response queue on functional accesses.
The response queue is not tying up an MSHR, should we change that or assume infinite storage for responses?
src/mem/cache/base_cache.cc:
src/mem/tport.cc:
Add in functional check of retry queued packets.
--HG--
extra : convert_revision :
0cb40b3a96d37a5e9eec95312d660ec6a9ce526a
Ron Dreslinski [Thu, 12 Oct 2006 17:45:28 +0000 (13:45 -0400)]
Another memleak in the memtester (need [] with the delete)
src/cpu/memtest/memtest.cc:
Another memleak in the memtester
--HG--
extra : convert_revision :
f7ab079e90d578fb6b9d1ff238d049fcce55b01b
Ron Dreslinski [Thu, 12 Oct 2006 17:43:12 +0000 (13:43 -0400)]
Fix a memory leak in the memtester
--HG--
extra : convert_revision :
93062b0f1a3ba7a5210e2f27099f20ae8f66522b
Ron Dreslinski [Thu, 12 Oct 2006 17:33:21 +0000 (13:33 -0400)]
Fix problems with unCacheable addresses in timing-coherence
src/base/traceflags.py:
src/mem/physical.cc:
Add debug falgs fro physical memory accesses
src/mem/cache/cache_impl.hh:
Snoops to uncacheable blocks should not happen
src/mem/cache/miss/miss_queue.cc:
Set the size properly on unCacheable accesses
--HG--
extra : convert_revision :
fc78192863afb11fc7c591fba169021b9e127d16
Ron Dreslinski [Thu, 12 Oct 2006 01:04:11 +0000 (21:04 -0400)]
Merge zizzer:/bk/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
b6224624ea493531e5ecc161bede7433f96d8a0f
Ron Dreslinski [Thu, 12 Oct 2006 00:54:06 +0000 (20:54 -0400)]
Make default ID unique (not broadcast)
Fix a segfault associated with DefaultId
src/mem/bus.cc:
Handle a segfault in the bus when DefaultPort was being used
src/mem/bus.hh:
Make the Default ID more unique (it overlapped with Broadcast ID)
--HG--
extra : convert_revision :
9182805c5cf4d9fe004e6c5be8547a8f41ed7bfe
Ron Dreslinski [Wed, 11 Oct 2006 23:47:11 +0000 (19:47 -0400)]
Forgot to mark myself as on the retry list
--HG--
extra : convert_revision :
c20170320a284a7bf143a929e4d3aa1475a8bfe0
Korey Sewell [Wed, 11 Oct 2006 23:26:56 +0000 (19:26 -0400)]
add spec2k tests
--HG--
extra : convert_revision :
619d6af7013b597ade6440f8cf84d6d099e31763
Ron Dreslinski [Wed, 11 Oct 2006 23:25:48 +0000 (19:25 -0400)]
Fix bus in FS mode.
src/mem/bus.cc:
Add debugging statement
src/mem/bus.hh:
Fix implementation of bus for subsequent recvTimings while handling a retry request.
src/mem/tport.cc:
Rework timing port to retry properly
--HG--
extra : convert_revision :
fbfb5e8b4a625e49c6cd764da1df46a4f336b1b2
Korey Sewell [Wed, 11 Oct 2006 23:07:10 +0000 (19:07 -0400)]
add bzip test-prog
--HG--
extra : convert_revision :
f5197172b094d59ced84423eb34c31ddf23689ee
Lisa Hsu [Wed, 11 Oct 2006 22:54:31 +0000 (18:54 -0400)]
System not global object, need to preface it with objects.
--HG--
extra : convert_revision :
5e105d7082a8c103fb5d5383c3093734bfd590f5
Lisa Hsu [Wed, 11 Oct 2006 22:53:50 +0000 (18:53 -0400)]
since memoryMode was put into the System (from SimObject), things got broken - this fixes it so that changeToTiming/changeToAtomic works.
src/python/m5/SimObject.py:
now that setMemoryMode is a method in System, need to convert the SimObject * _ccObject into a system ptr to call setMemoryMode.
src/sim/main.cc:
need this conversion now.
src/sim/sim_object.hh:
put the enum back into SimObject.
src/sim/system.hh:
memoryMode is now a part of SimObject, need the ::'s
--HG--
extra : convert_revision :
0ade06957fa57b497798e1f50c237ca1badc821d
Lisa Hsu [Wed, 11 Oct 2006 22:44:48 +0000 (18:44 -0400)]
some drain changes in timing (kevin's) and some memory mode assertion changes so that when you come out of resume, you only assert if you're really wrong.
src/cpu/simple/atomic.cc:
memory mode assertion change so that it only goes off if it's supposed to.
src/cpu/simple/timing.cc:
some drain changes (kevin's) and some changes to memoryMode assertions so that they don't go off when they're not supposed to.
--HG--
extra : convert_revision :
007d8610f097e08f01367b905ada49f93cf37ca3
Ron Dreslinski [Wed, 11 Oct 2006 22:28:33 +0000 (18:28 -0400)]
More cache fixes. Atomic coherence now works as well.
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
Make Memtester able to test atomic as well
src/mem/bus.cc:
src/mem/bus.hh:
Handle atomic snoops properly for cache->cache transfers
src/mem/cache/cache_impl.hh:
Debug output.
Clean up memleak in atomic mode.
Set hitLatency.
Still need to send back reasonable number for atomic return value.
src/mem/packet.cc:
Add command strings for new commands
src/python/m5/objects/MemTest.py:
Add param to test atomic memory.
--HG--
extra : convert_revision :
43f880e29215776167c16ea90793ebf8122c785b
Ron Dreslinski [Wed, 11 Oct 2006 05:59:38 +0000 (01:59 -0400)]
Update for Atomic Coherece with Gabes bus
--HG--
extra : convert_revision :
6a23052056d1c61cba0a4c77f1030cee419c6fa3
Ron Dreslinski [Wed, 11 Oct 2006 05:18:20 +0000 (01:18 -0400)]
Interesting memtest finally.
Get over 500,000 reads on each of 8 testers before memory leak becomes large.
tests/configs/memtest.py:
Update test to be more interesting
--HG--
extra : convert_revision :
4258b798fbeeed2a376f1bfac100a109eb05620e
Ron Dreslinski [Wed, 11 Oct 2006 05:02:18 +0000 (01:02 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
70187b8f04d0f8424512f64bdade05bf1aca85a3
Ron Dreslinski [Wed, 11 Oct 2006 05:01:40 +0000 (01:01 -0400)]
Use bus response time paramteres
Fix bug with deadlocking
src/mem/cache/base_cache.cc:
Make sure to not wait anymore
--HG--
extra : convert_revision :
5f7b44a1c475820b9862275a0d6113ec2991735d
Gabe Black [Wed, 11 Oct 2006 04:54:47 +0000 (00:54 -0400)]
Don't call recvRetry if the bus is busy anyway. This takes care of a corner case as well when dealing with grants that aren't used.
--HG--
extra : convert_revision :
38f7ef1b41477fb2a2438387ef3a81cccd3e7a8a
Ron Dreslinski [Wed, 11 Oct 2006 04:31:40 +0000 (00:31 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
d2d19b27533f35c6570ee84c6c83b2919f27b97f
Gabe Black [Wed, 11 Oct 2006 04:26:21 +0000 (00:26 -0400)]
Make the bus work if the other sides recvRetry doesn't call sendTiming for some reason.
--HG--
extra : convert_revision :
e722ddb0354a5c021dc7c44a3e2f0a64e962442b
Ron Dreslinski [Wed, 11 Oct 2006 04:19:31 +0000 (00:19 -0400)]
When turning asserts into if's don't forget to invert.
src/mem/cache/base_cache.cc:
When turning asserts into if's don't forget to invert.
Must be too sleepy.
--HG--
extra : convert_revision :
ea38d5a4b4ddde7b5266b3b2c83bbc256218af9a
Ron Dreslinski [Wed, 11 Oct 2006 04:13:53 +0000 (00:13 -0400)]
Writebacks can be pulled out from under the BusRequest when snoops of uprgades to owned blocks hit in the WB buffer
--HG--
extra : convert_revision :
f0502836a79ce303150daa7e571badb0bce3a97a
Ron Dreslinski [Wed, 11 Oct 2006 03:53:10 +0000 (23:53 -0400)]
Only issue responses if we aren;t already blocked
--HG--
extra : convert_revision :
511c0bcd44b93d5499eefa8399f36ef8b6607311
Ron Dreslinski [Wed, 11 Oct 2006 03:37:14 +0000 (23:37 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
--HG--
extra : convert_revision :
18608114350c466a56ab499ae523b01fcb2f6ef2
Gabe Black [Wed, 11 Oct 2006 03:28:33 +0000 (23:28 -0400)]
Make the bus is occupied for none broadcast packets as well.
--HG--
extra : convert_revision :
aef3c625172e92be8f29c4c57077fefee43046bb
Ron Dreslinski [Wed, 11 Oct 2006 02:52:52 +0000 (22:52 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/bus.cc:
SCCS merged
--HG--
extra : convert_revision :
eaae105025635c37af06cf72bb061ce82def9dc9
Ron Dreslinski [Wed, 11 Oct 2006 02:50:36 +0000 (22:50 -0400)]
Debugging info
src/base/traceflags.py:
Add new flags for cacheport
src/mem/bus.cc:
Add debugging info
src/mem/cache/base_cache.cc:
Add debuggin info
--HG--
extra : convert_revision :
a6c4b452466a8e0b50a86e886833cb6e29edc748
Gabe Black [Wed, 11 Oct 2006 02:10:08 +0000 (22:10 -0400)]
Put in an accounting mechanism and an assert to make sure something doesn't try to send another packet while it's still waiting for the bus.
--HG--
extra : convert_revision :
4a2b83111e49f71ca27e05c98b55bc3bac8d9f53
Gabe Black [Tue, 10 Oct 2006 21:49:31 +0000 (17:49 -0400)]
Fixed a corner case and simplified the logic in Packet::intersect.
--HG--
extra : convert_revision :
b57c31ca7c220e701d34e02bb07ce392370e4428
Ron Dreslinski [Tue, 10 Oct 2006 21:32:24 +0000 (17:32 -0400)]
Merge zizzer:/n/wexford/x/gblack/m5/newmem_bus
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
7b7a1b03ffed36bce49595962ea57c08d1d1a4ad
Ron Dreslinski [Tue, 10 Oct 2006 21:25:50 +0000 (17:25 -0400)]
Some more code cleanup
src/mem/cache/base_cache.cc:
Add sanity checks
src/mem/cache/base_cache.hh:
Fix for retry mechanism
--HG--
extra : convert_revision :
9298e32e64194b1ef3fe51242595eaa56dcbbcfd
Gabe Black [Tue, 10 Oct 2006 21:24:03 +0000 (17:24 -0400)]
Changed the bus to use a bool to keep track of retries rather than a pointer
src/mem/tport.cc:
minor formatting tweak
--HG--
extra : convert_revision :
7391d142815c5876fcc0f991bd053e6a1781c101
Gabe Black [Tue, 10 Oct 2006 21:18:09 +0000 (17:18 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
aa59d3169d84bcd13b8c97f22b52aeef43dc33c3
Ron Dreslinski [Tue, 10 Oct 2006 21:10:56 +0000 (17:10 -0400)]
Fix some more mem leaks, still some left
Update retry mechanism
src/mem/cache/base_cache.cc:
Rework the retry mechanism
src/mem/cache/base_cache.hh:
Rework the retry mechanism
Try to fix memory bug
src/mem/cache/cache_impl.hh:
Rework upgrades to not be blocked by slave
src/mem/cache/miss/mshr_queue.cc:
Fix mem leak on writebacks
--HG--
extra : convert_revision :
3cec234ee441edf398ec8d0f51a0c5d7ada1e2be
Gabe Black [Tue, 10 Oct 2006 19:56:18 +0000 (15:56 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
4036e8447fb3038d93285c6582900210d7d88d67
Ron Dreslinski [Tue, 10 Oct 2006 19:53:25 +0000 (15:53 -0400)]
Fix cshr Retry's
Fix Upgrades being blocked by slave
--HG--
extra : convert_revision :
cca98a38e32233145163577500f1362cd807ab15
Gabe Black [Tue, 10 Oct 2006 19:04:55 +0000 (15:04 -0400)]
Merge zizzer.eecs.umich.edu:/bk/newmem
into zeep.eecs.umich.edu:/home/gblack/m5/newmem_bus
--HG--
extra : convert_revision :
6027c395af044858465eafd3ea78bcfe4c923bcc
Kevin Lim [Tue, 10 Oct 2006 15:04:21 +0000 (11:04 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
--HG--
extra : convert_revision :
8b27fc92f8aafe691d70dc654bff3798abf8e755
Kevin Lim [Tue, 10 Oct 2006 15:04:05 +0000 (11:04 -0400)]
Updates refs.
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/linux/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/linux/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/linux/simple-timing/stdout:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/o3-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-atomic/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.ini:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/config.out:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/m5stats.txt:
tests/quick/00.hello/ref/alpha/tru64/simple-timing/stdout:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.ini:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/config.out:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/m5stats.txt:
tests/quick/01.hello-2T-smt/ref/alpha/linux/o3-timing/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-atomic/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing-dual/stdout:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.ini:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/config.out:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/m5stats.txt:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stderr:
tests/quick/10.linux-boot/ref/alpha/linux/tsunami-simple-timing/stdout:
Update refs.
--HG--
extra : convert_revision :
5341341507ddbe1211992e5f72013d7be0000bae
Ron Dreslinski [Tue, 10 Oct 2006 06:36:04 +0000 (02:36 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
--HG--
extra : convert_revision :
87f83c4edf6ea51adc767d98265d1e74c0fbb46f
Ron Dreslinski [Tue, 10 Oct 2006 06:33:30 +0000 (02:33 -0400)]
Yet another fix to the HasData command attribute.
--HG--
extra : convert_revision :
dcf0d7eafa5168591c2b374b452821ca34dde7f9
Ron Dreslinski [Tue, 10 Oct 2006 06:21:03 +0000 (02:21 -0400)]
Actually set the HasData attribute on Read Responses
--HG--
extra : convert_revision :
129dadbf8091ab00fb7f16eace59df265fc3718c
Ron Dreslinski [Tue, 10 Oct 2006 06:00:37 +0000 (02:00 -0400)]
Fix another merge issue
--HG--
extra : convert_revision :
2b33da5e8578ea6a8bdd2d89f183c2e6b942b0fc
Ron Dreslinski [Tue, 10 Oct 2006 05:57:57 +0000 (01:57 -0400)]
Merge zizzer:/z/m5/Bitkeeper/newmem
into zazzer.eecs.umich.edu:/z/rdreslin/m5bk/newmemcleanest
src/mem/packet.hh:
Hand merge code
--HG--
extra : convert_revision :
d659418f24f4f4bf9867fec8573a5d227c0dfcea
Kevin Lim [Tue, 10 Oct 2006 05:49:46 +0000 (01:49 -0400)]
Two minor fixes.
configs/common/SysPaths.py:
Undo accidental change.
src/SConscript:
Fix.
--HG--
extra : convert_revision :
665b186cff7d8ae560601ced7ae407a41a16cfea
Ron Dreslinski [Tue, 10 Oct 2006 05:32:18 +0000 (01:32 -0400)]
Fix several bugs pertaining to upgrades/mem leaks.
src/mem/cache/base_cache.cc:
Fix a bug about not having a request to send
src/mem/cache/base_cache.hh:
Fix a bug with the blocking code
src/mem/cache/cache.hh:
A
\bFix a bug with snoop hits in WB buffer
src/mem/cache/cache_impl.hh:
Fix a bug with snoop hits in WB buffer
Also, add better DPRINTF's
src/mem/cache/miss/miss_queue.cc:
Fix a bug with upgrades (Need to clean it up later)
src/mem/cache/miss/mshr.cc:
Fix a memory leak bug, still some outstanding with writebacks not being deleted
src/mem/cache/miss/mshr_queue.cc:
Fix a bug about upgrades (need to clean up later)
src/mem/packet.hh:
Fix for newly added cmd attribute for upgrades
tests/configs/memtest.py:
More interesting testcase
--HG--
extra : convert_revision :
fcb4f17dd58b537bb4f67a8c835f50e455e8c688
Gabe Black [Tue, 10 Oct 2006 04:49:27 +0000 (00:49 -0400)]
Fixed a bug where a packet was attempted to be sent even though another packet was waiting for the bus.
--HG--
extra : convert_revision :
29f7a4f676884330d7b7e93517dea85fc7bbf678
Gabe Black [Tue, 10 Oct 2006 03:24:21 +0000 (23:24 -0400)]
Fixes to the bus, and added fields to the packet.
src/mem/bus.cc:
Put back the check to see if the bus is busy. Also, populate the fields in the packet to indicate when the first word and the entire packet will be delivered.
src/mem/bus.hh:
Remove the occupyBus function.
src/mem/packet.hh:
Added fields to the packet to indicate when the first chunk of a packet arrives, and when the entire packet arrives.
--HG--
extra : convert_revision :
cfc7670a33913d48a04d02c6d2448290a51f2d3c
Kevin Lim [Tue, 10 Oct 2006 02:59:56 +0000 (22:59 -0400)]
Merge ktlim@zizzer:/bk/newmem
into zamp.eecs.umich.edu:/z/ktlim2/clean/o3-merge/newmem
src/cpu/memtest/memtest.cc:
src/cpu/memtest/memtest.hh:
src/cpu/simple/timing.hh:
tests/configs/o3-timing-mp.py:
Hand merge.
--HG--
extra : convert_revision :
a58cc439eb5e8f900d175ed8b5a85b6c8723e558
Kevin Lim [Tue, 10 Oct 2006 02:49:58 +0000 (22:49 -0400)]
Comment out code that messed up SMT (but will be needed eventually).
src/cpu/o3/cpu.cc:
Comment out reseting CPU structures for now. This can be updated to work in the future.
--HG--
extra : convert_revision :
bc1a86e2fe47da5acb14ba8b64568b0355431f1c
Ron Dreslinski [Tue, 10 Oct 2006 00:18:00 +0000 (20:18 -0400)]
Handle NACK's that occur from devices on the same bus.
Not fully implemented yet, but good enough for single level cache coherence
src/mem/packet.hh:
Add a bit to distinguish invalidates and upgrades
--HG--
extra : convert_revision :
5bf50d535857cea37fbdaf7993915d1332cb757e