Dmitry Selyutin [Wed, 25 Oct 2023 19:49:11 +0000 (22:49 +0300)]
syscall: improve architecture detection
Jacob Lifshay [Wed, 25 Oct 2023 03:18:48 +0000 (20:18 -0700)]
install pytest-subtests==0.11.0
Jacob Lifshay [Wed, 25 Oct 2023 03:18:27 +0000 (20:18 -0700)]
generate syscalls.json
Luke Kenneth Casson Leighton [Tue, 24 Oct 2023 17:16:06 +0000 (18:16 +0100)]
whitespace cleanup
Jacob Lifshay [Fri, 20 Oct 2023 01:57:00 +0000 (18:57 -0700)]
Revert "skip broken test"
requested by luke:
https://bugs.libre-soc.org/show_bug.cgi?id=1193#c1
This reverts commit
e0a4f19b2c90be84a77a4aa584c6d60e508d92f5.
Jacob Lifshay [Fri, 20 Oct 2023 01:18:51 +0000 (18:18 -0700)]
Revert "Revert "fix bug where pseudo-code assignments modify more than just the variable being assigned to""
we need copy_assign_rhs
See https://bugs.libre-soc.org/show_bug.cgi?id=1066
This reverts commit
bd3b54e83101217dc32da09083c6a3858fd7c600.
Jacob Lifshay [Fri, 20 Oct 2023 01:17:20 +0000 (18:17 -0700)]
Revert "fix bug introduced by having to revert unauthorized addition of"
we need copy_assign_rhs
See https://bugs.libre-soc.org/show_bug.cgi?id=1066
This reverts commit
9dab88318a2938f14873804d83bf85ef9ae2fb93.
Jacob Lifshay [Fri, 20 Oct 2023 01:00:55 +0000 (18:00 -0700)]
skip broken test
it wasn't obvious how to fix it, see https://bugs.libre-soc.org/show_bug.cgi?id=1193
Jacob Lifshay [Fri, 20 Oct 2023 00:49:04 +0000 (17:49 -0700)]
fill in manually verified expected state for TrapTestCase.case_2_kaivb_test
based on the Programming Note on left side of PowerISA v3.1B page 1289 (1315)
Jacob Lifshay [Fri, 20 Oct 2023 00:37:34 +0000 (17:37 -0700)]
format code
Jacob Lifshay [Mon, 23 Oct 2023 23:09:51 +0000 (16:09 -0700)]
reduce mmap BLOCK_SIZE to 1 << 28 so it works on armv7a
Dmitry Selyutin [Mon, 23 Oct 2023 20:32:57 +0000 (23:32 +0300)]
syscall: handle architecture aliases
Dmitry Selyutin [Mon, 23 Oct 2023 20:23:08 +0000 (23:23 +0300)]
syscall: handle arm and aarch64 architectures
Dmitry Selyutin [Mon, 23 Oct 2023 06:17:55 +0000 (09:17 +0300)]
test_syscall: hardcode MSR validation
Dmitry Selyutin [Sun, 22 Oct 2023 13:14:55 +0000 (16:14 +0300)]
test_syscall: check MSR; update expected PC
Dmitry Selyutin [Sun, 22 Oct 2023 06:44:37 +0000 (09:44 +0300)]
isa/test_runner: support initial_msr parameter
Dmitry Selyutin [Sun, 22 Oct 2023 06:29:50 +0000 (09:29 +0300)]
isa/caller: return from interrupt upon syscall emulation
Dmitry Selyutin [Fri, 20 Oct 2023 17:16:22 +0000 (20:16 +0300)]
test_syscall: provide code for future SPR checks
Dmitry Selyutin [Fri, 20 Oct 2023 17:15:12 +0000 (20:15 +0300)]
isa/caller: refactor sc logic
Dmitry Selyutin [Wed, 18 Oct 2023 17:11:51 +0000 (20:11 +0300)]
test_caller: introduce syscall tests
Dmitry Selyutin [Wed, 18 Oct 2023 15:32:37 +0000 (18:32 +0300)]
isa/caller: enable host-backed memory for scemu
Dmitry Selyutin [Wed, 18 Oct 2023 15:26:14 +0000 (18:26 +0300)]
test/runner: introduce use_syscall_emu parameter
Dmitry Selyutin [Wed, 18 Oct 2023 15:24:31 +0000 (18:24 +0300)]
isa/caller: introduce use_syscall_emu parameter
Dmitry Selyutin [Wed, 18 Oct 2023 17:06:17 +0000 (20:06 +0300)]
isa/test_runner: support additional parameters
Dmitry Selyutin [Wed, 18 Oct 2023 15:33:02 +0000 (18:33 +0300)]
isa/caller: remove redundant check
Dmitry Selyutin [Fri, 22 Sep 2023 19:08:10 +0000 (22:08 +0300)]
isa/caller: provide sc and scv instructions wrapper
Luke Kenneth Casson Leighton [Sat, 21 Oct 2023 18:10:23 +0000 (18:10 +0000)]
add extra comments to sc-rfid test
Luke Kenneth Casson Leighton [Fri, 20 Oct 2023 21:09:22 +0000 (22:09 +0100)]
add a test which does both sc and rfid, and does rudimentary
checking that they are executed in expected order by setting some GPRs.
a whole bunch of NOPs were added to get the assembler to start at 0xc00
with a jump right at the start. terrible hack but does the job.
Andrey Miroshnikov [Thu, 19 Oct 2023 10:05:05 +0000 (10:05 +0000)]
Added assert to check inner/outer results match
Andrey Miroshnikov [Thu, 19 Oct 2023 09:25:17 +0000 (09:25 +0000)]
Replace flatten func with builtin reduce()
Andrey Miroshnikov [Thu, 19 Oct 2023 06:49:14 +0000 (06:49 +0000)]
Readded the flatten func (removed accidentally)
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 21:05:52 +0000 (22:05 +0100)]
add expected results to "sc" instruction in TrapTestCase.
this demonstrates how "sc" is meant to work in standard (system) mode.
this *may* be exactly what TestIssuer does, it will have to be checked
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 21:04:33 +0000 (22:04 +0100)]
add SRR0 and SRR1 to list of special_regs in parser
which are not treated as "create on assign".
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 21:03:38 +0000 (22:03 +0100)]
annoying - call the TRAP() function in system.mdwn "sc" instruction.
setting NIA and MSR is tricky, it involves reading some english text
that is very unclear (Book III section 4.3.1 which then in turn says
"go to section 7.5 page 1076").
given that we are not implementing hypervisor or LEV=1/2/3 it is just
simpler to call TRAP(0xc00)
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 20:30:43 +0000 (21:30 +0100)]
fix bug introduced by having to revert unauthorized addition of
copy_assign_rhs
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 20:24:04 +0000 (21:24 +0100)]
Revert "fix bug where pseudo-code assignments modify more than just the variable being assigned to"
This reverts commit
4e701a851536bba6648779c183293ba75e7ea7b8.
adding copy_assign_rhs was added without authorization or discussion and
is damaging the simulator
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 20:21:48 +0000 (21:21 +0100)]
add sc test to TestTrapCases
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 19:56:40 +0000 (20:56 +0100)]
add test_caller_trap.py which stunningly actually works reasonably well
(TrapTestCase has only previously been run on TestIssuer)
Dmitry Selyutin [Fri, 22 Sep 2023 19:07:40 +0000 (22:07 +0300)]
power_enums: mention sc and scv instructions
Luke Kenneth Casson Leighton [Wed, 18 Oct 2023 14:52:30 +0000 (15:52 +0100)]
add "is_idle" capability to inorder.py so that after adding
instructions the pipeline continues to propagate
Shriya Sharma [Wed, 18 Oct 2023 14:47:51 +0000 (15:47 +0100)]
settting pushed_to_decode true
Shriya Sharma [Wed, 18 Oct 2023 14:32:36 +0000 (15:32 +0100)]
Added an extra unit test test_trace1
Andrey Miroshnikov [Tue, 17 Oct 2023 13:06:31 +0000 (13:06 +0000)]
Added pure python mat multiply (outer and inner product versions). Made result printing parametrisable.
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:49:11 +0000 (12:49 +0100)]
doh, use reduce on operator.add already
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:47:39 +0000 (12:47 +0100)]
print expected flattened matrix results
Andrey Miroshnikov [Wed, 11 Oct 2023 11:46:39 +0000 (11:46 +0000)]
Add assert
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:43:48 +0000 (12:43 +0100)]
remove cruft, make comments clearer
Andrey Miroshnikov [Wed, 11 Oct 2023 11:43:26 +0000 (11:43 +0000)]
Use flatten
Andrey Miroshnikov [Wed, 11 Oct 2023 11:41:16 +0000 (11:41 +0000)]
Add flatten function, print expected
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:23:02 +0000 (12:23 +0100)]
rename expected to results (actual results)
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:20:58 +0000 (12:20 +0100)]
store integer results in expected array
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:19:32 +0000 (12:19 +0100)]
simplify matmult test code
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:18:09 +0000 (12:18 +0100)]
whitespace
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:17:29 +0000 (12:17 +0100)]
whitespace
Andrey Miroshnikov [Wed, 11 Oct 2023 11:16:34 +0000 (11:16 +0000)]
Add pure python matrix mul function
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:11:57 +0000 (12:11 +0100)]
clarify prints and no conversion of integer input in maddld matrix test
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 11:05:59 +0000 (12:05 +0100)]
add stub (non-working) matrix multiply using maddld
Sadoon Albader [Wed, 11 Oct 2023 19:49:50 +0000 (22:49 +0300)]
add basic isacaller inlining to poly1305-donna.py
Luke Kenneth Casson Leighton [Wed, 11 Oct 2023 10:57:58 +0000 (11:57 +0100)]
accidentally commented-out matrix tests
Luke Kenneth Casson Leighton [Sun, 8 Oct 2023 13:57:48 +0000 (14:57 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:56:50 +0000 (11:56 +0100)]
forgot title
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:55:38 +0000 (11:55 +0100)]
missing brackets in lhbrx
Shriya Sharma [Fri, 27 Oct 2023 10:50:50 +0000 (11:50 +0100)]
added english language description for lhbrsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:46:27 +0000 (11:46 +0100)]
missing brackets in lhbrx
Shriya Sharma [Fri, 27 Oct 2023 10:46:18 +0000 (11:46 +0100)]
added english language description for lhbrsx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:44:32 +0000 (11:44 +0100)]
added english language description for ldsux instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:39:35 +0000 (11:39 +0100)]
replace (RA) with "the contents of RA"
Shriya Sharma [Fri, 27 Oct 2023 10:41:40 +0000 (11:41 +0100)]
added english language description for ldbrsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:38:09 +0000 (11:38 +0100)]
pifploadshift.mdwn, do one example english pseudocode operands
Shriya Sharma [Fri, 27 Oct 2023 10:40:24 +0000 (11:40 +0100)]
added english language description for lwbrsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:36:17 +0000 (11:36 +0100)]
do one example stfsux in pifpstoreshift, english pseudocode operands
Shriya Sharma [Fri, 27 Oct 2023 10:38:58 +0000 (11:38 +0100)]
added english language description for lhbrsx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:37:56 +0000 (11:37 +0100)]
added english language description for ldsx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:35:47 +0000 (11:35 +0100)]
added english language description for lwasux instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:33:02 +0000 (11:33 +0100)]
contents of RA again
Shriya Sharma [Fri, 27 Oct 2023 10:34:45 +0000 (11:34 +0100)]
added english language description for lwasx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:33:21 +0000 (11:33 +0100)]
added english language description for lwzsux instruction
Shriya Sharma [Fri, 27 Oct 2023 10:31:56 +0000 (11:31 +0100)]
added english language description for lwzsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:29:00 +0000 (11:29 +0100)]
use words "the contents of register RA instead of (RA)
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:28:06 +0000 (11:28 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:27:30 +0000 (11:27 +0100)]
whitespace and
also use explicit "the contents of register RA
Shriya Sharma [Fri, 27 Oct 2023 10:30:00 +0000 (11:30 +0100)]
added english language description for lhasux instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:26:18 +0000 (11:26 +0100)]
whitespace
Shriya Sharma [Fri, 27 Oct 2023 10:28:41 +0000 (11:28 +0100)]
added english language description for lhasx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:24:49 +0000 (11:24 +0100)]
whitespace
Shriya Sharma [Fri, 27 Oct 2023 10:27:09 +0000 (11:27 +0100)]
added english language description for lhzsux instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:24:10 +0000 (11:24 +0100)]
whitespace
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:22:32 +0000 (11:22 +0100)]
space-dot whitespace cleanup
Shriya Sharma [Fri, 27 Oct 2023 10:24:39 +0000 (11:24 +0100)]
added english language description for lhzsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:21:53 +0000 (11:21 +0100)]
big whitespace cleanup
Shriya Sharma [Fri, 27 Oct 2023 10:22:49 +0000 (11:22 +0100)]
added english language description for lbzsux instruction
Shriya Sharma [Fri, 27 Oct 2023 10:20:00 +0000 (11:20 +0100)]
added english language description for lbzsx instruction
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:15:19 +0000 (11:15 +0100)]
whitespace cleanup
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:11:25 +0000 (11:11 +0100)]
whitespace cleanup
Shriya Sharma [Fri, 27 Oct 2023 10:13:02 +0000 (11:13 +0100)]
added commas
Luke Kenneth Casson Leighton [Fri, 27 Oct 2023 10:07:34 +0000 (11:07 +0100)]
add a comma to reduce ambiguity
Shriya Sharma [Fri, 27 Oct 2023 10:09:44 +0000 (11:09 +0100)]
added english language description for stdbrsx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:08:45 +0000 (11:08 +0100)]
added english language description for stwbrsx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:03:53 +0000 (11:03 +0100)]
added english language description for sthbrx instruction
Shriya Sharma [Fri, 27 Oct 2023 10:02:05 +0000 (11:02 +0100)]
added english language description for stdsux instruction