Clifford Wolf [Sat, 2 Aug 2014 13:44:10 +0000 (15:44 +0200)]
Improvements in new RTLIL::IdString implementation
Clifford Wolf [Sat, 2 Aug 2014 13:12:16 +0000 (15:12 +0200)]
Fixed a performance bug in opt_reduce
Clifford Wolf [Sat, 2 Aug 2014 13:11:35 +0000 (15:11 +0200)]
Implemented new reference counting RTLIL::IdString
Clifford Wolf [Sat, 2 Aug 2014 11:34:07 +0000 (13:34 +0200)]
Fixed memory corruption related to id2cstr()
Clifford Wolf [Sat, 2 Aug 2014 11:11:01 +0000 (13:11 +0200)]
More cleanups related to RTLIL::IdString usage
Clifford Wolf [Fri, 1 Aug 2014 22:45:25 +0000 (00:45 +0200)]
Preparations for RTLIL::IdString redesign: cleanup of existing code
Clifford Wolf [Fri, 1 Aug 2014 17:43:28 +0000 (19:43 +0200)]
Added logfile hash to statistics footer
Clifford Wolf [Fri, 1 Aug 2014 17:01:10 +0000 (19:01 +0200)]
Replaced sha1 implementation
Clifford Wolf [Fri, 1 Aug 2014 16:42:10 +0000 (18:42 +0200)]
Added per-pass cpu usage statistics
Clifford Wolf [Fri, 1 Aug 2014 14:53:15 +0000 (16:53 +0200)]
Added ModIndex helper class, some changes to RTLIL::Monitor
Clifford Wolf [Fri, 1 Aug 2014 13:25:42 +0000 (15:25 +0200)]
Packed SigBit::data and SigBit::offset in a union
Clifford Wolf [Fri, 1 Aug 2014 01:57:37 +0000 (03:57 +0200)]
Consolidated hana test benches into fewer files
for pf in test_simulation_{always,and,buffer,decoder,inc,mux,nand,nor,or,seq,shifter,sop,techmap,xnor,xor}; do
gawk 'FNR == 1 { printf("\n// %s\n",FILENAME); } { gsub("^module *", sprintf("module f%d_",ARGIND)); print; }' \
${pf}_*_test.v > $pf.v; ../tools/autotest.sh $pf.v; mv -v ${pf}_*_test.v Attic/; done;
..etc..
Clifford Wolf [Fri, 1 Aug 2014 01:55:51 +0000 (03:55 +0200)]
Added "test_autotb -n <num_iter>" option
Clifford Wolf [Thu, 31 Jul 2014 21:30:18 +0000 (23:30 +0200)]
Renamed modwalker.h to modtools.h
Clifford Wolf [Thu, 31 Jul 2014 21:14:17 +0000 (23:14 +0200)]
Various cleanups in Makefile, Renamed default configurations
Clifford Wolf [Thu, 31 Jul 2014 21:07:00 +0000 (23:07 +0200)]
Added compiler + compiler version + compiler flags to version string
Clifford Wolf [Thu, 31 Jul 2014 14:45:23 +0000 (16:45 +0200)]
Fixed build of verific bindings
Clifford Wolf [Thu, 31 Jul 2014 14:38:54 +0000 (16:38 +0200)]
Renamed port access function on RTLIL::Cell, added param access functions
Clifford Wolf [Thu, 31 Jul 2014 13:02:16 +0000 (15:02 +0200)]
Added "trace" command
Clifford Wolf [Thu, 31 Jul 2014 12:34:12 +0000 (14:34 +0200)]
Added RTLIL::Monitor
Clifford Wolf [Thu, 31 Jul 2014 12:11:39 +0000 (14:11 +0200)]
Added module->design and cell->module, wire->module pointers
Clifford Wolf [Thu, 31 Jul 2014 11:19:47 +0000 (13:19 +0200)]
Moved some stuff to kernel/yosys.{h,cc}, using Yosys:: namespace
Clifford Wolf [Thu, 31 Jul 2014 00:32:00 +0000 (02:32 +0200)]
Renamed "stdcells.v" to "techmap.v"
Clifford Wolf [Thu, 31 Jul 2014 00:21:41 +0000 (02:21 +0200)]
Added "techmap -assert"
Clifford Wolf [Thu, 31 Jul 2014 00:21:06 +0000 (02:21 +0200)]
Reorganized stdcells.v (no actual code change, just moved and indented stuff)
Clifford Wolf [Wed, 30 Jul 2014 23:05:27 +0000 (01:05 +0200)]
Added "yosys -A"
Clifford Wolf [Wed, 30 Jul 2014 22:53:21 +0000 (00:53 +0200)]
Added "yosys -Q"
Clifford Wolf [Wed, 30 Jul 2014 20:04:30 +0000 (22:04 +0200)]
Added techmap CONSTMAP feature
Clifford Wolf [Wed, 30 Jul 2014 18:18:48 +0000 (20:18 +0200)]
Fixed counting verilog line numbers for "// synopsys translate_off" sections
Clifford Wolf [Wed, 30 Jul 2014 17:59:29 +0000 (19:59 +0200)]
Added write_file command
Clifford Wolf [Wed, 30 Jul 2014 17:21:52 +0000 (19:21 +0200)]
Added "make -j{N}" support to "make test"
Clifford Wolf [Wed, 30 Jul 2014 13:59:38 +0000 (15:59 +0200)]
Improvements in test_cell
Clifford Wolf [Wed, 30 Jul 2014 13:59:05 +0000 (15:59 +0200)]
New techmap default rules for $shr $sshr $shl $sshl
Clifford Wolf [Wed, 30 Jul 2014 15:18:31 +0000 (17:18 +0200)]
Using native ezSAT shift ops in satgen, fixed $shift and $shiftx SAT models
Clifford Wolf [Wed, 30 Jul 2014 15:17:31 +0000 (17:17 +0200)]
Added native support for shift operations to ezSAT
Clifford Wolf [Wed, 30 Jul 2014 13:58:21 +0000 (15:58 +0200)]
Added "log_dump_val_worker(char *v)"
Clifford Wolf [Wed, 30 Jul 2014 12:10:49 +0000 (14:10 +0200)]
Added CodingStyle document
Clifford Wolf [Wed, 30 Jul 2014 12:10:15 +0000 (14:10 +0200)]
Added "kernel/yosys.h" and "kernel/yosys.cc"
Clifford Wolf [Tue, 29 Jul 2014 20:05:00 +0000 (22:05 +0200)]
Added "test_cell" command
Clifford Wolf [Tue, 29 Jul 2014 19:12:50 +0000 (21:12 +0200)]
Renamed "write_autotest" to "test_autotb" and moved to passes/tests/
Clifford Wolf [Tue, 29 Jul 2014 18:14:25 +0000 (20:14 +0200)]
Fixed Verilog pre-processor for files with no trailing newline
Clifford Wolf [Tue, 29 Jul 2014 17:23:31 +0000 (19:23 +0200)]
Bugfix in simlib.v for iverilog
Clifford Wolf [Tue, 29 Jul 2014 14:33:56 +0000 (16:33 +0200)]
Allow "hierarchy -generate" for $__ cells
Clifford Wolf [Tue, 29 Jul 2014 14:06:27 +0000 (16:06 +0200)]
Added "techmap -map %{design-name}"
Clifford Wolf [Tue, 29 Jul 2014 12:42:33 +0000 (14:42 +0200)]
Added $shift and $shiftx cell types (needed for correct part select behavior)
Clifford Wolf [Mon, 28 Jul 2014 17:38:30 +0000 (19:38 +0200)]
Removed left over debug code
Clifford Wolf [Mon, 28 Jul 2014 14:45:26 +0000 (16:45 +0200)]
Fixed part selects of parameters
Clifford Wolf [Mon, 28 Jul 2014 14:09:50 +0000 (16:09 +0200)]
Set results of out-of-bounds static bit/part select to undef
Clifford Wolf [Mon, 28 Jul 2014 13:31:19 +0000 (15:31 +0200)]
Fixed RTLIL code generator for part select of parameter
Clifford Wolf [Mon, 28 Jul 2014 13:19:34 +0000 (15:19 +0200)]
Fixed width detection for part selects
Clifford Wolf [Mon, 28 Jul 2014 12:25:03 +0000 (14:25 +0200)]
Added support for "upto" wires to Verilog front- and back-end
Clifford Wolf [Mon, 28 Jul 2014 10:12:13 +0000 (12:12 +0200)]
Added wire->upto flag for signals such as "wire [0:7] x;"
Clifford Wolf [Mon, 28 Jul 2014 09:08:55 +0000 (11:08 +0200)]
Using log_assert() instead of assert()
Clifford Wolf [Mon, 28 Jul 2014 08:52:58 +0000 (10:52 +0200)]
Added std::initializer_list<> constructor to SigSpec
Clifford Wolf [Mon, 28 Jul 2014 08:52:30 +0000 (10:52 +0200)]
Added cover() to all SigSpec constructors
Clifford Wolf [Mon, 28 Jul 2014 08:10:08 +0000 (10:10 +0200)]
Fixed signdness detection of expressions with bit- and part-selects
Clifford Wolf [Mon, 28 Jul 2014 07:15:40 +0000 (09:15 +0200)]
Improvements in tests/vloghtb
Clifford Wolf [Sun, 27 Jul 2014 19:13:23 +0000 (21:13 +0200)]
Added techmap -extern
Clifford Wolf [Sun, 27 Jul 2014 19:12:09 +0000 (21:12 +0200)]
Added proper Design->addModule interface
Clifford Wolf [Sun, 27 Jul 2014 14:19:24 +0000 (16:19 +0200)]
Added topological sorting to techmap
Clifford Wolf [Sun, 27 Jul 2014 13:38:02 +0000 (15:38 +0200)]
Added SigPool::check(bit)
Clifford Wolf [Sun, 27 Jul 2014 13:14:02 +0000 (15:14 +0200)]
Small improvements in PerformanceTimer API
Clifford Wolf [Sun, 27 Jul 2014 13:13:29 +0000 (15:13 +0200)]
Fixed bug in opt_clean
Clifford Wolf [Sun, 27 Jul 2014 12:50:25 +0000 (14:50 +0200)]
Improved performance of opt_const on large modules
Clifford Wolf [Sun, 27 Jul 2014 12:47:48 +0000 (14:47 +0200)]
Added RTLIL::SigSpec::remove_const() handling of packed SigSpecs
Clifford Wolf [Sun, 27 Jul 2014 12:47:23 +0000 (14:47 +0200)]
Added RTLIL::SigSpecConstIterator
Clifford Wolf [Sun, 27 Jul 2014 11:19:05 +0000 (13:19 +0200)]
Fixed a bug in opt_clean and some RTLIL API usage cleanups
Clifford Wolf [Sun, 27 Jul 2014 10:04:12 +0000 (12:04 +0200)]
Added log_cmd_error_expection
Clifford Wolf [Sun, 27 Jul 2014 10:00:28 +0000 (12:00 +0200)]
Fixed verific bindings for new RTLIL api
Clifford Wolf [Sun, 27 Jul 2014 09:56:35 +0000 (11:56 +0200)]
Fixed ilang parser for new RTLIL API
Clifford Wolf [Sun, 27 Jul 2014 08:41:42 +0000 (10:41 +0200)]
Using new obj iterator API in a few places
Clifford Wolf [Sun, 27 Jul 2014 09:03:56 +0000 (11:03 +0200)]
Added RTLIL::Module::wire(id) and cell(id) lookup functions
Clifford Wolf [Sun, 27 Jul 2014 08:40:31 +0000 (10:40 +0200)]
Added RTLIL::Design::modules()
Clifford Wolf [Sun, 27 Jul 2014 08:18:00 +0000 (10:18 +0200)]
Refactoring: Renamed RTLIL::Design::modules to modules_
Clifford Wolf [Sun, 27 Jul 2014 08:41:06 +0000 (10:41 +0200)]
Added conversion from ObjRange to std::vector and std::set
Clifford Wolf [Sun, 27 Jul 2014 08:13:22 +0000 (10:13 +0200)]
Added RTLIL::ObjIterator and RTLIL::ObjRange
Clifford Wolf [Sun, 27 Jul 2014 07:20:59 +0000 (09:20 +0200)]
Using std::move() in SigSpec move constructor
Clifford Wolf [Sun, 27 Jul 2014 00:11:57 +0000 (02:11 +0200)]
Added RTLIL::SigSpec move constructor and move assignment operator
Clifford Wolf [Sun, 27 Jul 2014 00:00:04 +0000 (02:00 +0200)]
Mostly cosmetic changes to rtlil.h
Clifford Wolf [Sat, 26 Jul 2014 23:51:45 +0000 (01:51 +0200)]
Refactoring: Renamed RTLIL::Module::cells to cells_
Clifford Wolf [Sat, 26 Jul 2014 23:49:51 +0000 (01:49 +0200)]
Refactoring: Renamed RTLIL::Module::wires to wires_
Clifford Wolf [Sat, 26 Jul 2014 19:34:19 +0000 (21:34 +0200)]
New message for completion of build
Clifford Wolf [Sat, 26 Jul 2014 19:16:05 +0000 (21:16 +0200)]
Changed more code to the new RTLIL::Wire constructors
Clifford Wolf [Sat, 26 Jul 2014 18:12:50 +0000 (20:12 +0200)]
Changed a lot of code to the new RTLIL::Wire constructors
Clifford Wolf [Sat, 26 Jul 2014 15:43:41 +0000 (17:43 +0200)]
Added tests/various/.gitignore
Clifford Wolf [Sat, 26 Jul 2014 15:22:18 +0000 (17:22 +0200)]
Added tests/various/submod_extract.ys
Clifford Wolf [Sat, 26 Jul 2014 15:21:40 +0000 (17:21 +0200)]
Added support for here documents
Clifford Wolf [Sat, 26 Jul 2014 14:14:02 +0000 (16:14 +0200)]
More RTLIL::Cell API usage cleanups
Clifford Wolf [Sat, 26 Jul 2014 14:11:28 +0000 (16:11 +0200)]
Added RTLIL::Cell::has(portname)
Clifford Wolf [Sat, 26 Jul 2014 14:00:30 +0000 (16:00 +0200)]
Merge automatic and manual code changes for new cell connections API
Clifford Wolf [Sat, 26 Jul 2014 13:57:57 +0000 (15:57 +0200)]
Manual fixes for new cell connections API
Clifford Wolf [Sat, 26 Jul 2014 12:32:50 +0000 (14:32 +0200)]
Changed users of cell->connections_ to the new API (sed command)
git grep -l 'connections_' | xargs sed -i -r -e '
s/(->|\.)connections_\["([^"]*)"\] = (.*);/\1set("\2", \3);/g;
s/(->|\.)connections_\["([^"]*)"\]/\1get("\2")/g;
s/(->|\.)connections_.at\("([^"]*)"\)/\1get("\2")/g;
s/(->|\.)connections_.push_back/\1connect/g;
s/(->|\.)connections_/\1connections()/g;'
Clifford Wolf [Sat, 26 Jul 2014 13:57:27 +0000 (15:57 +0200)]
Added some missing "const" in rtlil.h
Clifford Wolf [Sat, 26 Jul 2014 12:38:33 +0000 (14:38 +0200)]
Added RTLIL::Module::connections()
Clifford Wolf [Sat, 26 Jul 2014 12:31:47 +0000 (14:31 +0200)]
Added RTLIL::Module::connect(const RTLIL::SigSig&)
Clifford Wolf [Sat, 26 Jul 2014 12:08:43 +0000 (14:08 +0200)]
Use "wget -N" in tests/vloghtb/run-test.sh
Clifford Wolf [Sat, 26 Jul 2014 12:08:20 +0000 (14:08 +0200)]
Added "passed" message to make test targets
Clifford Wolf [Sat, 26 Jul 2014 11:59:30 +0000 (13:59 +0200)]
Automatically pack SigSpec on copy/assign
Clifford Wolf [Sat, 26 Jul 2014 10:22:58 +0000 (12:22 +0200)]
Added new RTLIL::Cell port access methods
Clifford Wolf [Sat, 26 Jul 2014 09:58:03 +0000 (11:58 +0200)]
Renamed RTLIL::{Module,Cell}::connections to connections_