Alyssa Rosenzweig [Wed, 13 May 2020 18:43:50 +0000 (14:43 -0400)]
panfrost: Stub out lowering boilerplate
Structure ourselves as a NIR pass replacing loads/stores with
unpacked/packed versions as necessary. Not actually functional yet.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 16:23:53 +0000 (12:23 -0400)]
panfrost: Determine classes for stores
Fewer special cases here, thankfully.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 16:22:22 +0000 (12:22 -0400)]
panfrost: Determine load classes for formats
Via quirks.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 16:15:28 +0000 (12:15 -0400)]
panfrost: Add quirks for blend shader types
Every hardware has its own set of what it can and can't do... let's
document it all as quirks so the lowering code is GPU-agnostic.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 16:07:46 +0000 (12:07 -0400)]
panfrost: Determine unpacked type for formats
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 15:50:18 +0000 (11:50 -0400)]
panfrost: Add theory for new framebuffer lowering
We take a somewhat different strategy that should be more flexible.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Sat, 30 May 2020 01:11:11 +0000 (21:11 -0400)]
pan/mdg: Implement raw colourbuf loads on T720
Uses a similar path to the fp16 cbuf loads on T760. It should make sense
given the symmetry with T860.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Sat, 30 May 2020 01:08:32 +0000 (21:08 -0400)]
pan/mdg: Drop the u8 from the colorbuf op names
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Thu, 14 May 2020 17:30:41 +0000 (13:30 -0400)]
pan/mdg: Print 8-bit constants
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 22:42:19 +0000 (18:42 -0400)]
pan/mdg: Handle bitsize for packs
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 22:41:52 +0000 (18:41 -0400)]
pan/mdg: Treat packs "specially"
We maybe would prefer synthetic ops? We'll find out in due time..
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Tue, 12 May 2020 23:07:48 +0000 (19:07 -0400)]
pan/mdg: Add pack_unorm_4x8 via 8-bit
More efficient than the 32-bit version in NIR.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Alyssa Rosenzweig [Wed, 13 May 2020 20:17:46 +0000 (16:17 -0400)]
pan/mdg: Handle un/pack opcodes as moves
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5265>
Chris Wilson [Fri, 29 May 2020 18:51:28 +0000 (19:51 +0100)]
iris: Fixup copy'n'paste mistake in Makefile.sources
In changing iris_seqno.[ch] to iris_fine_fence.[ch] and moving the
lines earlier, the newline escape was forgotten.
Fixes: 034329128b703f8c2e8a ("iris: Rename iris_seqno to iris_fine_fence")
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5264>
Satyeshwar Singh [Thu, 28 May 2020 07:44:26 +0000 (00:44 -0700)]
intel/dev: Don't consider all TGL SKUs as GT1 only
We should be passing _gt instead of 1 to GEN12_FEATURES or else all TGL
SKUs will be considered as gt1 only.
Fixes: 54996ad4927 ("intel/dev: Split .num_subslices out of GEN12_FEATURES macro")
Signed-off-by: Satyeshwar Singh <satyeshwar.singh@intel.com>
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5261>
Vinson Lee [Sat, 30 May 2020 00:13:35 +0000 (17:13 -0700)]
r300g: Remove extra printf format specifiers.
Fix warning reported by Coverity Scan.
Missing argument to printf format specifier (PRINTF_ARGS)
missing_argument: No argument for format specifier %s.
Fixes: 04c1536bf7ab ("r300g: rasterizer debug logging")
Fixes: 85efb2fff0d4 ("r300g: try to use color varyings for texcoords if max texcoord limit is exceeded")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5274>
Ilia Mirkin [Sat, 30 May 2020 06:47:42 +0000 (02:47 -0400)]
nouveau: allow invalidating coherent/persistent buffer backings
This is needed to support the core's usage of coherent buffers for
glVertex-style input. The reason why this was disallowed is that any
mappings will be invalidated. Let the state tracker worry about that,
and just reallocate when we're told.
Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
Cc: mesa-stable@lists.freedesktop.org
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5276>
Jason Ekstrand [Sat, 25 Apr 2020 19:59:30 +0000 (14:59 -0500)]
intel/fs: Emit HALT for discard on Gen4-5
Using HALT to immediately jump to the end of the shader is required to
implement GL_EXT_gpu_shader4 and OpenGL 3.0. However, vanilla OpenGL
1.2 doesn't forbid it and it likely makes something somewhere faster.
We should be consistent and implement the same discard behavior on all
hardware if we can.
The rules for HALT on Gen4-5 are a bit different from Gen6+. On the
older hardware, there is no stack for HALT; instead it's up to software
to save and restore mask registers. However, there's no real saving
needed since we only use HALT to jump to the end of the program where
we're about about to do our FB writes. All we need to do is reset AMask
to DMask, the value it was initialized to at the start of the thread.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5244>
Jason Ekstrand [Sun, 26 Apr 2020 14:48:16 +0000 (09:48 -0500)]
intel/fs: Fix unused texture coordinate zeroing on Gen4-5
We were inserting the right number of MOVs but, thanks to the way we
advanced msg_end earlier in the function, were often writing the zeros
past the end of where we actually read in the register file.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5243>
Jason Ekstrand [Sat, 25 Apr 2020 19:15:11 +0000 (14:15 -0500)]
intel/vec4: Stomp the return type of RESINFO to UINT32
We already do this in the FS back-end; we just weren't doing it in vec4
so RESINFO messages weren't returning the right data.
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5243>
Timothy Arceri [Fri, 29 May 2020 07:02:24 +0000 (17:02 +1000)]
radv: fix regression with builtin cache
If the ~/.cache dir already exists continue on without failing.
Fixes: cd61f5234d2c ("radv: Handle failing to create .cache dir.")
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5249>
Bas Nieuwenhuizen [Fri, 29 May 2020 11:47:00 +0000 (13:47 +0200)]
gallium/dri: Remove lowered_yuv tracking for plane mapping.
Just heard that etnaviv is also compatible with it even
in the non-lowered cases, so let us enable it for everyone.
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5253>
Vinson Lee [Thu, 28 May 2020 23:36:54 +0000 (16:36 -0700)]
panfrost: Fix printf format specifier.
bifrost_sampler_descriptor.zero1 is of type uint8_t.
Fix warning reported by Coverity.
Invalid type in argument to printf format specifier (PRINTF_ARGS)
invalid_type: Argument s->zero1 to format specifier %lx was expected to
have type unsigned long but has type unsigned char.
Fixes: 6148d1be4bb5 ("panfrost: Fix size of bifrost sampler descriptor")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5248>
Marek Olšák [Thu, 28 May 2020 20:21:39 +0000 (16:21 -0400)]
glthread: don't upload for glDraw inside a display list and always sync
Let the vbo module handle it, not glthread.
This handles functions set in vbo_initialize_save_dispatch.
Fixes: 2840bc3065b ("glthread: upload non-VBO vertices and indices for non-Indirect non-IBM draws")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3001
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5246>
Bas Nieuwenhuizen [Sun, 24 May 2020 22:05:20 +0000 (00:05 +0200)]
util/format: Add more multi-planar formats.
These don't have a fourcc code as far as I can tell, but we want
them for internal Vulkan use.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5195>
Bas Nieuwenhuizen [Sun, 24 May 2020 20:57:28 +0000 (22:57 +0200)]
util/format: Use correct pipe format for VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM.
NV12 is UVUVUV (https://wiki.videolan.org/YUV#NV12) and in Vulkan is
VK_FORMAT_G8_B8R8_2PLANE_420_UNORM. So U=B and V=R. So plane order in
VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM is YUV, which is PIPE_FORMAT_IYUV.
Further confirmation: https://fourcc.org/yuv.php U=Cb V=Cr. From the nir
ycbcr conversion, B=Cb and R=Cr.
Fixes: 75d7ee80291 "util/format: translate 422_UNORM and 420_UNORM vulkan formats"
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5195>
Bas Nieuwenhuizen [Sun, 24 May 2020 17:11:16 +0000 (19:11 +0200)]
util/format: Add VK_FORMAT_D16_UNORM_S8_UINT.
Not participating in packing/unpacking/stencil-only/depth-only,
because it doesn't mix well in a single plane.
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5195>
Vinson Lee [Tue, 26 May 2020 22:54:06 +0000 (15:54 -0700)]
etnaviv: Fix memory leak on error path.
Fix warning reported by Coverity Scan.
Resource leak (RESOURCE_LEAK)
leaked_storage: Variable pq going out of scope leaks the storage it
points to.
Suggested-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Fixes: eed5a009897a ("etnaviv: convert perfmon queries to acc queries")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5220>
Alyssa Rosenzweig [Fri, 29 May 2020 23:24:45 +0000 (19:24 -0400)]
panfrost: Probe G31/G52 if PAN_MESA_DEBUG=bifrost
We're not *quite* ready to open the flood gates on Bifrost (a major
blocker is CI, which is itself blocked on the lockdowns - expected to be
resolved in the coming months..)
Nevertheless, let's add a debug option to probe on compatible Bifrost
devices to avoid keeping out-of-tree patches around.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5272>
Alyssa Rosenzweig [Fri, 29 May 2020 23:24:05 +0000 (19:24 -0400)]
panfrost: Add GPU IDs for G31/G52
Dvalin/Gondul respectively.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5272>
Alyssa Rosenzweig [Fri, 29 May 2020 18:02:43 +0000 (14:02 -0400)]
panfrost: Disable QUAD_STRIP/POLYGON on Bifrost
Support was dropped and now raises a DATA_INVALID_FAULT on G31. Unknown
if retained on other devices. GL_QUADS is still ok.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 19:38:04 +0000 (15:38 -0400)]
pan/bi: Passthrough deps of the branch target
Now that we have the infrastructure, follow the branch.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 19:23:18 +0000 (15:23 -0400)]
pan/bi: Allow two successors in header packing
We need to take the union of the dependencies.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 19:01:14 +0000 (15:01 -0400)]
pan/bi: Measure backwards branches as well
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 19:01:38 +0000 (15:01 -0400)]
pan/bi: Add bi_foreach_block_from_rev helper
Needed for next commit.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:44:33 +0000 (14:44 -0400)]
pan/bi: Defer block naming until after emit
This ensures names are meaningful.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:38:44 +0000 (14:38 -0400)]
pan/bi: Pack unconditional branch
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:15:09 +0000 (14:15 -0400)]
pan/bi: Set branch conditional bit
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:13:12 +0000 (14:13 -0400)]
pan/bi: Set back-to-back bit more accurately
See Connor's ISA notes. Basically set unless it's a branch (explicit or
fallthrough).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:01:29 +0000 (14:01 -0400)]
pan/bi: Set branch_conditional if b2b is set
Match the blob.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 18:00:45 +0000 (14:00 -0400)]
pan/bi: Pack proper clause offsets
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:49:59 +0000 (13:49 -0400)]
pan/bi: Measure distance between blocks
For branch offset calculation.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:49:41 +0000 (13:49 -0400)]
pan/bi: Add bi_foreach_clause_in_block_from{_rev} helpers
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:48:46 +0000 (13:48 -0400)]
pan/bi: Link clauses back to their blocks
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 16:39:42 +0000 (12:39 -0400)]
pan/bi: Preliminary branch packing
Simple == 0 branch packing. Offset is still to-do.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:27:31 +0000 (13:27 -0400)]
pan/bi: Assign constant port for branch offsets
By convention.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:14:53 +0000 (13:14 -0400)]
pan/bi: Set branch_constant if there is a branch
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 17:08:04 +0000 (13:08 -0400)]
pan/bi: Pack branch offset constants
This is not fully generic but for a single constant it will do.
Extensions left for future work.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 16:53:22 +0000 (12:53 -0400)]
pan/bi: Add branch constant field to IR
The offsets used for branches need some extra bits twiddled, so add a
field to the clause to indicate this is happening. This is not ambiguous
since a clause can only have a single branch.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 16:39:26 +0000 (12:39 -0400)]
pan/bi: Passthrough ZERO in branch packing
There's a special mode for it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Thu, 28 May 2020 16:39:14 +0000 (12:39 -0400)]
pan/bi: Fix branch condition typesize
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Wed, 27 May 2020 22:35:50 +0000 (18:35 -0400)]
pan/bi: Fix CONVERT component counting
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Wed, 27 May 2020 22:29:01 +0000 (18:29 -0400)]
pan/bi: Only rewrite COMBINE dest if not SSA
If it's already a register, there's no point in rewriting and it will
disturb the existing register, i.e. for
if (..) {
r0 = vecN ..
} else {
r0 = vecN ..
}
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Wed, 27 May 2020 22:27:08 +0000 (18:27 -0400)]
pan/bi: Fix emit_if successor assignment
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 9a00cf3d1ef ("pan/bi: Add support for if-else blocks")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Wed, 27 May 2020 22:09:44 +0000 (18:09 -0400)]
pan/bi: Allow printing branches without targets
Useful for debugging codegen.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Wed, 27 May 2020 21:58:41 +0000 (17:58 -0400)]
pan/bi: Remove schedule_barrier
Legacy from Midgard.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 22:20:08 +0000 (18:20 -0400)]
pan/bi: Add helper to measure clause size
Useful for branching.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 21:58:16 +0000 (17:58 -0400)]
pan/bi: Add bi_layout.c for clause layout helpers
Figuring out what "shapes" of clauses are kosher happens during
scheduling, not packing, but shouldn't distract the scheduler. So let's
add a new file for these sorts of questions.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 21:29:24 +0000 (17:29 -0400)]
pan/bi: Remove more artefacts of 2-pass scheduling
A clause is, by definition, already scheduled.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:44 +0000 (16:15 -0400)]
pan/bi: Add MUL.i32 to disasm
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:36 +0000 (16:15 -0400)]
pan/bi: Disassemble pos=0xe
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 20:15:16 +0000 (16:15 -0400)]
pan/bi: Document constant count invariant
constants + instructions <= 13
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:34:58 +0000 (14:34 -0400)]
pan/bi: Move bi_flip_ports out of port assignment
It's more of a packing fixup than anything scheduler-y, and port
assignment will soon be the domain of the scheduler.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:31:20 +0000 (14:31 -0400)]
pan/bi: Add FILE* argument to bi_print_registers
In case we need it in general IR printing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:30:06 +0000 (14:30 -0400)]
pan/bi: Drop `struct` from bi_registers
It's a full-fledged part of the IR now.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:28:53 +0000 (14:28 -0400)]
pan/bi: Move bi_registers to bi_bundle
Make it a part of the IR itself.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:23:41 +0000 (14:23 -0400)]
pan/bi: Move bi_registers to common IR structures
Port assignments are critical to scheduling, this can't just live in
bi_pack.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Tue, 5 May 2020 18:17:58 +0000 (14:17 -0400)]
pan/bi: Remove comment about old scheduler design
I've realized it really has to be 1-pass to be sane.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Mon, 4 May 2020 23:46:32 +0000 (19:46 -0400)]
pan/bi: Remove FMA? parameter from get_src
We can lower away zeroes a bit earlier.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5260>
Alyssa Rosenzweig [Fri, 29 May 2020 20:06:39 +0000 (16:06 -0400)]
panfrost: Preload gl_FragCoord on Bifrost
It's a precoloured register but we do need to specify in the cmdstream
that we want the preloading to happen.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
Alyssa Rosenzweig [Fri, 29 May 2020 20:06:10 +0000 (16:06 -0400)]
panfrost: Set reads_frag_coord as a sysval
In addition to parsing out the varying. This is needed so it works on
Bifrost as well.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
Alyssa Rosenzweig [Fri, 29 May 2020 20:05:22 +0000 (16:05 -0400)]
panfrost: Don't generate gl_FragCoord varying on Bifrost
It's treated as a sysval there, so that's silly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5267>
Rob Clark [Mon, 18 May 2020 21:14:51 +0000 (14:14 -0700)]
freedreno/a6xx: fix vsc assert
Fixes a debug build assert seeing with an android app. Not quite sure
which path was passing us draw_info w/ instance_count==0. But we should
just treat non-instanced draws as having a single instance.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5091>
Kristian H. Kristensen [Thu, 21 May 2020 08:26:02 +0000 (01:26 -0700)]
freedreno/a6xx: Program VFD_DEST_CNTL from program stateobj
This only depends on the generated shader.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
Kristian H. Kristensen [Thu, 21 May 2020 08:38:44 +0000 (01:38 -0700)]
freedreno/a6xx: Create stateobj for VFD_DECODE
This now only depends on vertex state and we can create it once
up front in pctx->create_vertex_elements_state().
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
Kristian H. Kristensen [Thu, 21 May 2020 05:50:20 +0000 (22:50 -0700)]
freedreno/a6xx: Decouple VFD_FETCH and VFD_DECODE
We used to output a VFD_FETCH entry for each VFD_DECODE, but we can
instead output just one VFD_FETCH per VBO and point multiple
VFD_DECODE entries at the same VFD_FETCH entry. There's typically
fewer VBOs than vertex elements so this is a small win in itselfs, but
more importantly, the VFD_DECODE state now only depends on program
state.
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
Kristian H. Kristensen [Thu, 21 May 2020 05:34:59 +0000 (22:34 -0700)]
freedreno/a6xx: Move per element offset to VFD_DECODE
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5140>
Eric Anholt [Sat, 23 May 2020 03:00:07 +0000 (20:00 -0700)]
ci: Rename x86_cross_arm_test to just arm_test.
This gets us back to the behavior we used to have for freedreno: clicking
play on arm_test gets you testing of the ARM platforms that aren't under
arm-build (the LAVA runners).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Eric Anholt [Sat, 23 May 2020 02:58:50 +0000 (19:58 -0700)]
ci: Don't build an arm_test container now that the last user is gone.
db410c and cheza used to use it, and now both are on baremetal.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Eric Anholt [Fri, 15 May 2020 18:22:37 +0000 (11:22 -0700)]
ci: Switch cheza (freedreno a630) testing to baremetal.
Now that we have scripts in place to do baremetal testing of cheza, switch
it over. As of this writing, we have 5 chezas for baremetal and 4 for the
old docker CI setup (just 2 fewer than we originally had before this work,
since some had had filesystem failures and I switched those first), and
once we are sure of this we can backport to stable branch CI and move the
rest of them to baremetal.
I've run a lot of jobs through the baremetal scripts as I worked on
sorting out vulkan CTS stability, so I feel good about the stability of
the GLES CTS here.
The options job is now split out to separate jobs, as we don't currently
have a way to stack multiple sets deqp runs with different env vars in a
single baremetal run, and just chaining cros_servo.sh invocations runs
into a lack of cleanup of the serial-watching scripts which we rely on
container exit sorting out for us. This means a little less than 2x the
artifacts downloads we had before for a630 and a few more container
instantiations.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Eric Anholt [Fri, 15 May 2020 16:57:25 +0000 (09:57 -0700)]
ci: Add scripts for controlling bare-metal chezas.
This will let us:
- deploy kernels for testing code depending on new kernel featuers
- Ensure a pristine state in the HW before starting our tests
- Avoid disk rot on the chezas taking them out (we'd lost 3/9 in a few
months).
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Eric Anholt [Mon, 6 Apr 2020 22:55:30 +0000 (15:55 -0700)]
ci: Build a cheza kernel.
This is a set of kernel options I've come up with mostly cribbing from
chrome os's kernel config snippet. We also build an lzma kernel, as
uncompressed kernel is big but lzma is the only compression supported by
the bootloader. With that image, we have to pack it into a FIT formatted
image+dtb blob.
CONFIG_SUNRPC_DEBUG is added so that you can set "nfsrootdebug" to figure
out what's going wrong with your nfs mount (mine were "both the tcp and
nfsvers options were required, and don't try to use 'default' as the root
path to defer to DHCP's answer because otherwise you get
/tftpboot/default, just use an empty root path which doesn't prepend
/tftpboot.")
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Eric Anholt [Tue, 7 Apr 2020 00:00:14 +0000 (17:00 -0700)]
ci: Disable the firmware loader user helper option in arm64 kernels.
We won't have a user helper, so don't block for 60 seconds for it to show
up. Speeds up debug of new kernel builds.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5247>
Samuel Pitoiset [Thu, 21 May 2020 15:14:12 +0000 (17:14 +0200)]
radv/aco: enable VK_KHR_subgroup_extended_types on GFX8+
Should be working now.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Samuel Pitoiset [Thu, 28 May 2020 07:09:49 +0000 (09:09 +0200)]
aco: sign-extend input/indentity for 32-bit reduce ops on GFX10
Because some 16-bit instructions are already VOP3 on GFX10, we use
the 32-bit variants to remove the temporary VGPR and to use DDP with
the arithmetic instructions.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Samuel Pitoiset [Mon, 18 May 2020 15:01:46 +0000 (17:01 +0200)]
aco: allow gfx10_wave64_bpermute with 8-bit/16-bit input
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Samuel Pitoiset [Mon, 18 May 2020 15:03:21 +0000 (17:03 +0200)]
aco: allocate a temp VGPR for some 8-bit/16-bit reduction ops on GFX10
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Samuel Pitoiset [Mon, 18 May 2020 15:38:17 +0000 (17:38 +0200)]
aco: implement 8-bit/16-bit reductions on GFX10
Some 16-bit instructions are VOP3 on GFX10 and we have to emit a
32-bit DPP mov followed by the ALU instruction.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Samuel Pitoiset [Fri, 29 May 2020 08:02:39 +0000 (10:02 +0200)]
aco: fix register allocation for subdword instructions on GFX10
Cc: 20.1 <mesa-stable@lists.freedesktop.org>
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5148>
Bas Nieuwenhuizen [Mon, 25 May 2020 13:53:59 +0000 (15:53 +0200)]
frontend/dri: Implement mapping individual planes.
It is kinda surprising that
image2 = fromPlanar(image, 2, NULL)
mapImage(..., image2, ...)
does not map the third plane.
This implements that behavior in the case where the DRI frontend
lowers the multi-planar textures.
In the case it doesn't this would need driver support. AFAIU at
least etnaviv is impacted, and while it looks possible, I don't
have the etnaviv knowledge to implement it.
Instead of silently returning weird results (either always plane 0
or possibly something interleaved) this adds an error return on
mapping multi-planar textures otherwise.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5200>
Vinson Lee [Wed, 27 May 2020 23:19:25 +0000 (16:19 -0700)]
zink: Check fopen result.
Fix warning reported by Coverity.
Dereference null return value (NULL_RETURNS)
dereference: Dereferencing a pointer that might be NULL fp when calling
fwrite.
Fixes: 8d46e35d16e3 ("zink: introduce opengl over vulkan")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5235>
Samuel Pitoiset [Wed, 20 May 2020 06:41:46 +0000 (08:41 +0200)]
radv/aco: enable VK_EXT_subgroup_size_control
ACO should already support Wave32 on GFX10 with all shader stages
and CTS pass. RADV currently only allows Wave32 with the compute
shader stage.
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5056>
Rob Clark [Wed, 27 May 2020 20:50:05 +0000 (13:50 -0700)]
freedreno/a6xx: document LRZ flag buffer
Doesn't seem to be a big win, although I could still be missing
something in my implementation. But might as well add the
documentation.
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>
Rob Clark [Tue, 26 May 2020 20:58:22 +0000 (13:58 -0700)]
freedreno/a6xx: LRZ fix for alpha-test
Similarly to stencil-test, if alpha-test is enabled, we don't know
necessarily whether the fragment will pass.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3045
Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5217>
Neha Bhende [Wed, 27 May 2020 15:15:29 +0000 (20:45 +0530)]
util: Initialize pipe_shader_state for passthrough and transform shaders
mesa/st is initializing pipe_shader_state for user define shaders.
This patch intialized pipe_shader_state for all passthough
and transform shaders.
This fixes crashes for several opengl apps. Issue is found in vmware
internal testing
Fixes: f01c0565bb9 ("draw: free the NIR IR.")
Reviewed-by: Charmaine Lee <charmainel@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5240>
Chris Wilson [Wed, 27 May 2020 21:19:52 +0000 (22:19 +0100)]
iris: Rename iris_seqno to iris_fine_fence
Rename iris_seqno to iris_fine_fence, borrowed from si_fine_fence, to
avoid introducing any confusion with any other seqno used for tracking
pipelines.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5233>
Gert Wollny [Tue, 19 May 2020 15:52:31 +0000 (17:52 +0200)]
nir: lower_tex: Don't normalize coordinates for TXF with RECT
v2: remove the option to actually request normalization and its
application in Intel < Gen6 (Jason)
v3: Also don't lower for query operations (Jason)
Fixes: 1ce8060c25c7f2c7a54159fab6a6974c0ba182a8
nir/lower_tex: support for lowering RECT textures
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5105>
Eric Anholt [Tue, 26 May 2020 20:28:30 +0000 (13:28 -0700)]
ci: Quick exit qpa extraction for non-matching qpas.
When you're bringing up a new driver in CI with significant number of
failures (or when a CI run breaks a driver), the QPA extraction can easily
take the whole job timeout as we go about processing each QPA (100 of them
in my early VK CI fails) per unexpected result we're saving (50), which
involves reading and each line of the file in shell. By quickly filtering
out the QPA files not including our test, we can save all that shell
overhead, bringing QPA extract time down to a couple of minutes.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>
Eric Anholt [Fri, 22 May 2020 22:48:55 +0000 (15:48 -0700)]
ci: Move baremetal DEQP_NO_SAVE_RESULTS setup to the yml.
I'm going to want it unset (artifacts enabled) for the cheza jobs.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>
Eric Anholt [Tue, 26 May 2020 17:53:05 +0000 (10:53 -0700)]
ci: Add DEQP_EXPECTED_RENDERER support for VK tests.
I used this to debug what was going on with freedreno VK in CI.
Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5225>
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