Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Support squashing all state after special instruction
For SPARC ASIs are added to the ExtMachInst. If the ASI is changed simply
marking the instruction as Serializing isn't enough beacuse that only
stops rename. This provides a mechanism to squash all the instructions
and refetch them
Giacomo Gabrielli [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Make all instructions that write a misc. register not perform the write until commit.
ARM instructions updating cumulative flags (ARM FP exceptions and saturation
flags) are not serialized.
Added aliases for ARM FP exceptions and saturation flags in FPSCR. Removed
write accesses to the FP condition codes for most ARM VFP instructions: only
VCMP and VCMPE instructions update the FP condition codes. Removed a potential
cause of seg. faults in the O3 model for NEON memory macro-ops (ARM).
Min Kyu Jeong [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
O3: Support SWAP and predicated loads/store in ARM.
Ali Saidi [Wed, 8 Dec 2010 00:19:57 +0000 (16:19 -0800)]
ARM: Support switchover with hardware table walkers
Nilay Vaish [Wed, 1 Dec 2010 19:30:04 +0000 (11:30 -0800)]
ruby: Converted old ruby debug calls to M5 debug calls
This patch developed by Nilay Vaish converts all the old GEMS-style ruby
debug calls to the appropriate M5 debug calls.
Ali Saidi [Sat, 27 Nov 2010 01:47:23 +0000 (20:47 -0500)]
IGbE: return 0 on an invalid descriptor size instead of -1.
Asserts where descSize() get called with assert if we end up returning
0.
Gabe Black [Tue, 23 Nov 2010 22:08:41 +0000 (17:08 -0500)]
Copyright: Add AMD copyright to the param changes I just made.
Gabe Black [Tue, 23 Nov 2010 20:54:43 +0000 (15:54 -0500)]
Params: Add parameter types for IP addresses in various forms.
New parameter forms are:
IP address in the format "a.b.c.d" where a-d are from decimal 0 to 255.
IP address with netmask which is an IP followed by "/n" where n is a netmask
length in bits from decimal 0 to 32 or by "/e.f.g.h" where e-h are from
decimal 0 to 255 and which is all 1 bits followed by all 0 bits when
represented in binary. These can also be specified as an integral IP and
netmask passed in separately.
IP address with port which is an IP followed by ":p" where p is a port index
from decimal 0 to 65535. These can also be specified as an integral IP and
port value passed in separately.
Gabe Black [Tue, 23 Nov 2010 11:11:50 +0000 (06:11 -0500)]
X86: Loosen an assert for x86 and connect the APIC ports when caches are used.
Gabe Black [Tue, 23 Nov 2010 11:10:17 +0000 (06:10 -0500)]
X86: Obey the PCD (cache disable) bit in the page tables.
Gabe Black [Mon, 22 Nov 2010 10:49:03 +0000 (05:49 -0500)]
X86: Mark IO space accesses as uncachable.
Gabe Black [Mon, 22 Nov 2010 10:47:54 +0000 (05:47 -0500)]
X86: Remove reserved* from the m5 utility program for x86.
Gabe Black [Mon, 22 Nov 2010 07:33:47 +0000 (02:33 -0500)]
IDE,X86: Fix IDE controller BAR configuration for x86.
Nathan Binkert [Sat, 20 Nov 2010 20:12:27 +0000 (12:12 -0800)]
random: small comment about our random number generator and its origin
Ali Saidi [Sat, 20 Nov 2010 00:01:01 +0000 (18:01 -0600)]
SE: Fix simulating more than 4GB of RAM in SE mode
This change removes some dead code in PhysicalMemory, uses a 64 bit type
for the page pointer in System (instead of 32 bit) and cleans up some style.
Ali Saidi [Sat, 20 Nov 2010 00:00:59 +0000 (18:00 -0600)]
SCons: Fix compilation on OS X
Ali Saidi [Sat, 20 Nov 2010 00:00:39 +0000 (18:00 -0600)]
SCons: Support building without an ISA
Gabe Black [Thu, 18 Nov 2010 18:11:36 +0000 (13:11 -0500)]
O3: Fix fp destination register flattening, and index offset adjusting.
This change makes O3 flatten floating point destination registers, and also
fixes misc register flattening so that it's correctly repositioned relative to
the resized regions for integer and floating point indices.
It also fixes some overly long lines.
Gabe Black [Thu, 18 Nov 2010 04:16:19 +0000 (23:16 -0500)]
Config: Change misleading "cycle" message to say "tick".
Most of the messages in the config scripts that report a time value already
print "@ tick" followed by the current tick value, but a few were printing
"@ cycle". Since this is a distinction that's frequently confusing to new
users, this changes those message to the more accurate and consistent "@ tick".
Gabe Black [Tue, 16 Nov 2010 03:37:15 +0000 (19:37 -0800)]
Stats: Update the O3 fetch stats for SPARC.
Gabe Black [Tue, 16 Nov 2010 03:37:03 +0000 (19:37 -0800)]
O3: Make O3 support variably lengthed instructions.
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
O3: reset architetural state by calling clear()
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
ARM: Add comment about the organization of the IT state register
Ali Saidi [Mon, 15 Nov 2010 20:04:05 +0000 (14:04 -0600)]
Regressions: Update regressions for SIMD opclass changes
Giacomo Gabrielli [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
CPU/ARM: Add SIMD op classes to CPU models and ARM ISA.
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
ARM: Compile O3 CPU by default
Min Kyu Jeong [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
O3: prevent a squash when completeAcc() modifies misc reg through TC.
This happens on ARM instructions when they update the IT state bits.
Code and associated comment was copied from execute() and initiateAcc() methods
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
ARM: Return an FailUnimp instruction when an unimplemented CP15 register is accessed.
Just panicing in readMiscReg() doesn't work because a speculative access
in the o3 model can end the simulation.
Ali Saidi [Mon, 15 Nov 2010 20:04:04 +0000 (14:04 -0600)]
SCons: Cleanup SCons output during compile
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Update regressions for CLCD and KMI additions
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add a Keyboard Mouse Interface controller
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Implement a CLCD Frame buffer
William Wang [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for GDB on ARM
--HG--
rename : src/arch/alpha/remote_gdb.cc => src/arch/arm/remote_gdb.cc
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Make utility.hh meet style guidelines
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for a dumb IDE controller
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Cache the misc regs at the TLB to limit readMiscReg() calls.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Add support for switching CPUs
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Use the correct delete operator for RFE
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Fix SRS instruction to micro-code memory operation and register update.
Previously the SRS instruction attempted to writeback in initiateAcc() which
worked until a recent change, but was incorrect.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
CPU: Fix bug when a split transaction is issued to a faster cache
In the case of a split transaction and a cache that is faster than a CPU we
could get two responses before next_tick expires. Add an event that is
scheduled in this case and return false rather than asserting.
Ali Saidi [Mon, 15 Nov 2010 20:04:03 +0000 (14:04 -0600)]
ARM: Do something predictable for an UNPREDICTABLE branch.
Gabe Black [Thu, 11 Nov 2010 19:58:09 +0000 (11:58 -0800)]
Params: Fix an off by one error and a misleading comment.
Gabe Black [Thu, 11 Nov 2010 19:41:13 +0000 (11:41 -0800)]
SimObject: Add a comment near clear_child that it's unlikely to be called.
Gabe Black [Thu, 11 Nov 2010 10:03:58 +0000 (02:03 -0800)]
SPARC: Clean up some historical style issues.
Ali Saidi [Wed, 10 Nov 2010 06:48:03 +0000 (00:48 -0600)]
Update EIO regressions for last set of patches
Gabe Black [Tue, 9 Nov 2010 19:03:40 +0000 (11:03 -0800)]
scons: Work around for old versions of scons mistaking strings for sequences.
Gabe Black [Tue, 9 Nov 2010 18:45:02 +0000 (10:45 -0800)]
SimObject: Use "self" when calling the clear_child method.
Gabe Black [Mon, 8 Nov 2010 20:43:38 +0000 (12:43 -0800)]
X86: Fix X86_FS compilation.
Ali Saidi [Mon, 8 Nov 2010 19:59:35 +0000 (13:59 -0600)]
ARM: Update SE stats for TLB stats additions
Ali Saidi [Mon, 8 Nov 2010 19:58:25 +0000 (13:58 -0600)]
ARM: Add full-system regressions
Ali Saidi [Mon, 8 Nov 2010 19:58:25 +0000 (13:58 -0600)]
ARM: Add some TLB statistics for ARM
Ali Saidi [Mon, 8 Nov 2010 19:58:25 +0000 (13:58 -0600)]
ARM: Add checkpointing support
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
ARM: Add support for M5 ops in the ARM ISA
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
ARM: Keep the warnings to a minimum.
These warnings still need to be addresses, but pages of them is
counterproductive.
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
Mem: Finish half-baked support for mmaping file in physmem.
Physmem has a parameter to be able to mem map a file, however
it isn't actually used. This changeset utilizes the parameter
so a file can be mmapped.
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
Bus: Have the I/O devices that return address ranges print them out.
This way we actually get device names associated with the devices.
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
ARM: Don't return the result of a table walk the same cycle it's completed.
The L1 cache may have been accessed to provide this data, which confuses
it, if it ends up being accesses twice in one cycle. Instead wait 1 tick
which will force the timing simple CPU to forward to its next clock cycle
when the translation completes.
Also prevent multiple outstanding table walks from occuring at once.
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
scons: add a parameter to configure SCons' build cache
Ali Saidi [Mon, 8 Nov 2010 19:58:24 +0000 (13:58 -0600)]
ARM/Alpha/Cpu: Stats change for prefetchs to be more like normal loads.
Ali Saidi [Mon, 8 Nov 2010 19:58:22 +0000 (13:58 -0600)]
ARM/Alpha/Cpu: Change prefetchs to be more like normal loads.
This change modifies the way prefetches work. They are now like normal loads
that don't writeback a register. Previously prefetches were supposed to call
prefetch() on the exection context, so they executed with execute() methods
instead of initiateAcc() completeAcc(). The prefetch() methods for all the CPUs
are blank, meaning that they get executed, but don't actually do anything.
On Alpha dead cache copy code was removed and prefetches are now normal ops.
They count as executed operations, but still don't do anything and IsMemRef is
not longer set on them.
On ARM IsDataPrefetch or IsInstructionPreftech is now set on all prefetch
instructions. The timing simple CPU doesn't try to do anything special for
prefetches now and they execute with the normal memory code path.
Ali Saidi [Mon, 8 Nov 2010 19:58:22 +0000 (13:58 -0600)]
ARM: Make all ARM uops delayed commit.
Ali Saidi [Mon, 8 Nov 2010 19:58:22 +0000 (13:58 -0600)]
sim: Use forward declarations for ports.
Virtual ports need TLB data which means anything touching a file in the arch
directory rebuilds any file that includes system.hh which in everything.
Gabe Black [Sun, 7 Nov 2010 00:48:58 +0000 (17:48 -0700)]
scons: Replace the build_dir parameter to SConscript with variant_dir.
The build_dir parameter name has been deprecated and replaced with
variant_dir. This change switches us over to avoid warning spew in newer
versions of scons.
Gabe Black [Sun, 31 Oct 2010 07:07:48 +0000 (00:07 -0700)]
Ref output: Update refs for PCState change.
Gabe Black [Sun, 31 Oct 2010 07:07:20 +0000 (00:07 -0700)]
ISA,CPU,etc: Create an ISA defined PC type that abstracts out ISA behaviors.
This change is a low level and pervasive reorganization of how PCs are managed
in M5. Back when Alpha was the only ISA, there were only 2 PCs to worry about,
the PC and the NPC, and the lsb of the PC signaled whether or not you were in
PAL mode. As other ISAs were added, we had to add an NNPC, micro PC and next
micropc, x86 and ARM introduced variable length instruction sets, and ARM
started to keep track of mode bits in the PC. Each CPU model handled PCs in
its own custom way that needed to be updated individually to handle the new
dimensions of variability, or, in the case of ARMs mode-bit-in-the-pc hack,
the complexity could be hidden in the ISA at the ISA implementation's expense.
Areas like the branch predictor hadn't been updated to handle branch delay
slots or micropcs, and it turns out that had introduced a significant (10s of
percent) performance bug in SPARC and to a lesser extend MIPS. Rather than
perpetuate the problem by reworking O3 again to handle the PC features needed
by x86, this change was introduced to rework PC handling in a more modular,
transparent, and hopefully efficient way.
PC type:
Rather than having the superset of all possible elements of PC state declared
in each of the CPU models, each ISA defines its own PCState type which has
exactly the elements it needs. A cross product of canned PCState classes are
defined in the new "generic" ISA directory for ISAs with/without delay slots
and microcode. These are either typedef-ed or subclassed by each ISA. To read
or write this structure through a *Context, you use the new pcState() accessor
which reads or writes depending on whether it has an argument. If you just
want the address of the current or next instruction or the current micro PC,
you can get those through read-only accessors on either the PCState type or
the *Contexts. These are instAddr(), nextInstAddr(), and microPC(). Note the
move away from readPC. That name is ambiguous since it's not clear whether or
not it should be the actual address to fetch from, or if it should have extra
bits in it like the PAL mode bit. Each class is free to define its own
functions to get at whatever values it needs however it needs to to be used in
ISA specific code. Eventually Alpha's PAL mode bit could be moved out of the
PC and into a separate field like ARM.
These types can be reset to a particular pc (where npc = pc +
sizeof(MachInst), nnpc = npc + sizeof(MachInst), upc = 0, nupc = 1 as
appropriate), printed, serialized, and compared. There is a branching()
function which encapsulates code in the CPU models that checked if an
instruction branched or not. Exactly what that means in the context of branch
delay slots which can skip an instruction when not taken is ambiguous, and
ideally this function and its uses can be eliminated. PCStates also generally
know how to advance themselves in various ways depending on if they point at
an instruction, a microop, or the last microop of a macroop. More on that
later.
Ideally, accessing all the PCs at once when setting them will improve
performance of M5 even though more data needs to be moved around. This is
because often all the PCs need to be manipulated together, and by getting them
all at once you avoid multiple function calls. Also, the PCs of a particular
thread will have spatial locality in the cache. Previously they were grouped
by element in arrays which spread out accesses.
Advancing the PC:
The PCs were previously managed entirely by the CPU which had to know about PC
semantics, try to figure out which dimension to increment the PC in, what to
set NPC/NNPC, etc. These decisions are best left to the ISA in conjunction
with the PC type itself. Because most of the information about how to
increment the PC (mainly what type of instruction it refers to) is contained
in the instruction object, a new advancePC virtual function was added to the
StaticInst class. Subclasses provide an implementation that moves around the
right element of the PC with a minimal amount of decision making. In ISAs like
Alpha, the instructions always simply assign NPC to PC without having to worry
about micropcs, nnpcs, etc. The added cost of a virtual function call should
be outweighed by not having to figure out as much about what to do with the
PCs and mucking around with the extra elements.
One drawback of making the StaticInsts advance the PC is that you have to
actually have one to advance the PC. This would, superficially, seem to
require decoding an instruction before fetch could advance. This is, as far as
I can tell, realistic. fetch would advance through memory addresses, not PCs,
perhaps predicting new memory addresses using existing ones. More
sophisticated decisions about control flow would be made later on, after the
instruction was decoded, and handed back to fetch. If branching needs to
happen, some amount of decoding needs to happen to see that it's a branch,
what the target is, etc. This could get a little more complicated if that gets
done by the predecoder, but I'm choosing to ignore that for now.
Variable length instructions:
To handle variable length instructions in x86 and ARM, the predecoder now
takes in the current PC by reference to the getExtMachInst function. It can
modify the PC however it needs to (by setting NPC to be the PC + instruction
length, for instance). This could be improved since the CPU doesn't know if
the PC was modified and always has to write it back.
ISA parser:
To support the new API, all PC related operand types were removed from the
parser and replaced with a PCState type. There are two warts on this
implementation. First, as with all the other operand types, the PCState still
has to have a valid operand type even though it doesn't use it. Second, using
syntax like PCS.npc(target) doesn't work for two reasons, this looks like the
syntax for operand type overriding, and the parser can't figure out if you're
reading or writing. Instructions that use the PCS operand (which I've
consistently called it) need to first read it into a local variable,
manipulate it, and then write it back out.
Return address stack:
The return address stack needed a little extra help because, in the presence
of branch delay slots, it has to merge together elements of the return PC and
the call PC. To handle that, a buildRetPC utility function was added. There
are basically only two versions in all the ISAs, but it didn't seem short
enough to put into the generic ISA directory. Also, the branch predictor code
in O3 and InOrder were adjusted so that they always store the PC of the actual
call instruction in the RAS, not the next PC. If the call instruction is a
microop, the next PC refers to the next microop in the same macroop which is
probably not desirable. The buildRetPC function advances the PC intelligently
to the next macroop (in an ISA specific way) so that that case works.
Change in stats:
There were no change in stats except in MIPS and SPARC in the O3 model. MIPS
runs in about 9% fewer ticks. SPARC runs with 30%-50% fewer ticks, which could
likely be improved further by setting call/return instruction flags and taking
advantage of the RAS.
TODO:
Add != operators to the PCState classes, defined trivially to be !(a==b).
Smooth out places where PCs are split apart, passed around, and put back
together later. I think this might happen in SPARC's fault code. Add ISA
specific constructors that allow setting PC elements without calling a bunch
of accessors. Try to eliminate the need for the branching() function. Factor
out Alpha's PAL mode pc bit into a separate flag field, and eliminate places
where it's blindly masked out or tested in the PC.
Gabe Black [Fri, 29 Oct 2010 09:20:47 +0000 (02:20 -0700)]
X86: Fault on divide by zero instead of panicing.
Gabe Black [Fri, 29 Oct 2010 09:20:46 +0000 (02:20 -0700)]
X86: Make syscalls also serialize after.
Gabe Black [Sun, 24 Oct 2010 07:43:32 +0000 (00:43 -0700)]
O3: Get rid of a bunch of commented out lines.
Gabe Black [Sat, 23 Oct 2010 03:59:22 +0000 (20:59 -0700)]
Configs: Stop setting the "mem" parameter in splash2 config files.
This parameter is no longer used, and trying to set it like these scripts were
gives a simobject two parents and causes the simulation to die.
Gabe Black [Fri, 22 Oct 2010 07:24:15 +0000 (00:24 -0700)]
X86: Make nop a regular, non-microcoded instruction.
Code in the CPUs that need a nop to carry a fault can't easily deal with a
microcoded nop. This instruction format provides for one that isn't.
--HG--
rename : src/arch/x86/isa/formats/syscall.isa => src/arch/x86/isa/formats/nop.isa
Gabe Black [Fri, 22 Oct 2010 07:24:08 +0000 (00:24 -0700)]
X86: Implement genMachineCheckFault.
Even though this shouldn't ever be used, it might get called speculatively and
shouldn't panic.
Gabe Black [Fri, 22 Oct 2010 07:23:50 +0000 (00:23 -0700)]
X86: Make syscall instructions non-speculative in SE.
Gabe Black [Fri, 22 Oct 2010 07:23:19 +0000 (00:23 -0700)]
ISA: Simplify various implementations of completeAcc.
Gabe Black [Fri, 22 Oct 2010 07:22:59 +0000 (00:22 -0700)]
ARM: Don't pretend to writeback registers in initiateAcc.
Steve Reinhardt [Mon, 18 Oct 2010 20:05:15 +0000 (13:05 -0700)]
cache: minor SC assertion fix
Thanks to Joe Gross for finding/testing this.
Gabe Black [Mon, 18 Oct 2010 06:15:53 +0000 (23:15 -0700)]
MIPS: Get rid of the backdoor device copy/pasted from and only used in Alpha.
Gabe Black [Sat, 16 Oct 2010 07:00:54 +0000 (00:00 -0700)]
Mem: Reclaim some request flags used by MIPS for alignment checking.
These flags were being used to identify what alignment a request needed, but
the same information is available using the request size. This change also
eliminates the isMisaligned function. If more complicated alignment checks are
needed, they can be signaled using the ASI_BITS space in the flags vector like
is currently done with ARM.
Gabe Black [Sat, 16 Oct 2010 06:57:06 +0000 (23:57 -0700)]
GetArgument: Rework getArgument so that X86_FS compiles again.
When no size is specified for an argument, push the decision about what size
to use into the ISA by passing a size of -1.
Gabe Black [Thu, 14 Oct 2010 21:02:23 +0000 (14:02 -0700)]
SPARC: Get rid of the copy/pasted StackTrace stolen from Alpha.
Gabe Black [Wed, 13 Oct 2010 08:57:31 +0000 (01:57 -0700)]
Mem: Change the CLREX flag to CLEAR_LL.
CLREX is the name of an ARM instruction, not a name for this generic flag.
Gabe Black [Mon, 11 Oct 2010 03:39:26 +0000 (20:39 -0700)]
X86: Detect attempts to load a 32 bit kernel and panic.
Gabe Black [Mon, 11 Oct 2010 03:38:05 +0000 (20:38 -0700)]
SPARC: Make SPARC's ISA's clear function initialize everything it should.
Also make it not set some pointers to NULL potentially introducing a memory
leak. That should be done in the constructor.
Gabe Black [Mon, 11 Oct 2010 03:37:50 +0000 (20:37 -0700)]
Alpha: Force all the IPRs to an initial, determinstic value when cleared.
Gabe Black [Mon, 11 Oct 2010 03:37:39 +0000 (20:37 -0700)]
Alpha: Initialize the data TLB mode IPR.
Gabe Black [Sat, 9 Oct 2010 19:41:31 +0000 (12:41 -0700)]
UART: Make the 8250's MCR return a deterministic value.
This change makes the 8250 device return the value it has for the MCR when
read instead of leaving the packet data unmodified/uninitialized. The value
the UART has for the MCR may not be right, but that's a seperate issue that
apparently hasn't caused any problems to date.
Gabe Black [Mon, 4 Oct 2010 18:58:06 +0000 (11:58 -0700)]
Alpha: Fix Alpha NumMiscArchRegs constant.
Also add asserts in O3's Scoreboard class to catch bad indexes.
Ali Saidi [Fri, 1 Oct 2010 22:57:56 +0000 (17:57 -0500)]
Power: Fix compile error from previous push.
Ali Saidi [Fri, 1 Oct 2010 21:04:04 +0000 (16:04 -0500)]
ARM: Make the TLB a little bit faster by moving most recently used items to front of list
Ali Saidi [Fri, 1 Oct 2010 21:04:02 +0000 (16:04 -0500)]
ARM: Add a fake flash controller so that unmodified linux can boot
With this change an unmodified Linux kernel can boot in M5.
Prakash Ramrakhyani [Fri, 1 Oct 2010 21:04:00 +0000 (16:04 -0500)]
ARM: Fix some subtle bugs in the GIC
The GIC code can write to the registers with 8, 16, or 32 byte
accesses which could set/clear different numbers of interrupts.
Ali Saidi [Fri, 1 Oct 2010 21:03:27 +0000 (16:03 -0500)]
ARM: Implement functional virtual to physical address translation
for debugging and program introspection.
Ali Saidi [Fri, 1 Oct 2010 21:02:46 +0000 (16:02 -0500)]
Debug: Implement getArgument() and function skipping for ARM.
In the process make add skipFuction() to handle isa specific function skipping
instead of ifdefs and other ugliness. For almost all ABIs, 64 bit arguments can
only start in even registers. Size is now passed to getArgument() so that 32
bit systems can make decisions about register selection for 64 bit arguments.
The number argument is now passed by reference because getArgument() will need
to change it based on the size of the argument and the current argument number.
For ARM, if the argument number is odd and a 64-bit register is requested the
number must first be incremented to because all 64 bit arguments are passed
in an even argument register. Then the number will be incremented again to
access both halves of the argument.
Ali Saidi [Fri, 1 Oct 2010 21:02:45 +0000 (16:02 -0500)]
ARM: Clean up use of TBit and JBit.
Rather tha constantly using ULL(1) << PcXBitShift define those directly.
Additionally, add some helper functions to further clean up the code.
Ali Saidi [Thu, 30 Sep 2010 14:35:19 +0000 (09:35 -0500)]
CPU/Cache: Fix some errors exposed by valgrind
Gabe Black [Wed, 29 Sep 2010 18:31:03 +0000 (11:31 -0700)]
X86: Fix the RIP relative versions of the BT, BTC, BTR, and BTS instructions.
Steve Reinhardt [Wed, 22 Sep 2010 15:45:35 +0000 (08:45 -0700)]
python: get rid of internal.enums package.
Move generated enums into internal.params, which gets
imported into object.params, restoring backward
compatibility for scripts that expect to find them there.
Steve Reinhardt [Wed, 22 Sep 2010 06:07:35 +0000 (23:07 -0700)]
stats: update stats for previous cset
Coherence protocol change basically got rid
of UpgradeReqs in L2 caches, other minor
related cache stat changes.
Steve Reinhardt [Wed, 22 Sep 2010 06:07:34 +0000 (23:07 -0700)]
cache: improve coherence handling of writebacks
If we write back an exclusive copy, we now mark it
as such, so the cache receiving the writeback can
mark its copy as exclusive. This avoids some
unnecessary upgrade requests when a cache later
tries to re-acquire exclusive access to the block.
Steve Reinhardt [Wed, 22 Sep 2010 06:07:34 +0000 (23:07 -0700)]
diff-out: clean up options
Make diff-out sort stats changes by percentage
by default, with '-a' to use current alpha sort
(instead of requiring '-p' to sort by percentage).
Other minor options cleanup too.
Steve Reinhardt [Wed, 22 Sep 2010 06:07:34 +0000 (23:07 -0700)]
tests: print if output files match
Add '-s' flag to diff command generating outdiff
file so we have positive confirmation when
outputs match.