Ahmed Irfan [Fri, 3 Apr 2015 14:45:14 +0000 (16:45 +0200)]
Update README
pmux cell is implemented
Ahmed Irfan [Fri, 3 Apr 2015 14:41:50 +0000 (16:41 +0200)]
separated memory next from write cell
Ahmed Irfan [Fri, 3 Apr 2015 14:38:07 +0000 (16:38 +0200)]
Merge branch 'master' of https://github.com/cliffordwolf/yosys
Ahmed Irfan [Fri, 3 Apr 2015 14:34:05 +0000 (16:34 +0200)]
Merge branch 'btor' of https://github.com/ahmedirfan1983/yosys into btor
Ahmed Irfan [Fri, 3 Apr 2015 14:20:29 +0000 (16:20 +0200)]
appnote for verilog to btor
Clifford Wolf [Sun, 29 Mar 2015 18:22:08 +0000 (20:22 +0200)]
documentation improvements
Clifford Wolf [Wed, 25 Mar 2015 18:46:12 +0000 (19:46 +0100)]
Ignore celldefine directive in verilog front-end
Clifford Wolf [Wed, 25 Mar 2015 08:00:41 +0000 (09:00 +0100)]
Fixes in cmos_cells.v
Clifford Wolf [Sun, 22 Mar 2015 10:03:56 +0000 (11:03 +0100)]
Fixed detection of absolute paths in ABC for win32
Clifford Wolf [Sun, 22 Mar 2015 08:49:46 +0000 (09:49 +0100)]
Added blif reference to appnote 010
Clifford Wolf [Fri, 20 Mar 2015 08:10:16 +0000 (09:10 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Fri, 20 Mar 2015 08:10:02 +0000 (09:10 +0100)]
fix for python 2.6.6
Clifford Wolf [Wed, 18 Mar 2015 15:03:19 +0000 (16:03 +0100)]
Fixed handling of quotes in liberty parser
Clifford Wolf [Wed, 18 Mar 2015 07:33:40 +0000 (08:33 +0100)]
Added hierarchy -auto-top
Clifford Wolf [Wed, 18 Mar 2015 07:01:37 +0000 (08:01 +0100)]
Added Verilog backend $dffsr support
Clifford Wolf [Fri, 6 Mar 2015 09:21:21 +0000 (10:21 +0100)]
Documentation for JSON format, added attributes
Clifford Wolf [Thu, 5 Mar 2015 19:37:55 +0000 (20:37 +0100)]
Added very first version of "synth_ice40"
Clifford Wolf [Wed, 4 Mar 2015 14:52:34 +0000 (15:52 +0100)]
Fixed bug in "hierarchy" for parametric designs
Clifford Wolf [Tue, 3 Mar 2015 08:41:41 +0000 (09:41 +0100)]
Json bugfix
Clifford Wolf [Tue, 3 Mar 2015 08:28:44 +0000 (09:28 +0100)]
Json backend improvements
Clifford Wolf [Mon, 2 Mar 2015 22:47:45 +0000 (23:47 +0100)]
Added write_blif -attr
Clifford Wolf [Mon, 2 Mar 2015 22:30:58 +0000 (23:30 +0100)]
Added JSON backend
Clifford Wolf [Sun, 1 Mar 2015 10:20:22 +0000 (11:20 +0100)]
Const-fold parameter defs on-demand in AstNode::detectSignWidthWorker()
Clifford Wolf [Thu, 26 Feb 2015 18:02:55 +0000 (19:02 +0100)]
Added $assume support to write_smt2
Clifford Wolf [Thu, 26 Feb 2015 17:47:39 +0000 (18:47 +0100)]
Added non-std verilog assume() statement
Clifford Wolf [Thu, 26 Feb 2015 17:04:10 +0000 (18:04 +0100)]
Added $assume cell type
Clifford Wolf [Wed, 25 Feb 2015 22:01:54 +0000 (23:01 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 25 Feb 2015 22:01:42 +0000 (23:01 +0100)]
Bugfix in iopadmap
Clifford Wolf [Wed, 25 Feb 2015 11:46:00 +0000 (12:46 +0100)]
Added "keep_hierarchy" attribute
Clifford Wolf [Tue, 24 Feb 2015 21:31:30 +0000 (22:31 +0100)]
Some cleanups in "clean"
Clifford Wolf [Tue, 24 Feb 2015 10:01:00 +0000 (11:01 +0100)]
Fixed compilation problems with gcc 4.6.3; use enum instead of const ints.
(original patch by Andrew Becker <andrew.becker@epfl.ch>)
Clifford Wolf [Sun, 22 Feb 2015 15:30:02 +0000 (16:30 +0100)]
Minor "write_smt2" help msg change
Clifford Wolf [Sun, 22 Feb 2015 15:29:44 +0000 (16:29 +0100)]
Fixed "check -assert"
Clifford Wolf [Sun, 22 Feb 2015 15:19:10 +0000 (16:19 +0100)]
Added "<mod>_a" and "<mod>_i" to write_smt2 output
Clifford Wolf [Sun, 22 Feb 2015 12:02:48 +0000 (13:02 +0100)]
Added "check -assert" doc
Clifford Wolf [Sun, 22 Feb 2015 12:00:41 +0000 (13:00 +0100)]
Added "check -assert"
Clifford Wolf [Sun, 22 Feb 2015 11:42:05 +0000 (12:42 +0100)]
Fixed "sat -initsteps" off-by-one bug
Clifford Wolf [Sat, 21 Feb 2015 21:52:49 +0000 (22:52 +0100)]
Added "sat -stepsize" and "sat -tempinduct-step"
Clifford Wolf [Sat, 21 Feb 2015 21:03:54 +0000 (22:03 +0100)]
sat docu change
Clifford Wolf [Sat, 21 Feb 2015 19:05:16 +0000 (20:05 +0100)]
When "sat -tempinduct-baseonly -maxsteps N" reaches maxsteps it is a good thing.
Clifford Wolf [Sat, 21 Feb 2015 16:53:22 +0000 (17:53 +0100)]
Added "sat -tempinduct-baseonly -tempinduct-inductonly"
Clifford Wolf [Sat, 21 Feb 2015 16:43:49 +0000 (17:43 +0100)]
Fixed basecase init for "sat -tempinduct"
Clifford Wolf [Sat, 21 Feb 2015 14:01:13 +0000 (15:01 +0100)]
Fixed "flatten" for non-pre-derived modules
Clifford Wolf [Sat, 21 Feb 2015 13:31:02 +0000 (14:31 +0100)]
Hotfix for yosysjs/demo03.html
Clifford Wolf [Sat, 21 Feb 2015 13:25:34 +0000 (14:25 +0100)]
YosysJS: Wait for Viz to load
Clifford Wolf [Sat, 21 Feb 2015 11:15:41 +0000 (12:15 +0100)]
Replaced ezDefaultSAT with ezSatPtr
Clifford Wolf [Sat, 21 Feb 2015 10:21:28 +0000 (11:21 +0100)]
Catch constants assigned to cell outputs in "flatten"
Clifford Wolf [Fri, 20 Feb 2015 09:33:20 +0000 (10:33 +0100)]
Added deep recursion warning to AST simplify
Clifford Wolf [Fri, 20 Feb 2015 09:21:36 +0000 (10:21 +0100)]
Parser support for complex delay expressions
Clifford Wolf [Thu, 19 Feb 2015 12:55:36 +0000 (13:55 +0100)]
YosysJS firefox fixes
Clifford Wolf [Thu, 19 Feb 2015 12:36:54 +0000 (13:36 +0100)]
YosysJS stuff
Clifford Wolf [Thu, 19 Feb 2015 12:19:04 +0000 (13:19 +0100)]
format fixes in "sat -dump_json"
Clifford Wolf [Thu, 19 Feb 2015 09:53:40 +0000 (10:53 +0100)]
Added "sat -dump_json" (WaveJSON format)
Clifford Wolf [Thu, 19 Feb 2015 08:11:38 +0000 (09:11 +0100)]
Changed "show" defaults for Win32
Clifford Wolf [Wed, 18 Feb 2015 22:35:23 +0000 (23:35 +0100)]
Convert floating point cell parameters to strings
Clifford Wolf [Wed, 18 Feb 2015 13:54:22 +0000 (14:54 +0100)]
Fixed clang (svn trunk) warnings
Clifford Wolf [Wed, 18 Feb 2015 06:19:03 +0000 (07:19 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Wed, 18 Feb 2015 06:18:34 +0000 (07:18 +0100)]
Added "select %xe %cie %coe"
Clifford Wolf [Tue, 17 Feb 2015 12:02:16 +0000 (13:02 +0100)]
wreduce help typo fix
Clifford Wolf [Tue, 17 Feb 2015 12:01:01 +0000 (13:01 +0100)]
CodingReadme
Clifford Wolf [Mon, 16 Feb 2015 13:10:00 +0000 (14:10 +0100)]
YosysJS fixes for firefox
Clifford Wolf [Mon, 16 Feb 2015 12:23:54 +0000 (13:23 +0100)]
More YosysJS stuff
Clifford Wolf [Mon, 16 Feb 2015 11:41:48 +0000 (12:41 +0100)]
Added YosysJS wrapper
Clifford Wolf [Mon, 16 Feb 2015 08:08:00 +0000 (09:08 +0100)]
Bugfix in wreduce
Clifford Wolf [Sun, 15 Feb 2015 23:11:22 +0000 (00:11 +0100)]
More yosys.js improvements
Clifford Wolf [Sun, 15 Feb 2015 21:53:41 +0000 (22:53 +0100)]
Added Viz to yosys.js
Clifford Wolf [Sun, 15 Feb 2015 17:10:54 +0000 (18:10 +0100)]
Added yosys.js FS support
Clifford Wolf [Sun, 15 Feb 2015 16:14:09 +0000 (17:14 +0100)]
More emcc stuff
Clifford Wolf [Sun, 15 Feb 2015 15:16:08 +0000 (16:16 +0100)]
Improved yosys.js example
Clifford Wolf [Sun, 15 Feb 2015 12:25:15 +0000 (13:25 +0100)]
Added "stat" to "synth" and "synth_xilinx"
Clifford Wolf [Sun, 15 Feb 2015 12:00:00 +0000 (13:00 +0100)]
Added final checks to "synth" and "synth_xilinx"
Clifford Wolf [Sun, 15 Feb 2015 11:58:12 +0000 (12:58 +0100)]
Added "check -noinit"
Clifford Wolf [Sun, 15 Feb 2015 11:57:41 +0000 (12:57 +0100)]
Cosmetic fixes in "hierarchy" for blackbox modules
Clifford Wolf [Sun, 15 Feb 2015 11:09:30 +0000 (12:09 +0100)]
More emscripten stuff, Added example app
Clifford Wolf [Sun, 15 Feb 2015 09:30:29 +0000 (10:30 +0100)]
Fixed default EMCCFLAGS
Clifford Wolf [Sat, 14 Feb 2015 23:20:05 +0000 (00:20 +0100)]
Smaller default parameters in $mem simlib model
Clifford Wolf [Sat, 14 Feb 2015 21:36:34 +0000 (22:36 +0100)]
Fixed "stat" handling of blackbox modules
Clifford Wolf [Sat, 14 Feb 2015 13:21:15 +0000 (14:21 +0100)]
Various fixes for memories with offsets
Clifford Wolf [Sat, 14 Feb 2015 11:55:03 +0000 (12:55 +0100)]
Added $meminit support to "memory" command
Clifford Wolf [Sat, 14 Feb 2015 10:26:20 +0000 (11:26 +0100)]
Added $meminit test case
Clifford Wolf [Sat, 14 Feb 2015 10:21:12 +0000 (11:21 +0100)]
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf [Sat, 14 Feb 2015 09:49:30 +0000 (10:49 +0100)]
Creating $meminit cells in verilog front-end
Clifford Wolf [Sat, 14 Feb 2015 09:23:03 +0000 (10:23 +0100)]
Added $meminit cell type
Clifford Wolf [Sat, 14 Feb 2015 07:41:03 +0000 (08:41 +0100)]
Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf [Fri, 13 Feb 2015 21:48:10 +0000 (22:48 +0100)]
Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf [Fri, 13 Feb 2015 13:40:49 +0000 (14:40 +0100)]
hotfix in "check" command
Clifford Wolf [Fri, 13 Feb 2015 13:34:51 +0000 (14:34 +0100)]
Added "check" command
Clifford Wolf [Fri, 13 Feb 2015 11:33:12 +0000 (12:33 +0100)]
Added AstNode::simplify() recursion counter
Clifford Wolf [Fri, 13 Feb 2015 11:32:04 +0000 (12:32 +0100)]
Added EMCCFLAGS
Clifford Wolf [Thu, 12 Feb 2015 16:45:44 +0000 (17:45 +0100)]
Some test related fixes
(incl. removal of three bad test cases)
Clifford Wolf [Thu, 12 Feb 2015 15:56:01 +0000 (16:56 +0100)]
Added "proc_dlatch"
Clifford Wolf [Tue, 10 Feb 2015 19:51:37 +0000 (20:51 +0100)]
Less aggressive "share" defaults
Clifford Wolf [Tue, 10 Feb 2015 11:17:29 +0000 (12:17 +0100)]
Improved read_verilog support for empty behavioral statements
Clifford Wolf [Tue, 10 Feb 2015 07:48:55 +0000 (08:48 +0100)]
Added "scc -expect <N> -nofeedback"
Clifford Wolf [Mon, 9 Feb 2015 19:11:51 +0000 (20:11 +0100)]
Some hashlib improvements
Clifford Wolf [Mon, 9 Feb 2015 15:36:37 +0000 (16:36 +0100)]
Various changes to release checklist
Clifford Wolf [Mon, 9 Feb 2015 12:24:29 +0000 (13:24 +0100)]
Fixed creation of command reference in manual
Clifford Wolf [Mon, 9 Feb 2015 12:12:48 +0000 (13:12 +0100)]
We are now in 0.5+ development
Clifford Wolf [Mon, 9 Feb 2015 11:49:52 +0000 (12:49 +0100)]
Yosys 0.5
Clifford Wolf [Mon, 9 Feb 2015 11:48:15 +0000 (12:48 +0100)]
Bugfix in "make vcxsrc"