Clifford Wolf [Mon, 14 Oct 2019 03:24:31 +0000 (05:24 +0200)]
Use "(id)" instead of "id" for types as temporary hack
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanović [Thu, 10 Oct 2019 12:09:32 +0000 (14:09 +0200)]
Merge pull request #1445 from YosysHQ/mwk/xilinx_ibufg
xilinx: Add simulation model for IBUFG.
Marcin Kościelnicki [Thu, 10 Oct 2019 09:31:33 +0000 (11:31 +0200)]
xilinx: Add simulation model for IBUFG.
Eddie Hung [Tue, 8 Oct 2019 19:41:26 +0000 (12:41 -0700)]
Revert "Add test that is expecting to fail"
This reverts commit
c28d4b804720c2cf0086e921748219150e9631b5.
Eddie Hung [Tue, 8 Oct 2019 19:41:24 +0000 (12:41 -0700)]
Revert "Be mindful that sigmap(wire) could have dupes when checking \init"
This reverts commit
f46ac1df9f8847dac9d9851f2f948d93a1064ff1.
Eddie Hung [Tue, 8 Oct 2019 19:38:29 +0000 (12:38 -0700)]
Merge pull request #1432 from YosysHQ/eddie/fix1427
Refactor peepopt_dffmux and be sensitive to \init when trimming
Eddie Hung [Tue, 8 Oct 2019 17:53:44 +0000 (10:53 -0700)]
Merge pull request #1433 from YosysHQ/eddie/equiv_opt_async2sync
async2sync to be called by equiv_opt only when -async2sync given
Eddie Hung [Tue, 8 Oct 2019 17:53:38 +0000 (10:53 -0700)]
Merge pull request #1437 from YosysHQ/eddie/abc_to_abc9
Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung [Tue, 8 Oct 2019 17:53:30 +0000 (10:53 -0700)]
Merge pull request #1438 from YosysHQ/eddie/xilinx_dsp_comments
Add notes and comments for xilinx_dsp
Clifford Wolf [Sun, 6 Oct 2019 10:11:20 +0000 (12:11 +0200)]
Merge pull request #1439 from YosysHQ/eddie/fix_ice40_wrapcarry
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
Eddie Hung [Sat, 5 Oct 2019 16:27:12 +0000 (09:27 -0700)]
Missing 'accept' at end of ice40_wrapcarry, spotted by @cliffordwolf
Clifford Wolf [Sat, 5 Oct 2019 16:13:04 +0000 (18:13 +0200)]
Update README.md
Eddie Hung [Sat, 5 Oct 2019 15:57:37 +0000 (08:57 -0700)]
Missed this
Eddie Hung [Sat, 5 Oct 2019 15:56:37 +0000 (08:56 -0700)]
Add comment on why we have to match for clock-enable/reset muxes
Eddie Hung [Sat, 5 Oct 2019 15:53:01 +0000 (08:53 -0700)]
Add note on pattern detector
Miodrag Milanović [Sat, 5 Oct 2019 05:48:30 +0000 (07:48 +0200)]
Merge pull request #1436 from YosysHQ/mmicko/msvc_fix
Fixes for MSVC build
Eddie Hung [Sat, 5 Oct 2019 05:30:14 +0000 (22:30 -0700)]
Add comment on why partial multipliers are 18x18
Eddie Hung [Sat, 5 Oct 2019 05:25:30 +0000 (22:25 -0700)]
Add comments for xilinx_dsp_cascade
Eddie Hung [Sat, 5 Oct 2019 05:24:15 +0000 (22:24 -0700)]
Improve comments for xilinx_dsp_CREG
Eddie Hung [Sat, 5 Oct 2019 04:45:31 +0000 (21:45 -0700)]
Fix comment
Eddie Hung [Sat, 5 Oct 2019 04:42:46 +0000 (21:42 -0700)]
Restore optimisation for sigM.empty()
Eddie Hung [Fri, 4 Oct 2019 20:38:09 +0000 (13:38 -0700)]
Retry on fixing TODOs
Eddie Hung [Fri, 4 Oct 2019 20:33:27 +0000 (13:33 -0700)]
Revert "Fix TODOs"
This reverts commit
8674a6c68d563908014d16671567459499c6dc99.
Eddie Hung [Fri, 4 Oct 2019 20:31:44 +0000 (13:31 -0700)]
More comments, cleanup
Eddie Hung [Fri, 4 Oct 2019 19:43:56 +0000 (12:43 -0700)]
Fix TODOs
Eddie Hung [Fri, 4 Oct 2019 19:43:19 +0000 (12:43 -0700)]
Consistency
Eddie Hung [Fri, 4 Oct 2019 19:40:34 +0000 (12:40 -0700)]
Add comments for xilinx_dsp
Eddie Hung [Sat, 5 Oct 2019 04:43:15 +0000 (21:43 -0700)]
Fix typo in check_label()
Eddie Hung [Sat, 5 Oct 2019 00:53:20 +0000 (17:53 -0700)]
Merge branch 'master' into eddie/abc_to_abc9
Eddie Hung [Sat, 5 Oct 2019 00:35:43 +0000 (17:35 -0700)]
Add temporary `abc9 -nomfs` and use for `synth_xilinx -abc9`
Eddie Hung [Sat, 5 Oct 2019 00:26:42 +0000 (17:26 -0700)]
Remove DSP48E1 from *_cells_xtra.v
Eddie Hung [Fri, 4 Oct 2019 23:46:15 +0000 (16:46 -0700)]
Fix xilinx_dsp for unsigned extensions
Eddie Hung [Fri, 4 Oct 2019 23:45:36 +0000 (16:45 -0700)]
Fix for SigSpec() == SigSpec(State::Sx, 0) to be true again
Eddie Hung [Fri, 4 Oct 2019 20:31:33 +0000 (13:31 -0700)]
Add Const::{begin,end,empty}()
Eddie Hung [Fri, 4 Oct 2019 18:04:10 +0000 (11:04 -0700)]
Rename abc_* names/attributes to more precisely be abc9_*
Eddie Hung [Fri, 4 Oct 2019 17:48:44 +0000 (10:48 -0700)]
Panic over. Model was elsewhere. Re-arrange for consistency
Eddie Hung [Fri, 4 Oct 2019 17:36:02 +0000 (10:36 -0700)]
Oops
Eddie Hung [Fri, 4 Oct 2019 17:34:16 +0000 (10:34 -0700)]
Ohmilord this wasn't added all this time!?!
Eddie Hung [Fri, 4 Oct 2019 17:17:46 +0000 (10:17 -0700)]
Add -async2sync to help text as per @daveshah1
Miodrag Milanovic [Fri, 4 Oct 2019 14:29:46 +0000 (16:29 +0200)]
Fixes for MSVC build
Eddie Hung [Thu, 3 Oct 2019 18:11:50 +0000 (11:11 -0700)]
Use `sat -tempinduct` and comments for why equiv_opt not sufficient
Eddie Hung [Thu, 3 Oct 2019 17:51:53 +0000 (10:51 -0700)]
Restore part of doc
Eddie Hung [Thu, 3 Oct 2019 17:45:53 +0000 (10:45 -0700)]
Disable equiv check for ice40 latches
Eddie Hung [Thu, 3 Oct 2019 17:30:51 +0000 (10:30 -0700)]
Add new -async2sync option
Eddie Hung [Thu, 3 Oct 2019 17:30:33 +0000 (10:30 -0700)]
Use equiv_opt -async2sync for xilinx
Eddie Hung [Thu, 3 Oct 2019 17:07:15 +0000 (10:07 -0700)]
Revert "equiv_opt to call async2sync when not -multiclock like SymbiYosys"
This reverts commit
a39505e329cc05dbd4ad624a1cf0f6caf664fd9a.
Eddie Hung [Thu, 3 Oct 2019 17:07:03 +0000 (10:07 -0700)]
Revert "Update doc for equiv_opt"
This reverts commit
a274b7cc86d4f64541d3d2903b4eeed4616ab1d8.
Clifford Wolf [Thu, 3 Oct 2019 12:59:07 +0000 (14:59 +0200)]
Change smtbmc "Warmup failed" status to "PREUNSAT"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 3 Oct 2019 12:05:21 +0000 (14:05 +0200)]
Update ABC to git rev
623b5e8
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 3 Oct 2019 10:26:08 +0000 (12:26 +0200)]
Bump version
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Thu, 3 Oct 2019 10:06:12 +0000 (12:06 +0200)]
Merge pull request #1419 from YosysHQ/eddie/lazy_derive
module->derive() to be lazy and not touch ast if already derived
Clifford Wolf [Thu, 3 Oct 2019 09:54:04 +0000 (11:54 +0200)]
Merge pull request #1422 from YosysHQ/eddie/aigmap_select
Add -select option to aigmap
Clifford Wolf [Thu, 3 Oct 2019 09:50:53 +0000 (11:50 +0200)]
Merge pull request #1429 from YosysHQ/clifford/checkmapped
Add "check -mapped"
Clifford Wolf [Thu, 3 Oct 2019 09:49:56 +0000 (11:49 +0200)]
Add "check -allow-tbuf"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
David Shah [Thu, 3 Oct 2019 08:55:43 +0000 (09:55 +0100)]
frontends/ast: code style
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 17:40:35 +0000 (18:40 +0100)]
sv: Improve tests
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 17:40:23 +0000 (18:40 +0100)]
sv: Fix typedefs in blocks
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 15:12:09 +0000 (16:12 +0100)]
sv: Disambiguate interface ports
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 12:01:47 +0000 (13:01 +0100)]
Update CHANGELOG and README
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 12:00:26 +0000 (13:00 +0100)]
sv: Add test scripts for typedefs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 11:11:17 +0000 (12:11 +0100)]
sv: Fix memories of typedefs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 10:59:33 +0000 (11:59 +0100)]
sv: Add %expect
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 10:46:37 +0000 (11:46 +0100)]
sv: Add support for memories of a typedef
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Fri, 20 Sep 2019 10:39:15 +0000 (11:39 +0100)]
sv: Add support for memory typedefs
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 19 Sep 2019 20:21:21 +0000 (21:21 +0100)]
sv: Fix typedefs in packages
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 19 Sep 2019 20:07:20 +0000 (21:07 +0100)]
sv: Fix typedef parameters
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 19 Sep 2019 19:43:13 +0000 (20:43 +0100)]
sv: Switch parser to glr, prep for typedef
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Thu, 3 Oct 2019 08:53:45 +0000 (09:53 +0100)]
Merge pull request #1425 from YosysHQ/dave/ecp5_pdp16
ecp5: Add support for mapping 36-bit wide PDP BRAMs
Eddie Hung [Thu, 3 Oct 2019 04:26:26 +0000 (21:26 -0700)]
Fix broken CI, check reset even for constants, trim rstmux
Eddie Hung [Thu, 3 Oct 2019 02:40:39 +0000 (19:40 -0700)]
Merge pull request #1423 from YosysHQ/eddie/techmap_replace_wire
RFC: techmap to recognise wires named "_TECHMAP_REPLACE_.<suffix>"
Eddie Hung [Thu, 3 Oct 2019 01:12:25 +0000 (18:12 -0700)]
Fix test
Eddie Hung [Thu, 3 Oct 2019 01:07:38 +0000 (18:07 -0700)]
Merge branch 'eddie/fix_sat_init' into eddie/fix1427
Eddie Hung [Thu, 3 Oct 2019 01:03:45 +0000 (18:03 -0700)]
Update test
Eddie Hung [Thu, 3 Oct 2019 00:53:42 +0000 (17:53 -0700)]
Refactor peepopt_dffmux and be sensitive to \init when trimming
Eddie Hung [Thu, 3 Oct 2019 00:48:55 +0000 (17:48 -0700)]
Add test
Eddie Hung [Thu, 3 Oct 2019 00:49:07 +0000 (17:49 -0700)]
log_dump() to support State enum
Eddie Hung [Wed, 2 Oct 2019 23:08:46 +0000 (16:08 -0700)]
Be mindful that sigmap(wire) could have dupes when checking \init
Eddie Hung [Wed, 2 Oct 2019 21:52:40 +0000 (14:52 -0700)]
Add test that is expecting to fail
Eddie Hung [Wed, 2 Oct 2019 19:43:35 +0000 (12:43 -0700)]
Also rename cells with _TECHMAP_REPLACE_. prefix, as per @cliffordwolf
Eddie Hung [Wed, 2 Oct 2019 19:43:18 +0000 (12:43 -0700)]
Extend test with renaming cells with prefix too
Clifford Wolf [Wed, 2 Oct 2019 11:48:09 +0000 (13:48 +0200)]
Merge pull request #1428 from YosysHQ/clifford/fixbtor
Fix btor back-end to use "state" instead of "input" for undef init bits
Clifford Wolf [Wed, 2 Oct 2019 11:35:03 +0000 (13:35 +0200)]
Add "check -mapped"
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Clifford Wolf [Wed, 2 Oct 2019 10:48:04 +0000 (12:48 +0200)]
Fix btor back-end to use "state" instead of "input" for undef init bits
Signed-off-by: Clifford Wolf <clifford@clifford.at>
Miodrag Milanović [Tue, 1 Oct 2019 17:50:37 +0000 (19:50 +0200)]
Merge pull request #1426 from YosysHQ/mmicko/fix_environ
Define environ, fixes #1424
Miodrag Milanovic [Tue, 1 Oct 2019 16:45:07 +0000 (18:45 +0200)]
Define environ, fixes #1424
David Shah [Tue, 1 Oct 2019 13:14:46 +0000 (14:14 +0100)]
ecp5: Fix shuffle_enable port
Signed-off-by: David Shah <dave@ds0.me>
David Shah [Tue, 1 Oct 2019 12:46:36 +0000 (13:46 +0100)]
ecp5: Add support for mapping 36-bit wide PDP BRAMs
Signed-off-by: David Shah <dave@ds0.me>
Eddie Hung [Tue, 1 Oct 2019 00:20:39 +0000 (17:20 -0700)]
Add test
Eddie Hung [Tue, 1 Oct 2019 00:20:12 +0000 (17:20 -0700)]
techmap wires named _TECHMAP_REPLACE_.<identifier> to create alias
Eddie Hung [Mon, 30 Sep 2019 22:34:04 +0000 (15:34 -0700)]
Add quick test
Eddie Hung [Sat, 28 Sep 2019 00:44:01 +0000 (17:44 -0700)]
Add -select option to aigmap
Eddie Hung [Sat, 28 Sep 2019 00:00:19 +0000 (17:00 -0700)]
Fix typo
Eddie Hung [Mon, 30 Sep 2019 21:52:04 +0000 (14:52 -0700)]
Fix for svinterfaces
Eddie Hung [Mon, 30 Sep 2019 21:11:01 +0000 (14:11 -0700)]
module->derive() to be lazy and not touch ast if already derived
Eddie Hung [Mon, 30 Sep 2019 17:59:56 +0000 (10:59 -0700)]
Update doc for equiv_opt
whitequark [Mon, 30 Sep 2019 17:38:20 +0000 (17:38 +0000)]
Merge pull request #1406 from whitequark/connect_rpc
rpc: new frontend
Eddie Hung [Mon, 30 Sep 2019 17:31:57 +0000 (10:31 -0700)]
Merge pull request #1397 from btut/fix/python_wrappers_inline_constructors
Generate Python wrappers for inline constructors
whitequark [Thu, 26 Sep 2019 03:57:16 +0000 (03:57 +0000)]
rpc: new frontend.
A new pass, connect_rpc, allows any HDL frontend that can read/write
JSON from/to stdin/stdout or an unix socket or a named pipe to
participate in elaboration as a first class citizen, such that any
other HDL supported by Yosys directly or indirectly can transparently
instantiate modules handled by this frontend.
Recognizing that many HDL frontends emit Verilog, it allows the RPC
frontend to direct Yosys to process the result of instantiation via
any built-in Yosys frontend. The resulting RTLIL is then hygienically
integrated into the overall design.
whitequark [Thu, 26 Sep 2019 02:11:22 +0000 (02:11 +0000)]
libs: import json11.
This commit imports the code from upstream commit
dropbox/json11@
8ccf1f0c5ecab6151a65f216e7eeccd8588e5457.
Miodrag Milanović [Mon, 30 Sep 2019 15:49:23 +0000 (17:49 +0200)]
Merge pull request #1416 from YosysHQ/mmicko/frontend_binary_in
Open aig frontend as binary file