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Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 14:23:28 +0000 (15:23 +0100)]
whitespace
Staf Verhaegen [Thu, 1 Apr 2021 12:49:55 +0000 (14:49 +0200)]
Document c4m-jtag dependency.
Luke Kenneth Casson Leighton [Thu, 1 Apr 2021 12:23:58 +0000 (13:23 +0100)]
disable PLL for litex build, new variant
Staf Verhaegen [Thu, 1 Apr 2021 12:10:07 +0000 (14:10 +0200)]
Fix svf file for limited c4m-jtag SVF grammar.
Staf Verhaegen [Thu, 1 Apr 2021 11:23:04 +0000 (13:23 +0200)]
First setup for cocotb test run.
Currently only test bench is using Icarus Verilog on pre-layout design
without SRAMs.
Luke Kenneth Casson Leighton [Tue, 30 Mar 2021 10:53:41 +0000 (11:53 +0100)]
update Makefile to build 4ksrams
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 18:12:50 +0000 (19:12 +0100)]
move name of XICS ICS/ICP to match latest litex pythondata-microwatt
Luke Kenneth Casson Leighton [Mon, 29 Mar 2021 17:57:06 +0000 (18:57 +0100)]
must not add bus width parameter
Luke Kenneth Casson Leighton [Sun, 28 Mar 2021 17:03:35 +0000 (18:03 +0100)]
fix issues with port direction on several pads
Luke Kenneth Casson Leighton [Sat, 27 Mar 2021 14:24:38 +0000 (14:24 +0000)]
latest fighting with litex to get pad directions connected up
Luke Kenneth Casson Leighton [Thu, 25 Mar 2021 06:08:27 +0000 (06:08 +0000)]
debugging ls180 litex hell
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:51:02 +0000 (12:51 +0000)]
sort out naming of IOpads for bi-directional pins
Luke Kenneth Casson Leighton [Mon, 22 Mar 2021 12:50:42 +0000 (12:50 +0000)]
SDR pad mask output for DM
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 14:14:38 +0000 (14:14 +0000)]
unneeded file
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 13:50:42 +0000 (13:50 +0000)]
splitting out litex files from soc repo into separate repo
Luke Kenneth Casson Leighton [Fri, 12 Mar 2021 13:42:15 +0000 (13:42 +0000)]
first (empty) commit
projects / libresoc-litex.git / log