Nilay Vaish [Sun, 30 Dec 2012 18:45:50 +0000 (12:45 -0600)]
x86: implement x87 fp instruction fnstsw
This patch implements the fnstsw instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.
Nilay Vaish [Sun, 30 Dec 2012 18:45:45 +0000 (12:45 -0600)]
x86: implement x87 fp instruction fsincos
This patch implements the fsincos instruction. The code was originally written
by Vince Weaver. Gabe had made some comments about the code, but those were
never addressed. This patch addresses those comments.
Nilay Vaish [Wed, 12 Dec 2012 15:51:55 +0000 (09:51 -0600)]
arm regressions: updates to config.ini, terminal files
Nathanael Premillieu [Wed, 12 Dec 2012 15:50:33 +0000 (09:50 -0600)]
arm: set uopSet_uop as conditional or unconditional control
uopSet_uop is microop instruction that has the IsControl flags set, but the
IsCondControl or IsUncondControl flags seems not to be set, neither in
the construction nor where the microop is used. This patch adds the the
flags in the constructor of the instruction (MicroUopSetPCCPSR).
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nathanael Premillieu [Wed, 12 Dec 2012 15:50:16 +0000 (09:50 -0600)]
arm: set movret_uop as conditional or unconditional control
A flag was missing for the movret_uop microop instruction. This patch adds
that flag when the instruction is used, not directly in the constructor of
the instruction.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nilay Vaish [Tue, 11 Dec 2012 16:06:01 +0000 (10:06 -0600)]
regressions: stats update due to stats from ruby prefetcher
Nilay Vaish [Tue, 11 Dec 2012 16:05:56 +0000 (10:05 -0600)]
ruby: add support for prefetching to MESI protocol
Nilay Vaish [Tue, 11 Dec 2012 16:05:55 +0000 (10:05 -0600)]
ruby: modify the directed tester to read/write streams
The directed tester supports only generating only read or only write accesses. The
patch modifies the tester to support streams that have both read and write accesses.
Nilay Vaish [Tue, 11 Dec 2012 16:05:55 +0000 (10:05 -0600)]
ruby: change slicc to allow for constructor args
The patch adds support to slicc for recognizing arguments that should be
passed to the constructor of a class. I did not like the fact that an explicit
check was being carried on the type 'TBETable' to figure out the arguments to
be passed to the constructor.
The patch also moves some of the member variables that are declared for all
the controllers to the base class AbstractController.
Nilay Vaish [Tue, 11 Dec 2012 16:05:54 +0000 (10:05 -0600)]
ruby: add a prefetcher
This patch adds a prefetcher for the ruby memory system. The prefetcher
is based on a prefetcher implemented by others (well, I don't know
who wrote the original). The prefetcher does stride-based prefetching,
both unit and non-unit. It obseves the misses in the cache and trains on
these. After the training period is over, the prefetcher starts issuing
prefetch requests to the controller.
Nilay Vaish [Tue, 11 Dec 2012 16:05:53 +0000 (10:05 -0600)]
ruby: add functions for computing next stride/page address
Nilay Vaish [Thu, 6 Dec 2012 16:26:12 +0000 (10:26 -0600)]
regression test: update a couple of config.ini files
Erik Tomusk [Thu, 6 Dec 2012 15:31:06 +0000 (09:31 -0600)]
TournamentBP: Fix some bugs with table sizes and counters
globalHistoryBits, globalPredictorSize, and choicePredictorSize are decoupled.
globalHistoryBits controls how much history is kept, global and choice
predictor sizes control how much of that history is used when accessing
predictor tables. This way, global and choice predictors can actually be
different sizes, and it is no longer possible to walk off the predictor arrays
and cause a seg fault.
There are now individual thresholds for choice, global, and local saturating
counters, so that taken/not taken decisions are correct even when the
predictors' counters' sizes are different.
The interface for localPredictorSize has been removed from TournamentBP because
the value can be calculated from localHistoryBits.
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Malek Musleh [Thu, 6 Dec 2012 11:25:40 +0000 (05:25 -0600)]
inorder cpu: add missing DPRINTF argument
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Nathanael Premillieu [Thu, 6 Dec 2012 10:36:51 +0000 (04:36 -0600)]
o3 cpu: remove some unused buggy functions in the lsq
Committed by: Nilay Vaish <nilay@cs.wisc.edu>
Andreas Hansson [Mon, 19 Nov 2012 16:21:09 +0000 (11:21 -0500)]
config: Fix description of checkpoint option from cycle to tick
This patch merely updates the description of the "take-checkpoints"
option to reflect that it is specified in ticks and not in cycles.
Nilay Vaish [Fri, 16 Nov 2012 16:27:47 +0000 (10:27 -0600)]
sim: have a curTick per eventq
This patch adds a _curTick variable to an eventq. This variable is updated
whenever an event is serviced in function serviceOne(), or all events upto
a particular time are processed in function serviceEvents(). This change
helps when there are eventqs that do not make use of curTick for scheduling
events.
Nilay Vaish [Sat, 10 Nov 2012 23:18:02 +0000 (17:18 -0600)]
regressions: stats update due to ruby functional access patch
Nilay Vaish [Sat, 10 Nov 2012 23:18:01 +0000 (17:18 -0600)]
ruby: support functional accesses in garnet flexible network
Nilay Vaish [Sat, 10 Nov 2012 23:18:00 +0000 (17:18 -0600)]
ruby: bug in functionalRead, revert recent changes
Recent changes to functionalRead() in the memory system was not correct.
The change allowed for returning data from the first message found in
the buffers of the memory system. This is not correct since it is possible
that a timing message has data from an older state of the block.
The changes are being reverted.
Andreas Hansson [Thu, 8 Nov 2012 09:25:06 +0000 (04:25 -0500)]
mem: Fix DRAM draining to ensure write queue is empty
This patch fixes the draining of the SimpleDRAM controller model. The
controller performs buffering of writes and normally there is no need
to ever empty the write buffer (if you have a fast on-chip memory,
then use it). The patch adds checks to ensure the write buffer is
drained when the controller is asked to do so.
Lluis Vilanova [Sat, 3 Nov 2012 17:57:28 +0000 (12:57 -0500)]
x86, util: add m5_writefile to m5op_x86.S
Committed by: Nilay Vaish
ruby: reset and dump stats along with reset of the system
This patch adds support to ruby so that the statistics maintained by ruby
are reset/dumped when the statistics for the rest of the system are
reset/dumped. For resetting the statistics, ruby now provides the
resetStats() function that a sim object can provide. As a consequence, the
clearStats() function has been removed from RubySystem. For dumping stats,
Ruby now adds a callback event to the dumpStatsQueue. The exit callback that
ruby used to add earlier is being removed.
Created by: Hamid Reza Khaleghzadeh.
Improved by: Lluc Alvarez, Nilay Vaish
Committed by: Nilay Vaish
Ali Saidi [Fri, 2 Nov 2012 16:50:16 +0000 (11:50 -0500)]
mem: fix use after free issue in memories until 4-phase work complete.
Ali Saidi [Fri, 2 Nov 2012 16:50:06 +0000 (11:50 -0500)]
update stats for preceeding changes
Andreas Sandberg [Fri, 2 Nov 2012 16:32:02 +0000 (11:32 -0500)]
mem: Add support for writing back and flushing caches
This patch adds support for the following optional drain methods in
the classical memory system's cache model:
memWriteback() - Write back all dirty cache lines to memory using
functional accesses.
memInvalidate() - Invalidate all cache lines. Dirty cache lines
are lost unless a writeback is requested.
Since memWriteback() is called when checkpointing systems, this patch
adds support for checkpointing systems with caches. The serialization
code now checks whether there are any dirty lines in the cache. If
there are dirty lines in the cache, the checkpoint is flagged as bad
and a warning is printed.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:02 +0000 (11:32 -0500)]
sim: Add drain methods to request additional cleanup operations
This patch adds the following two methods to the Drainable base class:
memWriteback() - Write back all dirty cache lines to memory using
functional accesses.
memInvalidate() - Invalidate memory system buffers. Dirty data
won't be written back.
Specifying calling memWriteback() after draining will allow us to
checkpoint systems with caches. memInvalidate() can be used to drop
memory system buffers in preparation for switching to an accelerated
CPU model that bypasses the gem5 memory system (e.g., hardware
virtualized CPUs).
Note: This patch only adds the methods to Drainable, the code for
flushing the TLB and the cache is committed separately.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:02 +0000 (11:32 -0500)]
sim: Add SWIG interface for Serializable
This changeset adds a SWIG interface for the Serializable class, which
fixes a warning when compiling the SWIG interface for the event
queue. Currently, the only method exported is the name() method.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:02 +0000 (11:32 -0500)]
python: Rename doDrain()->drain() and make it do the right thing
There is no point in exporting the old drain() method in
Simulate.py. It should only be used internally by doDrain(). This
patch moves the old drain() method into doDrain() and renames
doDrain() to drain().
Andreas Sandberg [Fri, 2 Nov 2012 16:32:02 +0000 (11:32 -0500)]
sim: Reuse the code to change memory mode.
changeToAtomic and changeToTiming both do essentially the same thing,
they check the type of their input argument, drain the system, and
switch to the desired memory mode. This patch moves all of that code
to a separate method (changeMemoryMode) and calls that from both
changeToAtomic and changeToTiming.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
sim: Move the draining interface into a separate base class
This patch moves the draining interface from SimObject to a separate
class that can be used by any object needing draining. However,
objects not visible to the Python code (i.e., objects not deriving
from SimObject) still depend on their parents informing them when to
drain. This patch also gets rid of the CountedDrainEvent (which isn't
really an event) and replaces it with a DrainManager.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
cpu: O3 add a header declaring the DerivO3CPU
SWIG needs a complete declaration of all wrapped objects. This patch
adds a header file with the DerivO3CPU class and includes it in the
SWIG interface.
--HG--
rename : src/cpu/o3/cpu_builder.cc => src/cpu/o3/deriv.cc
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
cpu: Add header files for checker CPUs
In order to create reliable SWIG wrappers, we need to include the
declaration of the wrapped class in the SWIG file. Previously, we
didn't expose the declaration of checker CPUs. This patch adds header
files for such CPUs and include them in the SWIG wrapper.
--HG--
rename : src/cpu/dummy_checker_builder.cc => src/cpu/dummy_checker.cc
rename : src/cpu/o3/checker_builder.cc => src/cpu/o3/checker.cc
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
dev: Fix ethernet device inheritance structure
The Python wrappers and the C++ should have the same object
structure. If this is not the case, bad things will happen when the
SWIG wrappers cast between an object and any of its base classes. This
was not the case for NSGigE and Sinic devices. This patch makes NSGigE
and Sinic inherit from the new EtherDevBase class, which in turn
inherits from EtherDevice. As a bonus, this removes some duplicated
statistics from the Sinic device.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
sim: Include object header files in SWIG interfaces
When casting objects in the generated SWIG interfaces, SWIG uses
classical C-style casts ( (Foo *)bar; ). In some cases, this can
degenerate into the equivalent of a reinterpret_cast (mainly if only a
forward declaration of the type is available). This usually works for
most compilers, but it is known to break if multiple inheritance is
used anywhere in the object hierarchy.
This patch introduces the cxx_header attribute to Python SimObject
definitions, which should be used to specify a header to include in
the SWIG interface. The header should include the declaration of the
wrapped object. We currently don't enforce header the use of the
header attribute, but a warning will be generated for objects that do
not use it.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
pci: Make Python wrapper cast to the right type
The PCI base class is PciDev and not PciDevice, which is used by the
Python world. Make sure this is reflected in the wrapper code.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
mips: Remove unused Python file
Remove BISystem.py, BareIronMipsSystem is already implemented in
MipsSystem.py.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
dev: Add missing inline declarations
Andreas Sandberg [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
base: Add missing header file to addr_range.hh.
James Clarkson [Tue, 9 Oct 2012 11:58:25 +0000 (12:58 +0100)]
m5: Expose m5 pseudo-instructions to C/C++ via a static library
Updated the util/m5/Makefile.arm so that m5op_arm.S is used to create
a static library - libm5.a. Allowing users to insert m5
psuedo-instructions into their applications for fine-grained
checkpointing, switching cpus or dumping statistics. e.g.
#include <m5op.h>
void foo(){
...
m5_reset_stats(<delay>,<period>)
m5_work_begin(<workid>,<threadid>);
...
m5_work_end(<workid>,<threadid>);
m5_dump_stats(<delay>,<period>);
}
Dam Sunwoo [Fri, 2 Nov 2012 16:32:01 +0000 (11:32 -0500)]
ARM: dump stats and process info on context switches
This patch enables dumping statistics and Linux process information on
context switch boundaries (__switch_to() calls) that are used for
Streamline integration (a graphical statistics viewer from ARM).
Chander Sudanthi [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
base: Fix a few incorrectly handled print format cases
This patch ensures cases like %0.6u, %06f, and %.6u are processed correctly.
The case like %06f is ambiguous and was made to match printf. Also, this patch
removes the goto statement in cprintf.cc in favor of a function call.
Chander Sudanthi [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
base: split out the VncServer into a VncInput and Server classes
This patch adds a VncInput base class which VncServer inherits from.
Another class can implement the same interface and be used instead
of the VncServer, for example a class that replays Vnc traffic.
--HG--
rename : src/base/vnc/VncServer.py => src/base/vnc/Vnc.py
rename : src/base/vnc/vncserver.cc => src/base/vnc/vncinput.cc
rename : src/base/vnc/vncserver.hh => src/base/vnc/vncinput.hh
Dam Sunwoo [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
ISA: generic Linux thread info support
This patch takes the Linux thread info support scattered across
different ISA implementations (currently in ARM, ALPHA, and MIPS), and
unifies them into a single file.
Adds a few more helper functions to read out TGID, mm, etc.
ISA-specific information (e.g., ALPHA PCBB register) is now moved to
the corresponding isa_traits.hh files.
Ali Saidi [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
sim: Fix as issue where exit events on instr queues are used after freed.
Mrinmoy Ghosh [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
o3: Fix a couple of issues with the local predictor.
Fix some issues with the local predictor and the way it's indexed.
Andreas Sandberg [Fri, 2 Nov 2012 16:32:00 +0000 (11:32 -0500)]
Partly revert [
4f54b0f229b5] and move draining to m5.changeToTiming
Changeset
4f54b0f229b5 removed the call to doDrain in changeToTiming
based on the assumption that the system does not need draining when
running in atomic mode. This is a false assumption since at least the
System class requires the system to be drained before it allows
switching of memory modes. This patch reverts that part of the
changeset.
Andreas Hansson [Wed, 31 Oct 2012 13:28:23 +0000 (09:28 -0400)]
mem: Fix typo in port comments
This patch merely fixes a few typos in the port comments.
Andreas Hansson [Wed, 31 Oct 2012 12:39:45 +0000 (08:39 -0400)]
stats: Update stats for fixed simple-atomic-mp config
This patch updates the stats for the regressions that were affected by
the typo in the simple-atomic-mp configuration.
Andreas Hansson [Wed, 31 Oct 2012 12:39:43 +0000 (08:39 -0400)]
config: Fix a typo in the simple-atomic-mp configuration
This patch fixes a minor typo that managed to sneak into the
simple-atomic-mp regression configuration.
Andreas Hansson [Tue, 30 Oct 2012 13:35:32 +0000 (09:35 -0400)]
stats: Update stats for unified cache configuration
This patch updates the stats to reflect the changes in the L2 MSHRs,
as the latter are now uniform across the regressions.
Andreas Hansson [Tue, 30 Oct 2012 11:44:08 +0000 (07:44 -0400)]
config: Unify caches used in regressions and adjust L2 MSHRs
This patch unified the L1 and L2 caches used throughout the
regressions instead of declaring different, but very similar,
configurations in the different scripts.
The patch also changes the default L2 configuration to match what it
used to be for the fs and se scripts (until the last patch that
updated the regressions to also make use of the cache config). The
MSHRs and targets per MSHR are now set to a more realistic default of
20 and 12, respectively.
As a result of both the aforementioned changes, many of the regression
stats are changed. A follow-on patch will bump the stats.
Nilay Vaish [Sat, 27 Oct 2012 21:05:06 +0000 (16:05 -0500)]
regressions: update stats for ruby fs test
Malek Musleh [Sat, 27 Oct 2012 21:04:30 +0000 (16:04 -0500)]
ruby: set the is_icache param for caches
This patch sets the is_icache param for the L1 caches used in
the MESI and the MOESI CMP directory protocols.
Ruby: Use block size in configuring directory bits in address
This patch replaces hard coded values used in Ruby's configuration files
for setting directory bits with values based on the block size in use.
Andreas Hansson [Fri, 26 Oct 2012 10:42:45 +0000 (06:42 -0400)]
config: Add a check for fastmem only used with Atomic CPU
This patch adds an additional check to ensure that the fastmem option
is only used if the system is using the Atomic CPU.
Andreas Hansson [Fri, 26 Oct 2012 10:42:43 +0000 (06:42 -0400)]
config: Remove unused mem_size in fs.py
This patch removes a segment of dead code that is never used.
Andreas Hansson [Fri, 26 Oct 2012 10:42:42 +0000 (06:42 -0400)]
config: Fix the cache class naming in regression scripts
This patch unifies the naming of the default L1 and L2 caches in the
regression configs to be in line with what is used in the se and fs
scripts.
Andreas Hansson [Thu, 25 Oct 2012 17:15:59 +0000 (13:15 -0400)]
stats: Update the stats to reflect the 1GHz default system clock
This patch updates the stats to reflect the change in the default
system clock from 1 THz to 1GHz. The changes are due to the DMA
devices now injecting requests at a lower pace.
Andreas Hansson [Thu, 25 Oct 2012 17:14:44 +0000 (13:14 -0400)]
dev: Make default clock more reasonable for system and devices
This patch changes the default system clock from 1THz to 1GHz. This
clock is used by all modules that do not override the default (parent
clock), and primarily affects the IO subsystem. Every DMA device uses
its clock to schedule the next transfer, and the change will thus
cause this inter-transfer delay to be longer.
The default clock of the bus is removed, as the clock inherited from
the system provides exactly the same value.
A follow-on patch will bump the stats.
Andreas Hansson [Thu, 25 Oct 2012 17:14:42 +0000 (13:14 -0400)]
stats: Update stats to reflect use of SimpleDRAM
This patch bumps the stats to match the use of SimpleDRAM instead of
SimpleMemory in all inorder and O3 regressions, and also all
full-system regressions. A number of performance-related stats change,
and a whole bunch of stats are added for the memory controller.
Andreas Hansson [Thu, 25 Oct 2012 17:14:38 +0000 (13:14 -0400)]
config: Use SimpleDRAM in full-system, and with o3 and inorder
This patch favours using SimpleDRAM with the default timing instead of
SimpleMemory for all regressions that involve the o3 or inorder CPU,
or are full system (in other words, where the actual performance of
the memory is important for the overall performance).
Moving forward, the solution for FSConfig and the users of fs.py and
se.py is probably something similar to what we use to choose the CPU
type. I envision a few pre-set configurations SimpleLPDDR2,
SimpleDDR3, etc that can be choosen by a dram_type option. Feedback on
this part is welcome.
This patch changes plenty stats and adds all the DRAM controller
related stats. A follow-on patch updates the relevant statistics. The
total run-time for the entire regression goes up with ~5% with this
patch due to the added complexity of the SimpleDRAM model. This is a
concious trade-off to ensure that the model is properly tested.
Andreas Hansson [Thu, 25 Oct 2012 08:32:44 +0000 (04:32 -0400)]
config: Use shared cache config for regressions
This patch uses the common L1, L2 and IOCache configuration for the
regressions that all share the same cache parameters. There are a few
regressions that use a slightly different configuration (memtest,
o3-timing=mp, simple-atomic-mp and simple-timing-mp), and the latter
are not changed in this patch. They will be updated in a future patch.
The common cache configurations are changed to match the ones used in
the regressions, and are slightly changed with respect to what they
were. Hopefully this means we can converge on a common base
configuration, used both in the normal user configurations and
regressions.
As only regressions that shared the same cache configuration are
updated, no regressions are affected.
Andreas Hansson [Thu, 25 Oct 2012 08:32:42 +0000 (04:32 -0400)]
arm: Use table walker clock that is inherited from CPU
This patch simplifies the scheduling of the next walk for the ARM
table walker. Previously it used the CPU clock, but as the table
walker inherits the clock from the CPU, it is cleaner to simply use
its own clock (which is the same).
Andreas Hansson [Tue, 23 Oct 2012 08:49:48 +0000 (04:49 -0400)]
stats: Update stats for DMA port send
This patch updates the stats after removing the zero-time send used in
the DMA port.
Andreas Hansson [Tue, 23 Oct 2012 08:49:33 +0000 (04:49 -0400)]
dev: Remove zero-time loop in DMA timing send
This patch removes the zero-time loop used to send items from the DMA
port transmit list. Instead of having a loop, the DMA port now uses an
event to schedule sending of a single packet.
Ultimately this patch serves to ease the transition to a blocking
4-phase handshake.
A follow-on patch will update the regression statistics.
Andreas Hansson [Tue, 23 Oct 2012 08:24:32 +0000 (04:24 -0400)]
stats: Update t1000 stats to match recent changes
This patch brings the t1000 stats up to date.
Nilay Vaish [Thu, 18 Oct 2012 23:35:42 +0000 (18:35 -0500)]
ruby: functional access updates to network test protocol
I had forgotten to change the network test protocol while making changes to
ruby for supporting functional accesses. This patch updates the protocol so
that it can compile correctly.
Nilay Vaish [Tue, 16 Oct 2012 19:47:31 +0000 (14:47 -0500)]
regressions: update stats for eio tests
Nilay Vaish [Tue, 16 Oct 2012 00:13:59 +0000 (19:13 -0500)]
regressions: update stats due to change to ruby memory system
Nilay Vaish [Mon, 15 Oct 2012 22:51:57 +0000 (17:51 -0500)]
ruby: improved support for functional accesses
This patch adds support to different entities in the ruby memory system
for more reliable functional read/write accesses. Only the simple network
has been augmented as of now. Later on Garnet will also support functional
accesses.
The patch adds functional access code to all the different types of messages
that protocols can send around. These messages are functionally accessed
by going through the buffers maintained by the network entities.
The patch also rectifies some of the bugs found in coherence protocols while
testing the patch.
With this patch applied, functional writes always succeed. But functional
reads can still fail.
Nilay Vaish [Mon, 15 Oct 2012 22:27:17 +0000 (17:27 -0500)]
memtest: move check on outstanding requests
The Memtest tester allows for only one request to be outstanding for a
particular physical address. The check has been written separately for
reads and writes. This patch moves the check earlier than its current
position so that it need not be written separately for reads and writes.
Nilay Vaish [Mon, 15 Oct 2012 22:27:17 +0000 (17:27 -0500)]
ruby: register multiple memory controllers
Currently the Ruby System maintains pointer to only one of the memory
controllers. But there can be multiple controllers in the system. This
patch adds a vector of memory controllers.
Nilay Vaish [Mon, 15 Oct 2012 22:27:16 +0000 (17:27 -0500)]
ruby: remove AbstractMemOrCache
The only place where this abstract class is in use is the memory controller,
which it self is an abstract class. Does not seem useful at all.
Nilay Vaish [Mon, 15 Oct 2012 22:27:16 +0000 (17:27 -0500)]
ruby: allow function definition in slicc structs
This patch adds support for function definitions to appear in slicc structs.
This is required for supporting functional accesses for different types of
messages. Subsequent patches will use this to development.
Nilay Vaish [Mon, 15 Oct 2012 22:27:15 +0000 (17:27 -0500)]
ruby banked array: do away with event scheduling
It seems unecessary that the BankedArray class needs to schedule an event
to figure out when the access ends. Instead only the time for the end of access
needs to be tracked.
Nilay Vaish [Mon, 15 Oct 2012 22:27:15 +0000 (17:27 -0500)]
ruby: reset timing after cache warm up
Ruby system was recently converted to a clocked object. Such objects maintain
state related to the time that has passed so far. During the cache warmup, Ruby
system changes its own time and the global time. Later on, the global time is
restored. So Ruby system also needs to reset its own time.
Andreas Hansson [Mon, 15 Oct 2012 16:51:21 +0000 (12:51 -0400)]
Mem: Fix incorrect logic in bus blocksize check
This patch fixes the logic in the blocksize check such that the
warning is printed if the size is not 16, 32, 64 or 128.
Andreas Hansson [Mon, 15 Oct 2012 12:12:35 +0000 (08:12 -0400)]
Port: Add protocol-agnostic ports in the port hierarchy
This patch adds an additional level of ports in the inheritance
hierarchy, separating out the protocol-specific and protocl-agnostic
parts. All the functionality related to the binding of ports is now
confined to use BaseMaster/BaseSlavePorts, and all the
protocol-specific parts stay in the Master/SlavePort. In the future it
will be possible to add other protocol-specific implementations.
The functions used in the binding of ports, i.e. getMaster/SlavePort
now use the base classes, and the index parameter is updated to use
the PortID typedef with the symbolic InvalidPortID as the default.
Andreas Hansson [Mon, 15 Oct 2012 12:12:32 +0000 (08:12 -0400)]
Mem: Separate the host and guest views of memory backing store
This patch moves all the memory backing store operations from the
independent memory controllers to the global physical memory. The main
reason for this patch is to allow address striping in a future set of
patches, but at this point it already provides some useful
functionality in that it is now possible to change the number of
memory controllers and their address mapping in combination with
checkpointing. Thus, the host and guest view of the memory backing
store are now completely separate.
With this patch, the individual memory controllers are far simpler as
all responsibility for serializing/unserializing is moved to the
physical memory. Currently, the functionality is more or less moved
from AbstractMemory to PhysicalMemory without any major
changes. However, in a future patch the physical memory will also
resolve any ranges that are interleaved and properly assign the
backing store to the memory controllers, and keep the host memory as a
single contigous chunk per address range.
Functionality for future extensions which involve CPU virtualization
also enable the host to get pointers to the backing store.
Andreas Hansson [Mon, 15 Oct 2012 12:12:29 +0000 (08:12 -0400)]
Checkpoint: Make system serialize call children
This patch changes how the serialization of the system works. The base
class had a non-virtual serialize and unserialize, that was hidden by
a function with the same name for a number of subclasses (most likely
not intentional as the base class should have been virtual). A few of
the derived systems had no specialization at all (e.g. Power and x86
that simply called the System::serialize), but MIPS and Alpha adds
additional symbol table entries to the checkpoint.
Instead of overriding the virtual function, the additional entries are
now printed through a virtual function (un)serializeSymtab. The reason
for not calling System::serialize from the two related systems is that
a follow up patch will require the system to also serialize the
PhysicalMemory, and if this is done in the base class if ends up being
between the general parts and the specialized symbol table.
With this patch, the checkpoint is not modified, as the order of the
segments is unchanged.
Andreas Hansson [Mon, 15 Oct 2012 12:12:25 +0000 (08:12 -0400)]
Mem: Use deque instead of list for bus retries
This patch changes the data structure used to keep track of ports that
should be told to retry. As the bus is doing this in an FCFS way,
there is no point having a list. A deque is a better match (and is at
least in theory a better choice from a performance point of view).
Andreas Hansson [Mon, 15 Oct 2012 12:12:23 +0000 (08:12 -0400)]
Fix: Address a few minor issues identified by cppcheck
This patch addresses a number of smaller issues identified by the code
inspection utility cppcheck. There are a number of identified leaks in
the arm/linux/system.cc (although the function only get's called once
so it is not a major problem), a few deletes in dev/x86/i8042.cc that
were not array deletes, and sprintfs where the character array had one
element less than needed. In the IIC tags there was a function
allocating an array of longs which is in fact never used.
Andreas Hansson [Mon, 15 Oct 2012 12:12:21 +0000 (08:12 -0400)]
Stats: Update stats for cache timings in cycles
This patch updates the stats to reflect the change in how cache
latencies are expressed. In addition, the latencies are now rounded to
multiples of the clock period, thus also affecting other stats.
Andreas Hansson [Mon, 15 Oct 2012 12:10:54 +0000 (08:10 -0400)]
Mem: Use cycles to express cache-related latencies
This patch changes the cache-related latencies from an absolute time
expressed in Ticks, to a number of cycles that can be scaled with the
clock period of the caches. Ultimately this patch serves to enable
future work that involves dynamic frequency scaling. As an immediate
benefit it also makes it more convenient to specify cache performance
without implicitly assuming a specific CPU core operating frequency.
The stat blocked_cycles that actually counter in ticks is now updated
to count in cycles.
As the timing is now rounded to the clock edges of the cache, there
are some regressions that change. Plenty of them have very minor
changes, whereas some regressions with a short run-time are perturbed
quite significantly. A follow-on patch updates all the statistics for
the regressions.
Andreas Hansson [Mon, 15 Oct 2012 12:10:52 +0000 (08:10 -0400)]
Stats: Update memtest stats after setting clock
This patch updates the memtest stats to reflect the addition of a
clock other than the default one.
Andreas Hansson [Mon, 15 Oct 2012 12:09:57 +0000 (08:09 -0400)]
Configs: Set the memtest clock to a reasonable value
This patch changes the memtest clock from 1THz (the default) to 2GHz,
similar to the CPUs in the other regressions. This is useful as the
caches will adopt the same clock as the CPU. The bus clock rate is
scaled accordingly, and the L1-L2 bus is kept at the CPU clock while
the memory bus is at half that frequency.
A separate patch updates the affected stats.
Andreas Hansson [Mon, 15 Oct 2012 12:09:54 +0000 (08:09 -0400)]
Stats: Update stats for new default L1-to-L2 bus clock and width
This patch updates the stats to reflect the changes in the clock speed
and width for the bus connecting the L1 and L2 caches.
Andreas Hansson [Mon, 15 Oct 2012 12:08:08 +0000 (08:08 -0400)]
Regression: Use CPU clock and 32-byte width for L1-L2 bus
This patch changes the CoherentBus between the L1s and L2 to use the
CPU clock and also four times the width compared to the default
bus. The parameters are not intending to fit every single scenario,
but rather serve as a better startingpoint than what we previously
had.
Note that the scripts that do not use the addTwoLevelCacheHiearchy are
not affected by this change.
A separate patch will update the stats.
Andreas Hansson [Mon, 15 Oct 2012 12:08:06 +0000 (08:08 -0400)]
Stats: Update stats for use of two-level builder
This patch updates the name of the l2 stats.
Andreas Hansson [Mon, 15 Oct 2012 12:07:09 +0000 (08:07 -0400)]
Regression: Use addTwoLevelCacheHierarchy in configs
This patch unifies the full-system regression config scripts and uses
the BaseCPU convenience method addTwoLevelCacheHierarchy to connect up
the L1s and L2, and create the bus inbetween.
The patch is a step on the way to use the clock period to express the
cache latencies, as the CPU is now the parent of the L1, L2 and L1-L2
bus, and these modules thus use the CPU clock.
The patch does not change the value of any stats, but plenty names,
and a follow-up patch contains the update to the stats, chaning
system.l2c to system.cpu.l2cache.
Andreas Hansson [Mon, 15 Oct 2012 12:07:07 +0000 (08:07 -0400)]
Clock: Inherit the clock from parent by default
This patch changes the default 1 Tick clock period to a proxy that
resolves the parents clock. As a result of this, the caches and
L1-to-L2 bus, for example, will automatically use the clock period of
the CPU unless explicitly overridden.
To ensure backwards compatibility, the System class overrides the
proxy and specifies a 1 Tick clock. We could change this to something
more reasonable in a follow-on patch, perhaps 1 GHz or something
similar.
With this patch applied, all clocked objects should have a reasonable
clock period set, and could start specifying delays in Cycles instead
of absolute time.
Andreas Hansson [Mon, 15 Oct 2012 12:07:06 +0000 (08:07 -0400)]
Param: Fix proxy traversal to support chained proxies
This patch modifies how proxies are traversed and unproxied to allow
chained proxies. The issue that is solved manifested itself when a
proxy during its evaluation ended up being hitting another proxy, and
the second one got evaluated using the object that was originally used
for the first proxy.
For a more tangible example, see the following patch on making the
default clock being inherited from the parent. In this patch, the CPU
clock is a proxy Parent.clock, which is overridden in the system to be
an actual value. This all works fine, but the AlphaLinuxSystem has a
boot_cpu_frequency parameter that is Self.cpu[0].clock.frequency. When
the latter is evaluated, it all happens relative to the current object
of the proxy, i.e. the system. Thus the cpu.clock is evaluated as
Parent.clock, but using the system rather than the cpu as the object
to enquire.
Andreas Hansson [Mon, 15 Oct 2012 12:07:04 +0000 (08:07 -0400)]
Mem: Use range operations in bus in preparation for striping
This patch transitions the bus to use the AddrRange operations instead
of directly accessing the start and end. The change facilitates the
move to a more elaborate AddrRange class that also supports address
striping in the bus by specifying interleaving bits in the ranges.
Two new functions are added to the AddrRange to determine if two
ranges intersect, and if one is a subset of another. The bus
propagation of address ranges is also tweaked such that an update is
only propagated if the bus received information from all the
downstream slave modules. This avoids the iteration and need for the
cycle-breaking scheme that was previously used.
Andreas Hansson [Thu, 11 Oct 2012 10:38:43 +0000 (06:38 -0400)]
Mem: Determine bus block size during initialisation
This patch moves the block size computation from findBlockSize to
initialisation time, once all the neighbouring ports are connected.
There is no need to dynamically update the block size, and the caching
of the value effectively avoided that anyhow. This is very similar to
what was already in place, just with a slightly leaner implementation.
Andreas Hansson [Thu, 11 Oct 2012 10:38:42 +0000 (06:38 -0400)]
Doxygen: Update the version of the Doxyfile
This patch bumps the Doxyfile to match more recent versions of
Doxygen. The sections that are deprecated have been removed, and the
new ones added. The project name has also been updated.
Nilay Vaish [Tue, 2 Oct 2012 19:35:46 +0000 (14:35 -0500)]
Regression Tests: Update statistics
Nilay Vaish [Tue, 2 Oct 2012 19:35:45 +0000 (14:35 -0500)]
ruby: makes some members non-static
This patch makes some of the members (profiler, network, memory vector)
of ruby system non-static.
Nilay Vaish [Tue, 2 Oct 2012 19:35:45 +0000 (14:35 -0500)]
ruby: changes to simple network
This patch makes the Switch structure inherit from BasicRouter, as is
done in two other networks.
Nilay Vaish [Tue, 2 Oct 2012 19:35:44 +0000 (14:35 -0500)]
ruby: rename template_hack to template
I don't like using the word hack. Hence, the patch.