libreriscv.git
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lkcl [Wed, 5 Oct 2022 13:43:47 +0000 (14:43 +0100)]

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lkcl [Wed, 5 Oct 2022 11:05:00 +0000 (12:05 +0100)]

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lkcl [Wed, 5 Oct 2022 10:57:10 +0000 (11:57 +0100)]

2 years agoadd int_fp_mv discussion link to ls002
Luke Kenneth Casson Leighton [Wed, 5 Oct 2022 10:56:30 +0000 (11:56 +0100)]
add int_fp_mv discussion link to ls002

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lkcl [Wed, 5 Oct 2022 10:55:09 +0000 (11:55 +0100)]

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lkcl [Wed, 5 Oct 2022 10:02:34 +0000 (11:02 +0100)]

2 years agowhoops rename
Luke Kenneth Casson Leighton [Wed, 5 Oct 2022 10:02:14 +0000 (11:02 +0100)]
whoops rename

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lkcl [Wed, 5 Oct 2022 09:58:04 +0000 (10:58 +0100)]

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lkcl [Tue, 4 Oct 2022 13:21:44 +0000 (14:21 +0100)]

2 years agoclarify notes on fishmv being R-M-W
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 13:14:48 +0000 (14:14 +0100)]
clarify notes on fishmv being R-M-W

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lkcl [Tue, 4 Oct 2022 13:06:47 +0000 (14:06 +0100)]

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lkcl [Tue, 4 Oct 2022 11:44:31 +0000 (12:44 +0100)]

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lkcl [Tue, 4 Oct 2022 11:41:55 +0000 (12:41 +0100)]

2 years agoobservation motivation on ls002, even FPR=0 needs FLD
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 11:29:04 +0000 (12:29 +0100)]
observation motivation on ls002, even FPR=0 needs FLD

2 years agowhitespace
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 11:28:38 +0000 (12:28 +0100)]
whitespace

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lkcl [Tue, 4 Oct 2022 11:24:59 +0000 (12:24 +0100)]

2 years agoadd zero-overhead loop link
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 11:12:36 +0000 (12:12 +0100)]
add zero-overhead loop link

2 years agoadd asm for affine
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 10:29:32 +0000 (11:29 +0100)]
add asm for affine

2 years agoadd gf2p8affineqb bitmatrix-mul to bitmanip page
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 10:28:48 +0000 (11:28 +0100)]
add gf2p8affineqb bitmatrix-mul to bitmanip page

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lkcl [Tue, 4 Oct 2022 05:23:06 +0000 (06:23 +0100)]

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lkcl [Tue, 4 Oct 2022 02:33:21 +0000 (03:33 +0100)]

2 years agoformatting
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 01:55:28 +0000 (02:55 +0100)]
formatting

2 years agowhitespace (linelength)
Luke Kenneth Casson Leighton [Tue, 4 Oct 2022 01:54:38 +0000 (02:54 +0100)]
whitespace (linelength)

2 years agoadd 256-bit packed SIMD emulation table
Jacob Lifshay [Tue, 4 Oct 2022 00:12:21 +0000 (17:12 -0700)]
add 256-bit packed SIMD emulation table

2 years agoadd motivation for SVP64 with VL=1 override
Jacob Lifshay [Tue, 4 Oct 2022 00:05:10 +0000 (17:05 -0700)]
add motivation for SVP64 with VL=1 override

2 years agowork on SVP64 scalar overriding VL to 1 question
Jacob Lifshay [Mon, 3 Oct 2022 23:40:36 +0000 (16:40 -0700)]
work on SVP64 scalar overriding VL to 1 question

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lkcl [Mon, 3 Oct 2022 23:03:08 +0000 (00:03 +0100)]

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lkcl [Mon, 3 Oct 2022 20:36:39 +0000 (21:36 +0100)]

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lkcl [Mon, 3 Oct 2022 20:30:22 +0000 (21:30 +0100)]

2 years agowildcard Makefile for RFCs
Luke Kenneth Casson Leighton [Mon, 3 Oct 2022 20:26:10 +0000 (21:26 +0100)]
wildcard Makefile for RFCs

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lkcl [Mon, 3 Oct 2022 20:25:31 +0000 (21:25 +0100)]

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lkcl [Mon, 3 Oct 2022 10:43:14 +0000 (11:43 +0100)]

2 years agoremove SVSRR0 mention
Luke Kenneth Casson Leighton [Mon, 3 Oct 2022 10:25:54 +0000 (11:25 +0100)]
remove SVSRR0 mention

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lkcl [Mon, 3 Oct 2022 06:36:40 +0000 (07:36 +0100)]

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lkcl [Sat, 1 Oct 2022 16:37:45 +0000 (17:37 +0100)]

2 years agodocs(pinmux): Added a bit on PinGen
Andrey Miroshnikov [Sat, 1 Oct 2022 11:25:42 +0000 (12:25 +0100)]
docs(pinmux): Added a bit on PinGen

2 years agodocs(pinmux): Changed 'bank' to 'port'/'mux', added section on PinSpec class
Andrey Miroshnikov [Sat, 1 Oct 2022 10:17:31 +0000 (11:17 +0100)]
docs(pinmux): Changed 'bank' to 'port'/'mux', added section on PinSpec class

2 years ago(no commit message)
lkcl [Thu, 29 Sep 2022 23:15:13 +0000 (00:15 +0100)]