Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:25:57 +0000 (19:25 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:24:13 +0000 (19:24 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:23:53 +0000 (19:23 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:20:03 +0000 (19:20 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 19:16:56 +0000 (19:16 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:11:01 +0000 (19:11 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 19:07:09 +0000 (19:07 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 19:00:05 +0000 (19:00 +0000)]
[libre-riscv-dev] [Bug 242] OpenPOWER simulation unit tests are needed
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:26:45 +0000 (18:26 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:21:47 +0000 (18:21 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 18:19:54 +0000 (18:19 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 18:02:13 +0000 (18:02 +0000)]
[libre-riscv-dev] [Bug 258] New: Finish implementing support for Power in simple-soft-float
bugzilla-daemon [Sun, 15 Mar 2020 17:34:09 +0000 (17:34 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
Hendrik Boom [Sun, 15 Mar 2020 16:57:23 +0000 (12:57 -0400)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
bugzilla-daemon [Sun, 15 Mar 2020 16:17:04 +0000 (16:17 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 12:11:43 +0000 (12:11 +0000)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 12:09:57 +0000 (12:09 +0000)]
[libre-riscv-dev] pearpc simulator running
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:22:12 +0000 (11:22 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 11:20:16 +0000 (11:20 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 07:59:31 +0000 (00:59 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Immanuel, Yehowshua U [Sun, 15 Mar 2020 07:18:54 +0000 (07:18 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 06:41:37 +0000 (23:41 -0700)]
Re: [libre-riscv-dev] [OT] Minecraft garbage collection
Jacob Lifshay [Sun, 15 Mar 2020 06:13:23 +0000 (23:13 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Hendrik Boom [Sun, 15 Mar 2020 05:47:56 +0000 (01:47 -0400)]
[libre-riscv-dev] [OT] Minecraft garbage collection
Jacob Lifshay [Sun, 15 Mar 2020 05:42:55 +0000 (22:42 -0700)]
Re: [libre-riscv-dev] benefits of rust
Hendrik Boom [Sun, 15 Mar 2020 05:18:21 +0000 (01:18 -0400)]
Re: [libre-riscv-dev] benefits of rust
Hendrik Boom [Sun, 15 Mar 2020 05:10:18 +0000 (01:10 -0400)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Luke Kenneth Casson Leighton [Sun, 15 Mar 2020 04:00:30 +0000 (04:00 +0000)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 03:17:07 +0000 (20:17 -0700)]
Re: [libre-riscv-dev] LibreSOC - RISCV and POWER dual architecture feasibility
Jacob Lifshay [Sun, 15 Mar 2020 02:47:45 +0000 (19:47 -0700)]
[libre-riscv-dev] benefits of rust
whygee [Sat, 14 Mar 2020 18:49:41 +0000 (19:49 +0100)]
Re: [libre-riscv-dev] next tasks
Luke Kenneth Casson Leighton [Sat, 14 Mar 2020 18:28:29 +0000 (18:28 +0000)]
Re: [libre-riscv-dev] next tasks
whygee [Sat, 14 Mar 2020 18:23:08 +0000 (19:23 +0100)]
Re: [libre-riscv-dev] next tasks
Hendrik Boom [Sat, 14 Mar 2020 18:13:51 +0000 (14:13 -0400)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Sat, 14 Mar 2020 14:18:15 +0000 (14:18 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 14:17:34 +0000 (14:17 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 10:31:57 +0000 (10:31 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Sat, 14 Mar 2020 10:30:26 +0000 (10:30 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
whygee [Fri, 13 Mar 2020 21:48:00 +0000 (22:48 +0100)]
Re: [libre-riscv-dev] Chips Alliance started
Cole Poirier [Fri, 13 Mar 2020 21:44:43 +0000 (14:44 -0700)]
Re: [libre-riscv-dev] Chips Alliance started
whygee [Fri, 13 Mar 2020 21:28:54 +0000 (22:28 +0100)]
Re: [libre-riscv-dev] Chips Alliance started
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 20:27:13 +0000 (20:27 +0000)]
[libre-riscv-dev] Chips Alliance started
bugzilla-daemon [Fri, 13 Mar 2020 20:16:34 +0000 (20:16 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
Jacob Lifshay [Fri, 13 Mar 2020 20:10:37 +0000 (13:10 -0700)]
Re: [libre-riscv-dev] changing bugzilla product name
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 19:56:34 +0000 (19:56 +0000)]
Re: [libre-riscv-dev] changing bugzilla product name
Jacob Lifshay [Fri, 13 Mar 2020 18:47:33 +0000 (11:47 -0700)]
[libre-riscv-dev] changing bugzilla product name
bugzilla-daemon [Fri, 13 Mar 2020 18:40:38 +0000 (18:40 +0000)]
[libre-riscv-dev] [Bug 257] New: Implement demo Load/Store queueing algorithm
bugzilla-daemon [Fri, 13 Mar 2020 18:37:01 +0000 (18:37 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 13 Mar 2020 18:29:13 +0000 (18:29 +0000)]
[libre-riscv-dev] [Bug 241] OpenPOWER SImulation is needed of standards
bugzilla-daemon [Fri, 13 Mar 2020 18:29:13 +0000 (18:29 +0000)]
[libre-riscv-dev] [Bug 256] Enhancements to an OpenPOWER ISA-level Simulator are needed
bugzilla-daemon [Fri, 13 Mar 2020 18:26:47 +0000 (18:26 +0000)]
[libre-riscv-dev] [Bug 256] New: Enhancements to an OpenPOWER ISA-level Simulator are needed
bugzilla-daemon [Fri, 13 Mar 2020 18:22:27 +0000 (18:22 +0000)]
[libre-riscv-dev] [Bug 236] Atomics Standard writeup needed
bugzilla-daemon [Fri, 13 Mar 2020 18:19:26 +0000 (18:19 +0000)]
[libre-riscv-dev] [Bug 214] ISAMUX/NS Standard writeup needed
bugzilla-daemon [Fri, 13 Mar 2020 18:12:18 +0000 (18:12 +0000)]
[libre-riscv-dev] [Bug 140] Implement AMDVLK / RADV Mesa Vulkan Driver NLNet 2019-10-042
bugzilla-daemon [Fri, 13 Mar 2020 18:12:18 +0000 (18:12 +0000)]
[libre-riscv-dev] [Bug 247] Implement AMDVLK / RADV Mesa Vulkan Driver
Jacob Lifshay [Fri, 13 Mar 2020 18:10:50 +0000 (11:10 -0700)]
[libre-riscv-dev] Rustup security
Cole Poirier [Fri, 13 Mar 2020 16:24:00 +0000 (09:24 -0700)]
Re: [libre-riscv-dev] [Bug 190] Setup Gitlab CI Runner for Kazan on a computer
Cole Poirier [Fri, 13 Mar 2020 16:21:24 +0000 (09:21 -0700)]
Re: [libre-riscv-dev] [Bug 178] first coriolis2 tutorial, workflow and "test project" page
bugzilla-daemon [Fri, 13 Mar 2020 15:59:33 +0000 (15:59 +0000)]
[libre-riscv-dev] [Bug 255] New: formal standard documentation of 3D Opcodes
bugzilla-daemon [Fri, 13 Mar 2020 15:41:46 +0000 (15:41 +0000)]
[libre-riscv-dev] [Bug 254] New: Second iteration round for opcodes, simulation and hardware for 3D MESA
bugzilla-daemon [Fri, 13 Mar 2020 15:38:14 +0000 (15:38 +0000)]
[libre-riscv-dev] [Bug 253] New: Add hardware implementations of 3D accelerated opcodes
bugzilla-daemon [Fri, 13 Mar 2020 15:36:02 +0000 (15:36 +0000)]
[libre-riscv-dev] [Bug 252] New: 3D accelerated opcodes need to be added to the POWER ISA simulator
bugzilla-daemon [Fri, 13 Mar 2020 15:32:25 +0000 (15:32 +0000)]
[libre-riscv-dev] [Bug 251] New: Initial 3D MESA non-accelerated software-only driver is needed
bugzilla-daemon [Fri, 13 Mar 2020 15:20:36 +0000 (15:20 +0000)]
[libre-riscv-dev] [Bug 250] New: Wishbone B4 Streaming Formal correctness proof needed
bugzilla-daemon [Fri, 13 Mar 2020 15:11:39 +0000 (15:11 +0000)]
[libre-riscv-dev] [Bug 249] New: Additional Wishbone B4 peripherals for Libre-SOC (including conversion from patented AXI4)
bugzilla-daemon [Fri, 13 Mar 2020 15:10:27 +0000 (15:10 +0000)]
[libre-riscv-dev] [Bug 140] Implement AMDVLK / RADV Mesa Vulkan Driver NLNet 2019-10-042
bugzilla-daemon [Fri, 13 Mar 2020 15:10:05 +0000 (15:10 +0000)]
[libre-riscv-dev] [Bug 248] New: Wishbone B4 Streaming presentation at ORConf 2020
bugzilla-daemon [Fri, 13 Mar 2020 15:09:39 +0000 (15:09 +0000)]
[libre-riscv-dev] [Bug 247] New: Implement AMDVLK / RADV Mesa Vulkan Driver
bugzilla-daemon [Fri, 13 Mar 2020 15:07:38 +0000 (15:07 +0000)]
[libre-riscv-dev] [Bug 246] New: Wishbone B4 Streaming I2S peripheral for LibreSOC
bugzilla-daemon [Fri, 13 Mar 2020 15:05:13 +0000 (15:05 +0000)]
[libre-riscv-dev] [Bug 245] New: Wisbone B4 Streaming Reference Implementations with unit tests
bugzilla-daemon [Fri, 13 Mar 2020 15:00:53 +0000 (15:00 +0000)]
[libre-riscv-dev] [Bug 244] New: Wishbone B4 Streaming Specification enhancement.
bugzilla-daemon [Fri, 13 Mar 2020 14:53:17 +0000 (14:53 +0000)]
[libre-riscv-dev] [Bug 175] NLNet 2019 Wishbone proposal 2019-10-043
Immanuel, Yehowshua U [Fri, 13 Mar 2020 14:39:16 +0000 (14:39 +0000)]
Re: [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
bugzilla-daemon [Fri, 13 Mar 2020 13:34:54 +0000 (13:34 +0000)]
[libre-riscv-dev] [Bug 138] NLNet 2019 Coriolis2 Layout proposal 2019-10-029
bugzilla-daemon [Fri, 13 Mar 2020 13:18:44 +0000 (13:18 +0000)]
[libre-riscv-dev] [Bug 243] New: Documentation budget for OpenPower Member discussion and proposals
bugzilla-daemon [Fri, 13 Mar 2020 13:17:31 +0000 (13:17 +0000)]
[libre-riscv-dev] [Bug 242] New: OpenPOWER simulation unit tests are needed
bugzilla-daemon [Fri, 13 Mar 2020 13:07:23 +0000 (13:07 +0000)]
[libre-riscv-dev] [Bug 241] New: OpenPOWER SImulation is needed of standards
bugzilla-daemon [Fri, 13 Mar 2020 12:56:08 +0000 (12:56 +0000)]
[libre-riscv-dev] [Bug 240] New: POWER-RISCV ISA switch formal standard writeup needed
bugzilla-daemon [Fri, 13 Mar 2020 12:54:52 +0000 (12:54 +0000)]
[libre-riscv-dev] [Bug 239] New: FP16 (and FP128) POWER Formal Standard proposal
bugzilla-daemon [Fri, 13 Mar 2020 12:53:39 +0000 (12:53 +0000)]
[libre-riscv-dev] [Bug 238] New: POWER Compressed Formal Standard writeup
bugzilla-daemon [Fri, 13 Mar 2020 12:52:02 +0000 (12:52 +0000)]
[libre-riscv-dev] [Bug 237] New: Variable encoding Standards writeup needed
bugzilla-daemon [Fri, 13 Mar 2020 12:50:07 +0000 (12:50 +0000)]
[libre-riscv-dev] [Bug 236] New: Atomics Standard writeup needed
bugzilla-daemon [Fri, 13 Mar 2020 12:41:05 +0000 (12:41 +0000)]
[libre-riscv-dev] [Bug 174] NLNet 2019 Formal Standards OpenPOWER proposal 2019-10-046
bugzilla-daemon [Fri, 13 Mar 2020 11:50:52 +0000 (11:50 +0000)]
[libre-riscv-dev] [Bug 216] LOAD STORE buffer needed
bugzilla-daemon [Fri, 13 Mar 2020 11:36:57 +0000 (11:36 +0000)]
[libre-riscv-dev] [Bug 217] create a "ring" system which allows pad locations to be specified conveniently
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 10:29:38 +0000 (10:29 +0000)]
Re: [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 10:24:16 +0000 (10:24 +0000)]
Re: [libre-riscv-dev] NLNet Funding Proposals for the Libre RISC-V SoC: call for participation
bugzilla-daemon [Fri, 13 Mar 2020 10:16:31 +0000 (10:16 +0000)]
[libre-riscv-dev] [Bug 137] NLNet 2019 Video Acceleration Proposal 2019-10-031
Luke Kenneth Casson Leighton [Fri, 13 Mar 2020 10:13:06 +0000 (10:13 +0000)]
Re: [libre-riscv-dev] next tasks
bugzilla-daemon [Fri, 13 Mar 2020 10:02:20 +0000 (10:02 +0000)]
[libre-riscv-dev] [Bug 235] New: Video opcode FPGA tests
bugzilla-daemon [Fri, 13 Mar 2020 10:01:56 +0000 (10:01 +0000)]
[libre-riscv-dev] [Bug 234] New: Hardware implementation of video opcodes
bugzilla-daemon [Fri, 13 Mar 2020 10:01:28 +0000 (10:01 +0000)]
[libre-riscv-dev] [Bug 233] New: Video unit tests in simulator
bugzilla-daemon [Fri, 13 Mar 2020 10:00:52 +0000 (10:00 +0000)]
[libre-riscv-dev] [Bug 232] New: Implementation of video opcodes in simulator
bugzilla-daemon [Fri, 13 Mar 2020 10:00:22 +0000 (10:00 +0000)]
[libre-riscv-dev] [Bug 231] New: Video Opcodes Standards writeup
bugzilla-daemon [Fri, 13 Mar 2020 09:59:54 +0000 (09:59 +0000)]
[libre-riscv-dev] [Bug 230] New: Video opcode development and discussion
bugzilla-daemon [Fri, 13 Mar 2020 09:59:06 +0000 (09:59 +0000)]
[libre-riscv-dev] [Bug 229] New: AV1 optimizations
bugzilla-daemon [Fri, 13 Mar 2020 09:58:41 +0000 (09:58 +0000)]
[libre-riscv-dev] [Bug 228] New: VP9 optimizations
bugzilla-daemon [Fri, 13 Mar 2020 09:58:12 +0000 (09:58 +0000)]
[libre-riscv-dev] [Bug 227] New: VP8 optimizations
bugzilla-daemon [Fri, 13 Mar 2020 09:57:50 +0000 (09:57 +0000)]
[libre-riscv-dev] [Bug 226] New: H.265 optimizations
bugzilla-daemon [Fri, 13 Mar 2020 09:57:22 +0000 (09:57 +0000)]
[libre-riscv-dev] [Bug 225] New: H.264 optimizations
projects / libre-riscv-dev.git / log