Marcelina Kościelnicka [Thu, 22 Oct 2020 08:37:44 +0000 (10:37 +0200)]
memory_dff: Fix needlessly duplicating enable bits.
When the register being merged into the EN signal happens to be a $sdff,
the current code creates a new $mux for every bit, even if they happen
to be identical (as is usually the case), preventing proper grouping
further down the flow. Fix this by adding a simple cache.
Fixes #2409.
Yosys Bot [Thu, 22 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Marcelina Kościelnicka [Sun, 18 Oct 2020 01:28:36 +0000 (03:28 +0200)]
btor: Use Mem helper.
Marcelina Kościelnicka [Sun, 18 Oct 2020 01:09:45 +0000 (03:09 +0200)]
smt2: Use Mem helper.
Marcelina Kościelnicka [Sat, 17 Oct 2020 19:48:38 +0000 (21:48 +0200)]
verilog_backend: Use Mem helper.
Marcelina Kościelnicka [Sat, 17 Oct 2020 13:49:36 +0000 (15:49 +0200)]
sim: Use Mem helper.
Marcelina Kościelnicka [Fri, 16 Oct 2020 23:39:22 +0000 (01:39 +0200)]
clk2fflogic: Use Mem helper.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:21:05 +0000 (22:21 +0200)]
opt_mem: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:55 +0000 (22:20 +0200)]
memory_bram: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:32 +0000 (22:20 +0200)]
memory_map: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:47 +0000 (22:20 +0200)]
memory_unpack: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:24 +0000 (22:20 +0200)]
memory_collect: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:20:16 +0000 (22:20 +0200)]
memory_nordff: Use Mem helpers.
Marcelina Kościelnicka [Sat, 17 Oct 2020 20:19:34 +0000 (22:19 +0200)]
Add new helper structures to represent memories.
Yosys Bot [Wed, 21 Oct 2020 00:10:07 +0000 (00:10 +0000)]
Bump version
clairexen [Tue, 20 Oct 2020 15:11:36 +0000 (17:11 +0200)]
Merge pull request #2405 from byuccl/fix_xilinx_cells
xilinx/cells_sim.v: Move signal declaration to before first use
clairexen [Tue, 20 Oct 2020 09:32:35 +0000 (11:32 +0200)]
Merge pull request #2404 from YosysHQ/claire/fixrpcargs
Fix argument handling in connect_rpc
Yosys Bot [Tue, 20 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Jeff Goeders [Mon, 19 Oct 2020 22:09:04 +0000 (16:09 -0600)]
Move signal declarations to before first use
Signed-off-by: Jeff Goeders <jeff.goeders@gmail.com>
Claire Xenia Wolf [Mon, 19 Oct 2020 11:40:57 +0000 (13:40 +0200)]
Fix argument handling in connect_rpc
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
Miodrag Milanović [Mon, 19 Oct 2020 09:20:56 +0000 (11:20 +0200)]
Merge pull request #2397 from daveshah1/nexus
synth_nexus: Initial implementation
Yosys Bot [Fri, 16 Oct 2020 00:10:07 +0000 (00:10 +0000)]
Bump version
clairexen [Thu, 15 Oct 2020 16:08:59 +0000 (18:08 +0200)]
Merge pull request #2398 from jakobwenzel/smtbmc-escape
smtbmc: escape identifiers in verilog testbench
David Shah [Thu, 1 Oct 2020 10:15:54 +0000 (11:15 +0100)]
synth_nexus: Initial implementation
Signed-off-by: David Shah <dave@ds0.me>
Yosys Bot [Tue, 13 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Miodrag Milanovic [Mon, 12 Oct 2020 12:56:15 +0000 (14:56 +0200)]
extend verific library API for formal apps and generators
Yosys Bot [Fri, 9 Oct 2020 00:10:05 +0000 (00:10 +0000)]
Bump version
Marcelina Kościelnicka [Thu, 8 Oct 2020 11:33:47 +0000 (13:33 +0200)]
opt_clean: Better memory handling.
Previously, `$memwr` and `$meminit` cells were always preserved (along
with the memory itself). With this change, they are instead part of the
main cell mark-and-sweep pass: a memory (and its `$meminit` and `$memwr`
cells) is only preserved iff any associated `$memrd` cell needs to be
preserved.
Jakob Wenzel [Tue, 6 Oct 2020 09:24:29 +0000 (11:24 +0200)]
smtbmc: escape identifiers in verilog testbench
Yosys Bot [Tue, 6 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Miodrag Milanović [Mon, 5 Oct 2020 11:27:27 +0000 (13:27 +0200)]
Update required Verific version
Yosys Bot [Sat, 3 Oct 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
clairexen [Fri, 2 Oct 2020 08:16:23 +0000 (10:16 +0200)]
Merge pull request #2396 from YosysHQ/claire/empty-param
Ignore empty parameters in Verilog module instantiations
Yosys Bot [Fri, 2 Oct 2020 00:10:05 +0000 (00:10 +0000)]
Bump version
Claire Xenia Wolf [Thu, 1 Oct 2020 16:26:53 +0000 (18:26 +0200)]
Ignore empty parameters in Verilog module instantiations
Fixes #2394
Signed-off-by: Claire Xenia Wolf <claire@symbioticeda.com>
clairexen [Thu, 1 Oct 2020 16:17:36 +0000 (18:17 +0200)]
Merge pull request #2378 from udif/pr_dollar_high_low
Added $high(), $low(), $left(), $right()
clairexen [Thu, 1 Oct 2020 16:12:31 +0000 (18:12 +0200)]
Merge pull request #2380 from Xiretza/parallel-tests
Clean up and parallelize testsuite
David Shah [Thu, 1 Oct 2020 14:53:14 +0000 (15:53 +0100)]
Update .gitignore
Signed-off-by: David Shah <dave@ds0.me>
clairexen [Thu, 1 Oct 2020 12:32:43 +0000 (14:32 +0200)]
Merge pull request #2395 from YosysHQ/sha1_if_contain_spaces
Use sha1 for parameter list in case if they contain spaces
Yosys Bot [Thu, 1 Oct 2020 00:10:08 +0000 (00:10 +0000)]
Bump version
Miodrag Milanovic [Wed, 30 Sep 2020 07:16:59 +0000 (09:16 +0200)]
use sha1 for parameter list in case if they contain spaces
Miodrag Milanovic [Wed, 30 Sep 2020 05:47:36 +0000 (07:47 +0200)]
Fixed installation dir override for Python scripts
Yosys Bot [Wed, 30 Sep 2020 00:10:09 +0000 (00:10 +0000)]
Bump version
clairexen [Tue, 29 Sep 2020 15:31:01 +0000 (17:31 +0200)]
Merge pull request #2393 from nakengelhardt/no_const_sensitivity
write_verilog: emit intermediate wire for constant values in sensitivity list
clairexen [Tue, 29 Sep 2020 15:21:08 +0000 (17:21 +0200)]
Merge pull request #2392 from YosysHQ/mmicko/hierarchy_fix
Validate parameters only when they are used
Yosys Bot [Tue, 29 Sep 2020 00:10:05 +0000 (00:10 +0000)]
Bump version
N. Engelhardt [Mon, 28 Sep 2020 16:12:40 +0000 (18:12 +0200)]
add tests
N. Engelhardt [Mon, 28 Sep 2020 16:11:18 +0000 (18:11 +0200)]
write_verilog: emit intermediate wire for constant values in sensitivity list
Miodrag Milanović [Mon, 28 Sep 2020 10:54:38 +0000 (12:54 +0200)]
Merge pull request #2386 from btut/fix/pyinstallpath
Fixed python installation path
N. Engelhardt [Mon, 28 Sep 2020 10:45:52 +0000 (12:45 +0200)]
Merge pull request #2387 from btut/fix/pythonWrappersCXXFlags
Use CXXFLAGS to enable pyosys specific code before generating wrappers
Xiretza [Sat, 26 Sep 2020 14:27:37 +0000 (16:27 +0200)]
tests: add gitignores for auto-generated makefiles
Benedikt Tutzer [Fri, 25 Sep 2020 10:57:46 +0000 (12:57 +0200)]
Use CXXFLAGS to enable pyosys specific code before generating wrappers
The .pyh files were generated without the CXXFLAGS. This meant that code
marked by the WITH_PYTHON flag was excluded. This is fixed by adding the
flag in the rule for .pyh files.
Miodrag Milanovic [Fri, 25 Sep 2020 09:40:37 +0000 (11:40 +0200)]
Validate parameters only when they are used
Benedikt Tutzer [Fri, 25 Sep 2020 09:21:16 +0000 (11:21 +0200)]
Fixed python installation path
The path where python expects it's libraries seems to change from
operating system to operating system, but can be querried from the site
package.
Yosys Bot [Thu, 24 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Eddie Hung [Wed, 23 Sep 2020 16:15:24 +0000 (09:15 -0700)]
xilinx: do not make DSP48E1 a whitebox for ABC9 by default (#2325)
* xilinx: eliminate SCCs from DSP48E1 model
* xilinx: add SCC test for DSP48E1
* Update techlibs/xilinx/cells_sim.v
* xilinx: Gate DSP48E1 being a whitebox behind ALLOW_WHITEBOX_DSP48E1
Have a test that checks it works through ABC9 when enabled
Miodrag Milanović [Wed, 23 Sep 2020 11:04:54 +0000 (13:04 +0200)]
Merge pull request #2384 from nakengelhardt/fix_2383
switch argument order to work with macOS getopt
N. Engelhardt [Wed, 23 Sep 2020 10:48:26 +0000 (12:48 +0200)]
switch argument order to work with macOS getopt
Yosys Bot [Tue, 22 Sep 2020 00:10:15 +0000 (00:10 +0000)]
Bump version
N. Engelhardt [Mon, 21 Sep 2020 13:18:06 +0000 (15:18 +0200)]
Merge pull request #2372 from nakengelhardt/name_is_public
add IdString::isPublic()
Xiretza [Mon, 21 Sep 2020 13:05:42 +0000 (15:05 +0200)]
tests/simple: remove "nullglob" shopt
Xiretza [Wed, 16 Sep 2020 17:58:16 +0000 (19:58 +0200)]
tests: Parallelize
Xiretza [Wed, 16 Sep 2020 15:59:37 +0000 (17:59 +0200)]
tests: Centralize test collection and Makefile generation
Yosys Bot [Sat, 19 Sep 2020 00:10:08 +0000 (00:10 +0000)]
Bump version
clairexen [Fri, 18 Sep 2020 15:43:30 +0000 (17:43 +0200)]
Merge pull request #2381 from YosysHQ/unsupported
Better error for unsupported SVA sequence
Miodrag Milanovic [Fri, 18 Sep 2020 15:08:00 +0000 (17:08 +0200)]
Better error for unsupported SVA sequence
Yosys Bot [Fri, 18 Sep 2020 00:10:08 +0000 (00:10 +0000)]
Bump version
clairexen [Thu, 17 Sep 2020 16:27:05 +0000 (18:27 +0200)]
Merge pull request #2329 from antmicro/arrays-fix-multirange-size
Rewrite multirange arrays sizes [n] as [n-1:0]
clairexen [Thu, 17 Sep 2020 16:21:53 +0000 (18:21 +0200)]
Merge pull request #2330 from antmicro/arrays-fix-multirange-access
Fix unsupported subarray access detection
Udi Finkelstein [Wed, 16 Sep 2020 21:55:17 +0000 (00:55 +0300)]
We can now handle array slices (e.g. $size(x[1]) etc. )
Udi Finkelstein [Wed, 16 Sep 2020 07:57:06 +0000 (10:57 +0300)]
Fixed comments, removed debug message
Udi Finkelstein [Tue, 15 Sep 2020 17:49:52 +0000 (20:49 +0300)]
Added $high(), $low(), $left(), $right()
N. Engelhardt [Mon, 14 Sep 2020 10:43:18 +0000 (12:43 +0200)]
use the new isPublic() in a few places
Yosys Bot [Fri, 11 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Miodrag Milanović [Thu, 10 Sep 2020 11:37:49 +0000 (13:37 +0200)]
Merge pull request #2369 from Xiretza/gitignores
Add missing gitignores for test artifacts
Yosys Bot [Fri, 4 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
N. Engelhardt [Thu, 3 Sep 2020 15:37:58 +0000 (17:37 +0200)]
add IdString::isPublic()
whitequark [Thu, 3 Sep 2020 09:45:40 +0000 (09:45 +0000)]
Merge pull request #2371 from whitequark/cxxrtl-debug-info
cxxrtl: expose port direction and driver kind in debug information
Yosys Bot [Thu, 3 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
whitequark [Wed, 2 Sep 2020 17:16:10 +0000 (17:16 +0000)]
cxxrtl: expose driver kind in debug information.
This can be useful to determine whether the wire should be a part of
a design checkpoint, whether it can be used to override design state,
and whether driving it may cause a conflict.
whitequark [Wed, 2 Sep 2020 16:03:35 +0000 (16:03 +0000)]
cxxrtl: improve handling of FFs with async inputs (other than CLK).
Before this commit, the meaning of "sync def" included some flip-flop
cells but not others. There was no actual reason for this; it was
just poorly defined.
After this commit, a "sync def" means that a wire holds design state
because it is connected directly to a flip-flop output, and may never
be unbuffered. This is not affected by presence of async inputs.
whitequark [Wed, 2 Sep 2020 15:18:44 +0000 (15:18 +0000)]
cxxrtl: expose port direction in debug information.
This can be useful to distinguish e.g. a combinatorially driven wire
with type `CXXRTL_VALUE` from a module input with the same type, as
well as general introspection.
whitequark [Wed, 2 Sep 2020 15:23:40 +0000 (15:23 +0000)]
cxxrtl: fix typo in comment. NFC.
whitequark [Wed, 2 Sep 2020 15:11:55 +0000 (15:11 +0000)]
cxxrtl: fix inaccuracy in CXXRTL_ALIAS documentation. NFC.
Nodes driven by a constant value have type CXXRTL_VALUE and their
`next` pointer set to NULL. (This is already documented.)
Miodrag Milanovic [Wed, 2 Sep 2020 08:22:25 +0000 (10:22 +0200)]
Use latest verific
Yosys Bot [Wed, 2 Sep 2020 00:10:07 +0000 (00:10 +0000)]
Bump version
clairexen [Tue, 1 Sep 2020 15:31:48 +0000 (17:31 +0200)]
Merge pull request #2352 from zachjs/const-func-localparam
Allow localparams in constant functions
clairexen [Tue, 1 Sep 2020 15:30:36 +0000 (17:30 +0200)]
Merge pull request #2366 from zachjs/library-format
Simple support for %l format specifier
clairexen [Tue, 1 Sep 2020 15:30:09 +0000 (17:30 +0200)]
Merge pull request #2353 from zachjs/top-scope
Module name scope support
clairexen [Tue, 1 Sep 2020 15:28:35 +0000 (17:28 +0200)]
Merge pull request #2365 from zachjs/const-arg-loop-split-type
Fix constant args used with function ports split across declarations
Yosys Bot [Tue, 1 Sep 2020 00:10:06 +0000 (00:10 +0000)]
Bump version
Xiretza [Mon, 31 Aug 2020 17:42:10 +0000 (19:42 +0200)]
Add missing gitignores for test artifacts
Miodrag Milanovic [Mon, 31 Aug 2020 10:22:26 +0000 (12:22 +0200)]
Reorder to prevent crash
clairexen [Mon, 31 Aug 2020 09:58:29 +0000 (11:58 +0200)]
Merge pull request #2368 from YosysHQ/verific_portrange
Fix import of VHDL enums
Miodrag Milanovic [Sun, 30 Aug 2020 11:33:03 +0000 (13:33 +0200)]
ast recognize lower case x and z and verific gives upper case
Miodrag Milanovic [Sun, 30 Aug 2020 11:15:06 +0000 (13:15 +0200)]
Do not check for 1 and 0 only
Miodrag Milanovic [Sun, 30 Aug 2020 10:25:23 +0000 (12:25 +0200)]
Fix import of VHDL enums
Yosys Bot [Sun, 30 Aug 2020 00:10:07 +0000 (00:10 +0000)]
Bump version
whitequark [Sat, 29 Aug 2020 20:02:35 +0000 (20:02 +0000)]
write_smt2: fix SMT-LIB tutorial URL
Zachary Snow [Sat, 29 Aug 2020 17:33:31 +0000 (13:33 -0400)]
Simple support for %l format specifier
Yosys doesn't support libraries, so this provides the same behavior as
%m, as some other tools have opted to do.