Nilay Vaish [Mon, 29 Aug 2011 11:34:40 +0000 (06:34 -0500)]
SLICC: Pass arguments by reference
Arguments to functions were being passed by value. This patch
changes SLICC so that arguments are passed by reference.
Nilay Vaish [Mon, 29 Aug 2011 10:10:23 +0000 (05:10 -0500)]
Ruby: Remove some unused code
Nilay Vaish [Fri, 26 Aug 2011 17:27:58 +0000 (12:27 -0500)]
Ruby: Eliminate modulo op for computing set size.
Ali Saidi [Fri, 19 Aug 2011 20:08:09 +0000 (15:08 -0500)]
ARM: Add some MP regressions and clean up the disk images and kernels a bit
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Mark some variables uncacheable until boot all CPUs are enabled.
There are a set of locations is the linux kernel that are managed via
cache maintence instructions until all processors enable their MMUs & TLBs.
Writes to these locations are manually flushed from the cache to main
memory when the occur so that cores operating without their MMU enabled
and only issuing uncached accesses can receive the correct data. Unfortuantely,
gem5 doesn't support any kind of software directed maintence of the cache.
Until such time as that support exists this patch marks the specific cache blocks
that need to be coherent as non-cacheable until all CPUs enable their MMU and
thus allows gem5 to boot MP systems with caches enabled (a requirement for
booting an O3 cpu and thus an O3 CPU regression).
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
Mem: Put prefetcher notify call before packet is deleted.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Add VExpress_E support with PCIe to gem5
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Add support for Versatile Express boards
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
ARM: Make GIC function that should only be called by GIC protected.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
IDE: Fix issues with new PIIX kernel driver and our model.
The driver can read the IDE config register as a 32 bit register since
some adapters use bit 18 as a disable channel bit. If the size isn't
set in a PRD it should be 64K according to the SPEC (and driver) not
128K.
Ali Saidi [Fri, 19 Aug 2011 20:08:08 +0000 (15:08 -0500)]
StoreSet: Update stats for store-set clearing
Ali Saidi [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
ARM: Add support for DIV/SDIV instructions.
Ali Saidi [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
LSQ: Set store predictor to periodically clear itself as recommended in the storesets paper.
This patch improves performance by as much as 10% on some spec benchmarks.
Geoffrey Blake [Fri, 19 Aug 2011 20:08:07 +0000 (15:08 -0500)]
Fix bugs due to interaction between SEV instructions and O3 pipeline
SEV instructions were originally implemented to cause asynchronous squashes
via the generateTCSquash() function in the O3 pipeline when updating the
SEV_MAILBOX miscReg. This caused race conditions between CPUs in an MP system
that would lead to a pipeline either going inactive indefinitely or not being
able to commit squashed instructions. Fixed SEV instructions to behave like
interrupts and cause synchronous sqaushes inside the pipeline, eliminating
the race conditions. Also fixed up the semantics of the WFE instruction to
behave as documented in the ARMv7 ISA description to not sleep if SEV_MAILBOX=1
or unmasked interrupts are pending.
Ali Saidi [Fri, 19 Aug 2011 20:08:06 +0000 (15:08 -0500)]
O3: Update stats for LSQ changes.
Mrinmoy Ghosh [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
LSQ: Add some better dprintfs for storeset predictor.
Mrinmoy Ghosh [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
LSQ: Fix a few issues with the storeset predictor.
Two issues are fixed in this patch:
1. The load and store pc passed to the predictor are passed in reverse order.
2. The flag indicating that a barrier is inflight was never cleared when
the barrier was squashed instead of committed. This made all load insts
dependent on a non-existent barrier in-flight.
Thomas Grass [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
Stats: Add a sparse histogram stat object.
Giacomo Gabrielli [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
O3: Squash the violator and younger instructions instead not all insts.
Change the way instructions are squashed on memory ordering violations
to squash the violator and younger instructions, not all instructions
that are younger than the instruction they violated (no reason to throw
away valid work).
Geoffrey Blake [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Add per-cpu local timers for ARM.
Cortex-A9 processors can have a local timer and watchdog counter. It
is enabled by default in Linux and up to this point we've had to disable
them since a model wasn't available. This change allows a default
MP ARM Linux configuration to boot.
Prakash Ramrakhani [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Add per-processor interrupt support to GIC.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: Fix a memory leak with the table walker.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
Prefetcher: Fix some memory leaks with the prefetcher.
Ali Saidi [Fri, 19 Aug 2011 20:08:05 +0000 (15:08 -0500)]
ARM: quiet what can be a very noise CLCD controller.
Gabe Black [Tue, 16 Aug 2011 09:47:15 +0000 (02:47 -0700)]
InOrder: Make cache_unit.hh include hashmap.hh explicitly, not transitively.
Gabe Black [Tue, 16 Aug 2011 09:46:57 +0000 (02:46 -0700)]
O3: Make lsq_unit.hh include arch/isa_traits.hh directly, not transitively.
Nilay Vaish [Mon, 15 Aug 2011 17:56:47 +0000 (12:56 -0500)]
Ruby: Initialize some variables.
Gabe Black [Mon, 15 Aug 2011 01:34:17 +0000 (18:34 -0700)]
X86: Add an X86_FS o3 regression.
Gabe Black [Mon, 15 Aug 2011 00:41:34 +0000 (17:41 -0700)]
O3: When squashing, restore the macroop that should be used for fetching.
Gabe Black [Sun, 14 Aug 2011 11:08:14 +0000 (04:08 -0700)]
O3: Add a pointer to the macroop for a microop in the dyninst.
Gabe Black [Sun, 14 Aug 2011 06:03:21 +0000 (23:03 -0700)]
Stats: Small update to stats for change to x86 inst flags.
Gabe Black [Sun, 14 Aug 2011 06:03:11 +0000 (23:03 -0700)]
X86: Use IsSquashAfter if an instruction could affect fetch translation.
Control register operands are set up so that writing to them is serialize
after, serialize before, and non-speculative. These are probably overboard,
but they should usually be safe. Unfortunately there are times when even these
aren't enough. If an instruction modifies state that affects fetch, later
serialized instructions which come after it might have already gone through
fetch and decode by the time it commits. These instructions may have been
translated incorrectly or interpretted incorrectly and need to be destroyed.
This change modifies instructions which will or may have this behavior so that
they use the IsSquashAfter flag when necessary.
Gabe Black [Sat, 13 Aug 2011 20:36:37 +0000 (13:36 -0700)]
O3: At the end of an instruction, force fetchAddr to something sensible.
It's possible (though until now very unlikely) for fetchAddr to get out of
sync with the actual PC of the current instruction. This change forcefull
resets fetchAddr at the end of every instruction.
Gabe Black [Tue, 9 Aug 2011 18:33:12 +0000 (11:33 -0700)]
SCons,tests: Tell scons about pc-o3-timing regressions.
Gabe Black [Tue, 9 Aug 2011 18:32:30 +0000 (11:32 -0700)]
X86: Build O3 by default in X86_FS.
Gabe Black [Tue, 9 Aug 2011 18:31:48 +0000 (11:31 -0700)]
Stats: Update stats for the end of macroop O3 fix.
Gabe Black [Tue, 9 Aug 2011 18:30:43 +0000 (11:30 -0700)]
O3: Stop using the current macroop no matter why you're leaving it.
Until now, the only reason a macroop would be left was because it ended at a
microop marked as the last microop. In O3 with branch prediction, it's
possible for the branch predictor to have entries which originally came from
different instructions which happened to have the same RIP. This could
theoretically happen in many ways, but it was encountered specifically when
different programs in different address spaces ran one after the other in
X86_FS.
What would happen in that case was that the macroop would continue to be
looped over and microops fetched from it until it reached the last microop
even though the macropc had moved out from under it. If things lined up
properly, this could mean that the end bytes of an instruction actually fell
into the instruction sized block of memory after the one in the predecoder.
The fetch loop implicitly assumes that the last instruction sized chunk of
memory processed was the last one needed for the instruction it just finished
executing. It would then tell the predecoder to move to an offset within the
bytes it was given that is larger than those bytes, and that would trip an
assert in the x86 predecoder.
This change fixes this problem by making fetch stop processing the current
macroop if the address it should be fetching from changed when the PC is
updated. That happens when the last microop was reached because the instruction
handled it properly, and it also catches the case where the branch predictor
makes fetch do a macro level branch when it shouldn't.
The check of isLastMicroop is retained because otherwise, a macroop that
branches back to itself would act like a single, long macroop instead of
multiple instances of the same microop. There may be situations (which may
turn out to be purely hypothetical) where that matters.
This also fixes a relatively minor issue where the curMacroop variable would
be set to NULL immediately after seeing that a microop was the last one before
curMacroop was used to build the dyninst. The traceData structure would have a
NULL pointer to the macroop for that microop.
Gabe Black [Tue, 9 Aug 2011 10:37:45 +0000 (03:37 -0700)]
Stats: Update stats for the recent O3 interrupt change.
Gabe Black [Tue, 9 Aug 2011 10:37:43 +0000 (03:37 -0700)]
O3: When waiting to handle an interrupt, let everything drain out.
Before this change, the commit stage would wait until the ROB and store queue
were empty before recognizing an interrupt. The fetch stage would stop
generating instructions at an appropriate point, so commit would then wait
until a valid time to interrupt the instruction stream. Instructions might be
in flight after fetch but not the in the ROB or store queue (in rename, for
instance), so this change makes commit wait until all in flight instructions
are finished.
Nilay Vaish [Mon, 8 Aug 2011 15:50:13 +0000 (10:50 -0500)]
BuildEnv: Eliminate RUBY as build environment variable
This patch replaces RUBY with PROTOCOL in all the SConscript files as
the environment variable that decides whether or not certain components
of the simulator are compiled.
Gabe Black [Sun, 7 Aug 2011 22:41:10 +0000 (15:41 -0700)]
O3: Get rid of the unused addToRemoveList function.
Gabe Black [Sun, 7 Aug 2011 22:41:09 +0000 (15:41 -0700)]
Stats: Update stats for the previous change.
Gabe Black [Sun, 7 Aug 2011 22:41:07 +0000 (15:41 -0700)]
O3: Let squashed and deferred instructions issue.
Let squahsed and deferred instructions issue so they don't accumulate and clog
up the CPU.
Gabe Black [Sun, 7 Aug 2011 16:22:18 +0000 (09:22 -0700)]
Stats: Update the stats after the uninitialized branch predictor variable fix.
Ali Saidi [Sun, 7 Aug 2011 16:21:49 +0000 (09:21 -0700)]
O3: Fix uninitialized variable in the tournament branch predictor.
Gabe Black [Sun, 7 Aug 2011 16:21:48 +0000 (09:21 -0700)]
Translation: Use a pointer type as the template argument.
This allows regular pointers and reference counted pointers without having to
use any shim structures or other tricks.
Nilay Vaish [Wed, 3 Aug 2011 23:25:30 +0000 (18:25 -0500)]
Ruby: Remove files and includes not in use
Gabe Black [Tue, 2 Aug 2011 18:51:16 +0000 (11:51 -0700)]
O3: Get rid of the raw ExtMachInst constructor on DynInsts.
This constructor assumes that the ExtMachInst can be decoded directly into a
StaticInst that's useful to execute. With the advent of microcoded
instructions that's no longer true.
Gabe Black [Tue, 2 Aug 2011 10:22:11 +0000 (03:22 -0700)]
Scons: Make some Action objects fit the abreviated output format.
Nilay Vaish [Tue, 2 Aug 2011 05:10:08 +0000 (00:10 -0500)]
Scons: Drop RUBY as compile time option.
This patch drops RUBY as a compile time option. Instead the PROTOCOL option
is used to figure out whether or not to build Ruby. If the specified protocol
is 'None', then Ruby is not compiled.
Gabe Black [Mon, 1 Aug 2011 02:21:17 +0000 (19:21 -0700)]
O3: Implement memory mapped IPRs for O3.
Gabe Black [Sun, 31 Jul 2011 06:23:01 +0000 (23:23 -0700)]
Stats: Update stats for the recent fix to fetch.
Gabe Black [Sun, 31 Jul 2011 06:22:53 +0000 (23:22 -0700)]
O3: Fix corner case squashing into the microcode ROM.
When fetching from the microcode ROM, if the PC is set so that it isn't in the
cache block that's been fetched the CPU will get stuck. The fetch stage
notices that it's in the ROM so it doesn't try to fetch from the current PC.
It then later notices that it's outside of the current cache block so it skips
generating instructions expecting to continue once the right bytes have been
fetched. This change lets the fetch stage attempt to generate instructions,
and only checks if the bytes it's going to use are valid if it's really going
to use them.
Nilay Vaish [Thu, 28 Jul 2011 01:20:53 +0000 (20:20 -0500)]
SLICC: Put functions of a controller in its .cc file
Currently, functions associated with a controller go into separate files.
This patch puts all the functions in the controller's .cc file. This should
hopefully take away some time from compilation.
Nilay Vaish [Tue, 26 Jul 2011 17:20:22 +0000 (12:20 -0500)]
Ruby: Fix instantiations of DMA controller and sequencer
The patch on Ruby functional accesses made changes to the process of
instantiating controllers and sequencers. The DMA controller and
sequencer was not updated, hence this patch.
Nilay Vaish [Mon, 25 Jul 2011 23:31:30 +0000 (18:31 -0500)]
Merged with Gabe's changeset.
Nilay Vaish [Mon, 25 Jul 2011 23:18:31 +0000 (18:18 -0500)]
Ruby: Fix dma controller configs/ruby/MI_example.py
The dma controller in configs/ruby/MI_example.py was not being set correctly.
This patch fixes it.
Gabe Black [Tue, 19 Jul 2011 09:56:02 +0000 (02:56 -0700)]
SCons: Only print all the SConsopts being read if verbose is turned on.
Korey Sewell [Sat, 16 Jul 2011 01:26:18 +0000 (21:26 -0400)]
inorder-fs: temp. regression removal
remove this regression till the fix for the hwrei instruction is put in
Ali Saidi [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
Mem: Fix issue with prefetches originating at non-L1 caches getting stale data
Prefetch requests issued from the L2 or below wouldn't check if valid data is
present higher in the system. If a prefetch into the L2 occured at the same
time as writeback from a higher-level cache the dirty data could be replaced
in by unmodified data in memory.
Giacomo Gabrielli [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
O3: Create a pipeline activity viewer for the O3 CPU model.
Implemented a pipeline activity viewer as a python script (util/o3-pipeview.py)
and modified O3 code base to support an extra trace flag (O3PipeView) for
generating traces to be used as inputs by the tool.
Ali Saidi [Fri, 15 Jul 2011 16:53:35 +0000 (11:53 -0500)]
ARM: Update stats for better miscreg support for MP configurations.
Wade Walker [Fri, 15 Jul 2011 16:53:34 +0000 (11:53 -0500)]
ARM: Fix SWP/SWPB undefined instruction behavior
SWP and SWPB now throw an undefined instruction exception if
SCTLR.SW == 0. This also required the MIDR to be changed
slightly so programs can correctly determine that gem5 supports
the ARM v7 behavior of SWP/SWPB (in ARM v6, SWP/SWPB were
deprecated, but not disabled at CPU startup).
Wade Walker [Fri, 15 Jul 2011 16:53:34 +0000 (11:53 -0500)]
ARM: Add two unimplemented miscellaneous registers.
Adds MISCREG_ID_MMFR2 and removes break on access to MISCREG_CLIDR. Both
registers now return values that are consistent with current ARM
implementations.
Nilay Vaish [Tue, 12 Jul 2011 00:57:10 +0000 (19:57 -0500)]
se.py: Fixes the way ruby's options are added
Nilay Vaish [Mon, 11 Jul 2011 21:52:52 +0000 (16:52 -0500)]
X86: implements copyRegs() function
This patch implements the copyRegs() function for the x86 architecture.
The patch assumes that no side effects other than TLB invalidation need
to be considered while copying the registers. This may not hold true in
future.
Gabe Black [Mon, 11 Jul 2011 11:47:06 +0000 (04:47 -0700)]
ISA: Get rid of the unused mem_acc_type template parameter.
Ali Saidi [Sun, 10 Jul 2011 17:56:09 +0000 (12:56 -0500)]
O3: Update stats for fetch and bp changes.
Mrinmoy Ghosh [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
Branch predictor: Fixes the tournament branch predictor.
Branch predictor could not predict a branch in a nested loop because:
1. The global history was not updated after a mispredict squash.
2. The global history was updated in the fetch stage. The choice predictors
that were updated used the changed global history. This is incorrect, as
it incorporates the state of global history after the branch in
encountered. Fixed update to choice predictor using the global history
state before the branch happened.
3. The global predictor table was also updated using the global history state
before the branch happened as above.
Additionally, parameters to initialize ctr and history size were reversed.
Geoffrey Blake [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
O3: Fix up pipelining icache accesses in fetch stage to function properly
Fixed up the patch from Yasuko Watanabe that enabled pipelining of fetch accessess to
icache to work with recent changes to main repository.
Also added in ability for fetch stage to delay issuing the fault carrying
nop when a pipeline fetch causes a fault and no fetch bandwidth is available
until the next cycle.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
IO: Handle case where ISA Fake device is being used as a fake memory.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
O3: Make sure fetch doesn't go off into the weeds during speculation.
Ali Saidi [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
Config: Add support for a Self.all proxy object
Daniel Johnson [Sun, 10 Jul 2011 17:56:08 +0000 (12:56 -0500)]
ARM: Fix mp interrupt bug in GIC.
Missing "!" made multiprocessor interrupts operate incorrectly.
Korey Sewell [Fri, 8 Jul 2011 01:32:49 +0000 (21:32 -0400)]
alpha:hwrei:rollback for o3
change hwrei back to being a non-control instruction so O3-FS mode will work
add squash in inorder that will catch a hwrei (or any other genric instruction)
that isnt a control inst but changes the PC. Additional testing still needs to be done
for inorder-FS mode but this change will free O3 development back up in the interim
Brad Beckmann [Thu, 7 Jul 2011 01:45:15 +0000 (18:45 -0700)]
ruby: added generic dma machine
Brad Beckmann [Thu, 7 Jul 2011 01:44:42 +0000 (18:44 -0700)]
MOESI_hammer: Fixed uniprocessor DMA bug
Nathan Binkert [Wed, 6 Jul 2011 01:30:05 +0000 (18:30 -0700)]
slicc: add a protocol statement and an include statement
All protocols must specify their name
The include statement allows any file to include another file.
Nathan Binkert [Wed, 6 Jul 2011 01:30:05 +0000 (18:30 -0700)]
slicc: cleanup slicc code and make it less verbose
Nathan Binkert [Wed, 6 Jul 2011 01:30:04 +0000 (18:30 -0700)]
grammar: better encapsulation of a grammar and parsing
This makes it possible to use the grammar multiple times and use the multiple
instances concurrently. This makes implementing an include statement as part
of a grammar possible.
Gabe Black [Wed, 6 Jul 2011 00:46:46 +0000 (17:46 -0700)]
X86: Add a config for an FS regression on O3.
Gabe Black [Tue, 5 Jul 2011 23:52:57 +0000 (16:52 -0700)]
ISAs: Streamline some spots where Mem is used in the ISA descriptions.
Gabe Black [Tue, 5 Jul 2011 23:52:15 +0000 (16:52 -0700)]
ISA parser: Define operand types with a ctype directly.
Gabe Black [Tue, 5 Jul 2011 23:48:18 +0000 (16:48 -0700)]
ISA parser: Simplify operand type handling.
This change simplifies the code surrounding operand type handling and makes it
depend only on the ctype that goes with each operand type. Future changes will
allow defining operand types by their ctypes directly, convert the ISAs over
to that style of definition, and then remove support for the old style. These
changes are to make it easier to use non-builtin types like classes or
structures as the type for operands.
Nilay Vaish [Sun, 3 Jul 2011 16:38:25 +0000 (11:38 -0500)]
Merged with Gabe's recent changes.
Nilay Vaish [Sun, 3 Jul 2011 16:33:46 +0000 (11:33 -0500)]
Network_test: Conform it with functional access changes in Ruby
Addition of functional access support to Ruby necessitated some changes to
the way coherence protocols are written. I had forgotten to update the
Network_test protocol. This patch makes those updates.
Gabe Black [Sun, 3 Jul 2011 05:52:26 +0000 (22:52 -0700)]
tracediff: Check for --debug-flags now instead of --trace-flags.
Gabe Black [Sun, 3 Jul 2011 05:35:04 +0000 (22:35 -0700)]
ExecContext: Rename the readBytes/writeBytes functions to readMem and writeMem.
readBytes and writeBytes had the word "bytes" in their names because they
accessed blobs of bytes. This distinguished them from the read and write
functions which handled higher level data types. Because those functions don't
exist any more, this change renames readBytes and writeBytes to more general
names, readMem and writeMem, which reflect the fact that they are how you read
and write memory. This also makes their names more consistent with the
register reading/writing functions, although those are still read and set for
some reason.
Gabe Black [Sun, 3 Jul 2011 05:34:58 +0000 (22:34 -0700)]
ExecContext: Get rid of the now unused read/write templated functions.
Gabe Black [Sun, 3 Jul 2011 05:34:29 +0000 (22:34 -0700)]
ISA: Use readBytes/writeBytes for all instruction level memory operations.
Gabe Black [Sun, 3 Jul 2011 05:31:42 +0000 (22:31 -0700)]
Stats: Update stats for the x86 store fault fix.
Gabe Black [Sun, 3 Jul 2011 05:31:22 +0000 (22:31 -0700)]
X86: Fix store microops so they don't drop faults in timing mode.
If a fault was returned by the CPU when a store initiated it's write, the
store instruction would ignore the fault. This change fixes that.
Nilay Vaish [Fri, 1 Jul 2011 21:29:33 +0000 (16:29 -0500)]
Ruby: Commit files missing from previous commit
The previous commit on functional access support in Ruby did not have
some of the files required. This patch adds those files to the repository.
Brad Beckmann [Fri, 1 Jul 2011 00:57:26 +0000 (19:57 -0500)]
Regression: Updates regression outputs for Ruby memtest
This patch updates the regression outputs for Ruby memtest. This was
required because of the changes carried out by the addition of functional
access support to Ruby.
Brad Beckmann [Fri, 1 Jul 2011 00:54:02 +0000 (19:54 -0500)]
config: removed unnecessary slashes
This patch removes unnecessary slashes from a couple of python scripts.
Ruby: Add support for functional accesses
This patch rpovides functional access support in Ruby. Currently only
the M5Port of RubyPort supports functional accesses. The support for
functional through the PioPort will be added as a separate patch.
Nilay Vaish [Tue, 28 Jun 2011 23:27:38 +0000 (18:27 -0500)]
arch: print next upc correctly
The patch corrects the print statement which prints the current and
the next pc. Instead of the next upc, the next pc was being printed.
Joel Hestness [Fri, 24 Jun 2011 20:47:35 +0000 (15:47 -0500)]
Ruby: remove unused functions in CacheMemory: get/setMemoryValue
Deyaun Guo [Thu, 23 Jun 2011 03:35:21 +0000 (23:35 -0400)]
mips: fix nmsub and nmadd definitions
the -/+ signs were flipped for nmsub_s, nmsub_d, and nmadd_d
Gabe Black [Wed, 22 Jun 2011 02:28:14 +0000 (19:28 -0700)]
X86: Eliminate an unused argument for building store microops.