Clifford Wolf [Sat, 14 Feb 2015 23:20:05 +0000 (00:20 +0100)]
Smaller default parameters in $mem simlib model
Clifford Wolf [Sat, 14 Feb 2015 21:36:34 +0000 (22:36 +0100)]
Fixed "stat" handling of blackbox modules
Clifford Wolf [Sat, 14 Feb 2015 13:21:15 +0000 (14:21 +0100)]
Various fixes for memories with offsets
Clifford Wolf [Sat, 14 Feb 2015 11:55:03 +0000 (12:55 +0100)]
Added $meminit support to "memory" command
Clifford Wolf [Sat, 14 Feb 2015 10:26:20 +0000 (11:26 +0100)]
Added $meminit test case
Clifford Wolf [Sat, 14 Feb 2015 10:21:12 +0000 (11:21 +0100)]
Added "read_verilog -nomeminit" and "nomeminit" attribute
Clifford Wolf [Sat, 14 Feb 2015 09:49:30 +0000 (10:49 +0100)]
Creating $meminit cells in verilog front-end
Clifford Wolf [Sat, 14 Feb 2015 09:23:03 +0000 (10:23 +0100)]
Added $meminit cell type
Clifford Wolf [Sat, 14 Feb 2015 07:41:03 +0000 (08:41 +0100)]
Fixed handling of "//" in filenames in verilog pre-processor
Clifford Wolf [Fri, 13 Feb 2015 21:48:10 +0000 (22:48 +0100)]
Fixed "write_verilog -attr2comment" handling of "*/" in strings
Clifford Wolf [Fri, 13 Feb 2015 13:40:49 +0000 (14:40 +0100)]
hotfix in "check" command
Clifford Wolf [Fri, 13 Feb 2015 13:34:51 +0000 (14:34 +0100)]
Added "check" command
Clifford Wolf [Fri, 13 Feb 2015 11:33:12 +0000 (12:33 +0100)]
Added AstNode::simplify() recursion counter
Clifford Wolf [Fri, 13 Feb 2015 11:32:04 +0000 (12:32 +0100)]
Added EMCCFLAGS
Clifford Wolf [Thu, 12 Feb 2015 16:45:44 +0000 (17:45 +0100)]
Some test related fixes
(incl. removal of three bad test cases)
Clifford Wolf [Thu, 12 Feb 2015 15:56:01 +0000 (16:56 +0100)]
Added "proc_dlatch"
Clifford Wolf [Tue, 10 Feb 2015 19:51:37 +0000 (20:51 +0100)]
Less aggressive "share" defaults
Clifford Wolf [Tue, 10 Feb 2015 11:17:29 +0000 (12:17 +0100)]
Improved read_verilog support for empty behavioral statements
Clifford Wolf [Tue, 10 Feb 2015 07:48:55 +0000 (08:48 +0100)]
Added "scc -expect <N> -nofeedback"
Clifford Wolf [Mon, 9 Feb 2015 19:11:51 +0000 (20:11 +0100)]
Some hashlib improvements
Clifford Wolf [Mon, 9 Feb 2015 15:36:37 +0000 (16:36 +0100)]
Various changes to release checklist
Clifford Wolf [Mon, 9 Feb 2015 12:24:29 +0000 (13:24 +0100)]
Fixed creation of command reference in manual
Clifford Wolf [Mon, 9 Feb 2015 12:12:48 +0000 (13:12 +0100)]
We are now in 0.5+ development
Clifford Wolf [Mon, 9 Feb 2015 11:49:52 +0000 (12:49 +0100)]
Yosys 0.5
Clifford Wolf [Mon, 9 Feb 2015 11:48:15 +0000 (12:48 +0100)]
Bugfix in "make vcxsrc"
Clifford Wolf [Mon, 9 Feb 2015 11:05:02 +0000 (12:05 +0100)]
Updated command reference in manual
Clifford Wolf [Mon, 9 Feb 2015 11:02:21 +0000 (12:02 +0100)]
Various presentation fixes
Clifford Wolf [Sun, 8 Feb 2015 23:18:36 +0000 (00:18 +0100)]
Fixed iterator invalidation bug in "rename" command
Clifford Wolf [Sun, 8 Feb 2015 22:30:15 +0000 (23:30 +0100)]
CodingReadme update
Clifford Wolf [Sun, 8 Feb 2015 22:29:54 +0000 (23:29 +0100)]
Fixed bug in "show -format .."
Clifford Wolf [Sun, 8 Feb 2015 20:14:52 +0000 (21:14 +0100)]
Added new APIs to changelog
Clifford Wolf [Sun, 8 Feb 2015 18:06:16 +0000 (19:06 +0100)]
Fixed eval_select_op() api
Clifford Wolf [Sun, 8 Feb 2015 17:56:06 +0000 (18:56 +0100)]
Added eval_select_args() and eval_select_op()
Clifford Wolf [Sun, 8 Feb 2015 14:13:51 +0000 (15:13 +0100)]
Minor "make vgtest" changes
Clifford Wolf [Sun, 8 Feb 2015 13:23:12 +0000 (14:23 +0100)]
Various ModIndex improvements
Clifford Wolf [Sun, 8 Feb 2015 11:01:22 +0000 (12:01 +0100)]
Added Yosys 0.5 Changelog
Clifford Wolf [Sun, 8 Feb 2015 11:01:00 +0000 (12:01 +0100)]
Various updates to CodingReadme
Clifford Wolf [Sun, 8 Feb 2015 10:59:38 +0000 (11:59 +0100)]
Added equiv_add
Clifford Wolf [Sat, 7 Feb 2015 23:58:03 +0000 (00:58 +0100)]
Ignore explicit assignments to constants in HDL code
Clifford Wolf [Sat, 7 Feb 2015 23:48:23 +0000 (00:48 +0100)]
Fixed a bug with autowire bit size
(removed leftover from when we tried to auto-size the wires)
Clifford Wolf [Sat, 7 Feb 2015 23:16:59 +0000 (00:16 +0100)]
fixed typo
Clifford Wolf [Sat, 7 Feb 2015 23:14:07 +0000 (00:14 +0100)]
Added "yosys-config --build modname.so cppsources.."
Clifford Wolf [Sat, 7 Feb 2015 23:01:51 +0000 (00:01 +0100)]
Added SigSpec::has_const()
Clifford Wolf [Sat, 7 Feb 2015 23:01:31 +0000 (00:01 +0100)]
Cleanup in add_share_file make macro
Clifford Wolf [Sat, 7 Feb 2015 18:05:06 +0000 (19:05 +0100)]
Removed "make mklibyosys"
Clifford Wolf [Sat, 7 Feb 2015 18:04:06 +0000 (19:04 +0100)]
Improved building of plugins
Clifford Wolf [Sat, 7 Feb 2015 16:46:46 +0000 (17:46 +0100)]
Added "make uninstall"
Clifford Wolf [Sat, 7 Feb 2015 10:40:19 +0000 (11:40 +0100)]
Added cell->known(), cell->input(portname), cell->output(portname)
Clifford Wolf [Fri, 6 Feb 2015 09:01:22 +0000 (10:01 +0100)]
Added "select -read"
Clifford Wolf [Thu, 5 Feb 2015 22:39:26 +0000 (23:39 +0100)]
Auto-detect TCL version
Clifford Wolf [Wed, 4 Feb 2015 17:52:54 +0000 (18:52 +0100)]
Added onehot attribute
Clifford Wolf [Wed, 4 Feb 2015 15:34:06 +0000 (16:34 +0100)]
Fixed opt_clean performance bug
Clifford Wolf [Wed, 4 Feb 2015 15:33:59 +0000 (16:33 +0100)]
Disabled (unused) Xilinx tristate buffers
Clifford Wolf [Tue, 3 Feb 2015 22:45:01 +0000 (23:45 +0100)]
Using design->selected_modules() in opt_*
Clifford Wolf [Tue, 3 Feb 2015 22:11:57 +0000 (23:11 +0100)]
Skip blackbox modules in design->selected_modules()
Clifford Wolf [Tue, 3 Feb 2015 22:04:58 +0000 (23:04 +0100)]
Added "yosys -L logfile"
Clifford Wolf [Sun, 1 Feb 2015 22:07:00 +0000 (23:07 +0100)]
Merge branch 'master' of github.com:cliffordwolf/yosys
Clifford Wolf [Sun, 1 Feb 2015 22:06:44 +0000 (23:06 +0100)]
no support for 6-series xilinx devices
Clifford Wolf [Sun, 1 Feb 2015 21:55:52 +0000 (22:55 +0100)]
Merge pull request #48 from rubund/master
Fixed typos found by lintian
Clifford Wolf [Sun, 1 Feb 2015 21:41:03 +0000 (22:41 +0100)]
Improved performance in equiv_simple
Ruben Undheim [Sun, 1 Feb 2015 20:49:55 +0000 (21:49 +0100)]
Fixed typos found by lintian
Clifford Wolf [Sun, 1 Feb 2015 16:10:46 +0000 (17:10 +0100)]
Removed old XST-based xilinx examples
Clifford Wolf [Sun, 1 Feb 2015 16:09:34 +0000 (17:09 +0100)]
Added Xilinx example for Basys3 board
Clifford Wolf [Sun, 1 Feb 2015 14:43:35 +0000 (15:43 +0100)]
Added EDIF backend support for multi-bit cell ports
Clifford Wolf [Sun, 1 Feb 2015 14:42:59 +0000 (15:42 +0100)]
Added missing ports and parameters to xilinx brams
Clifford Wolf [Sun, 1 Feb 2015 12:38:46 +0000 (13:38 +0100)]
Added "make mklibyosys", some minor API changes
Clifford Wolf [Sat, 31 Jan 2015 23:57:12 +0000 (00:57 +0100)]
Minor README changes
Clifford Wolf [Sat, 31 Jan 2015 23:48:22 +0000 (00:48 +0100)]
Removed TODO list from README file
Clifford Wolf [Sat, 31 Jan 2015 23:39:59 +0000 (00:39 +0100)]
Added yosys_banner(), Updated Copyright range
Clifford Wolf [Sat, 31 Jan 2015 23:27:07 +0000 (00:27 +0100)]
Added <algorithm> include to hashlib.h
Clifford Wolf [Sat, 31 Jan 2015 23:13:19 +0000 (00:13 +0100)]
Using selections in "ls" command
Clifford Wolf [Sat, 31 Jan 2015 22:52:36 +0000 (23:52 +0100)]
Shorter "dump" options
Clifford Wolf [Sat, 31 Jan 2015 22:25:32 +0000 (23:25 +0100)]
Bugfix in opt_const $eq -> buffer code
Clifford Wolf [Sat, 31 Jan 2015 20:26:53 +0000 (21:26 +0100)]
Log msg change
Clifford Wolf [Sat, 31 Jan 2015 20:07:42 +0000 (21:07 +0100)]
Fixed equiv_make for partially undriven nets (e.g. after "clean -purge")
Clifford Wolf [Sat, 31 Jan 2015 12:58:04 +0000 (13:58 +0100)]
Added "equiv_induct -undef"
Clifford Wolf [Sat, 31 Jan 2015 12:06:41 +0000 (13:06 +0100)]
Added "equiv_simple -undef"
Clifford Wolf [Sat, 31 Jan 2015 11:08:20 +0000 (12:08 +0100)]
Added "equiv_make -blacklist <file> -encfile <file>"
Clifford Wolf [Fri, 30 Jan 2015 21:51:16 +0000 (22:51 +0100)]
Synced RTLIL::unescape_id() to log_id() behavior
Clifford Wolf [Fri, 30 Jan 2015 21:46:53 +0000 (22:46 +0100)]
Added "fsm -encfile"
Clifford Wolf [Fri, 30 Jan 2015 21:22:52 +0000 (22:22 +0100)]
More log_id() stuff
Clifford Wolf [Fri, 30 Jan 2015 21:12:26 +0000 (22:12 +0100)]
Some cleanups in log.cc
Clifford Wolf [Tue, 27 Jan 2015 23:46:00 +0000 (00:46 +0100)]
Improved an error message
Clifford Wolf [Tue, 27 Jan 2015 23:14:23 +0000 (23:14 +0000)]
Fixed bug in equiv_miter
Clifford Wolf [Tue, 27 Jan 2015 23:04:28 +0000 (23:04 +0000)]
Added "sat -show-ports"
Clifford Wolf [Tue, 27 Jan 2015 18:30:06 +0000 (19:30 +0100)]
Bugfix in resource sharing test
Clifford Wolf [Tue, 27 Jan 2015 18:22:56 +0000 (19:22 +0100)]
Updaed ABC to hg rev
61ad5f908c03
Clifford Wolf [Sun, 25 Jan 2015 21:57:09 +0000 (22:57 +0100)]
Rethrow with "catch(...) throw;"
Clifford Wolf [Sun, 25 Jan 2015 13:20:22 +0000 (14:20 +0100)]
Added equiv_remove
Clifford Wolf [Sun, 25 Jan 2015 13:00:49 +0000 (14:00 +0100)]
Added equiv_miter
Clifford Wolf [Sat, 24 Jan 2015 11:16:46 +0000 (12:16 +0100)]
Added ENABLE_NDEBUG makefile options
Clifford Wolf [Sat, 24 Jan 2015 10:49:34 +0000 (11:49 +0100)]
Added #ifdef NDEBUG for log_assert()
Clifford Wolf [Sat, 24 Jan 2015 10:03:22 +0000 (11:03 +0100)]
Fixed xilinx FDSE sim model
Clifford Wolf [Fri, 23 Jan 2015 23:16:17 +0000 (00:16 +0100)]
Various equiv_* improvements
Clifford Wolf [Fri, 23 Jan 2015 23:13:27 +0000 (00:13 +0100)]
Added dict/pool.sort()
Clifford Wolf [Thu, 22 Jan 2015 20:23:01 +0000 (21:23 +0100)]
Improvements in equiv_make, equiv_induct
Clifford Wolf [Thu, 22 Jan 2015 19:45:53 +0000 (20:45 +0100)]
Improved xdot calling
Clifford Wolf [Thu, 22 Jan 2015 13:03:18 +0000 (14:03 +0100)]
Added equiv_induct
Clifford Wolf [Thu, 22 Jan 2015 12:40:26 +0000 (13:40 +0100)]
Various equiv_simple improvements
Clifford Wolf [Thu, 22 Jan 2015 11:03:15 +0000 (12:03 +0100)]
Moved equiv stuff to passes/equiv/