scons: Get rid of a redundant "Warning:" in the SConstruct.

The "warning()" method already prints "Warning:", so putting it in the
message itself means it gets printed twice.

Change-Id: Ic157355958fdf56739f865a926ecba071bb25c5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27127
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Replace find_first_prog() with the built in Detect().

The built in environment method Detect() does the same thing, that is it
finds the first program available from a list of options.

Change-Id: I3763ae5cc9dd22ee322908c0a7a2c037dc91d5a5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27126
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Use the lsan-suppressions file when running internal commands.

These commands (like the marshal binary) might otherwise fail with
spurious leaks detected in the python library.

Change-Id: I042c2a811d465ac03f005672f328c0fb0b594494
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27125
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Add Gabe Black as the scons and util maintainer.

Change-Id: I222c25ebd7b28ddad4bb903b6fd9e15b429b1039
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27143
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>

cpu-o3: Fix unset scoreboard in vector mode switching

This is another fix for the AArch32-AArch64 interprocessing issue
introduced in
3d15150d cpu, arch, arch-arm: Wire unused VecElem code in the O3 model.

Register mapping between AArch32 and AArch64 is explicitly defined in
ARMv8 manual. This allows software to read registers right after a state
switch without writing them first, and it is indeed common for software
to save registers to memory first before using them.

In gem5's implementation of vector mode switching, however, vectors may
not be marked as ready right after a state switch. Software reads toward
vectors at this time will stall O3CPU forever. This patch fixes this by
marking all mapped vectors (or vector elements, depending on AArch32 or
AArch64) as ready right after switching vector mode.

Change-Id: I609552c543dad8da66939c0a3079d73d48e92163
Signed-off-by: Hsuan Hsu <hsuan.hsu@mediatek.com>
Signed-off-by: Howard Wang <Howard.Wang@mediatek.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26203
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: Checkpoint from MOESI_hammer Ruby hangs

Fix MOESI_hammer checkpoint hanging.
The function markRemoved() should be called before hitCallback(),
not after it. The reason is that hitCallback() checks if draining is
complete based on the value of "m_outstanding_count". And since
markRemoved() is responsible for decrementing "m_outstanding_count",
hitCallback() does not see that there are no outstanding requests.

Reported by: Timothy Hayes
Jira: https://gem5.atlassian.net/browse/GEM5-331
Change-Id: I14c34be79843b172ae994ab1792fe4ce6cf5cf6e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25683
Reviewed-by: Timothy Hayes <timothy.hayes@arm.com>
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Maintainer: Bradford Beckmann <brad.beckmann@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a file to suppress spurious lsan leaks in the python lib.

The python interpreter does some fancy things with memory which trips up
the lsan leak checker which comes along with asan. This file simply
tells lsan to ignore those leaks.

To use it when running a binary, set the LSAN_OPTIONS environment
variable to "suppressions=${PATH TO SUPPRESSIONS FILE}". To disable the
a report on the leaks that were suppressed, you should also set
"print_suppressions=0". Multiple options can be set by seperating them
with ":"s.

LSAN_OPTIONS=suppressions=util/lsan-suppressions:print_suppressions=0

Change-Id: Ie4d712c6b95f429e67361c41a9b545a8536f2511
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27124
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

scons: Use the scons environment when marshalling.

scons maintains an environment (in the shell sense) in the ENV
construction variable for use when running external programs. When we
run the "marshal" program which gathers up python objects to embed in
the gem5 binary, it's run by subprocess instead of through scons, and it
uses its own environment inherited from the host system.

Instead, this change makes the subprocess function use the scons
environment when calling "marshal". This ensures the environment is
consistent between this command and other commands scons runs.

This is usually not very important, but some tools like asan take
options set through the environment, and they may need to be adjusted
sometimes.

Change-Id: I671b447657ed8fad45fac7393cc1c09073bf3d3a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27123
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,misc: Updated presubmit YAML to use main.py '-t' flag

This minor change reduces the presubmit build time by about 10 to 15
minutes.

Change-Id: I3a87d1a720b17fd22a9dbdbeebfb32e4be178c56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27064
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

tests: Migrated 10.linux-boot scons-based test to testlib

This test has purposely been designed to be easily extendible for future
x86 boot tests. Right now, it only runs two basic Ubuntu boot test
setups.

Change-Id: I81385b5dfc0764af2ec02999eb26e523bd09a595
Issue-on: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26324
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Don't use args and kwargs on attachIO

This is matching the attachOnChipIO style, and fixing the error of the
dma_ports kwarg being forwarded to the _attach_mem

Change-Id: Ib3ecf2fc18c488d938bbbf63eab3d7693cdb7d06
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27086
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>

arm: Return whether a semihosting call was recognized/handled.

Otherwise there's no way to determine whether the return value was from
the semihosting mechanism itself, or from one of the calls. There would
also be no way to determine whether a call had actually happened.

Change-Id: Ie2da812172fe2f9c1e2b5be95561863bd12920b1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25949
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

arch-riscv: print information about faults.

Change-Id: Ic69b788d508bab1044b693860c7d942963bed3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25646
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

arch-riscv: added support for pseudo instructions.

Change-Id: I4f73f8fcf62def8815e82555fc2a67f89efc09d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25645
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,sim: Return whether or not a pseudo inst was recognized.

Otherwise there's no way to distinguish whether return values are from
the calls themselves, including what they mean in the context (success
or failure?) or the pseudo inst dispatch function itself.

Change-Id: I3e71c277f175c69af0d1adeb3299d88d095dfa84
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25948
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alexandru Duțu <alexandru.dutu@amd.com>

sim-se: Add special paths for MPI, libnuma, ROCm support

Add new pseudo files which are read by various runtime libraries
including MPI, libnuma, and ROCm. New paths include /proc/self/maps,
/dev/urandom, and /sys/devices/system/cpu/online.

Change-Id: I00a82788cff9d6f4f16fc56230b18be9b76c4015
Signed-off-by: Brandon Potter <Brandon.Potter@amd.com>
Signed-off-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25367
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arm: Optionally enable gem5 extended semihosting calls.

ARM's semihosting interface defines call numbers up to 0xff to be
for standardized use, and says that custom calls should go above this
number.

This new mechanism will let the caller decide whether it wants to
enable these extended calls, or if they should be ignored and only
standard calls should be recognized.

Change-Id: I34b01a4439c8a88242971ac486e34d810b054baf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25947
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Update mmap, munmap, mremap to use MemState

This updates the syscalls for mmap, munmap, and mremap. The mmap
changes now create a virtual memory area through the MemState class
to allow for lazy allocation of mmapped regions. This provides
substantial performance boost for sparse usage of mmaps. The munmap
syscall is added to reclaim the virtual memory area reserved for the
mmapped region. The mremap syscall moves or resizes an mmapped region
and updates the corresponding virtual memory area region to keep the
page tables in sync.

Change-Id: Ide158e69cdff19bc81157e3e9826bcabc2a51140
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26863
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

sim-se: Switch to new MemState API

Switch over to the new MemState API by specifying memory regions for
stack in each ISA, changing brkFunc to use MemState for heap memory,
and calling the MemState fixup in fixupStackFault (renamed to just
fixupFault).

Change-Id: Ie3559a68ce476daedf1a3f28b168a8fbc7face5e
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25366
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sim-se: Extend MemState API to use VMAs

Extend the MemState API to handle tracking dynamically sized memory
regions of a Process class which may be added, moved, removed, or
change in size during the course of simulation. This utilizes the
virtual memory areas (VMA) class to track individual regions and
provides a fixup method to handle physical page allocation in case of
a page fault. This allows for lazy allocation of the stack, heap, and
mmap regions of memory.

Change-Id: I3ef10657e5f8e8f0e328bdf0aa15a27b1dde39bf
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25483
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: Use ArmFsWorkload for Arm baremetal

Change-Id: Ie6bfdd9b30438bc6eaf22bc79dcc1690ffa039be
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26991
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

cpu: IntrControl, clear all and check helpers

This patch extends the IntrControl to provided additional member
functions for (1) clearing all pending interrupts in a PE and (2)
checking for any pending interrupt in a PE. These are intended to
be used from interrupt management related peripherals.

Change-Id: I06b553872ed469e7449b872a0716865773ace154
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26809
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: Initialize atags_addr in baremetal.py

Change-Id: Iec797d4be607526d68a2813e188a32759418dbcc
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27023
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: Enable Semihosting for baremetal.py

This is enabled via the --semihosting option

Change-Id: If6961cba8ec4a3aa22e788db6fe0ae54e169bb9c
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26993
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

configs: Make --disk-image optional in baremetal.py

Since the script could be used to run baremetal applications, we don't
have to enforce the presence of a disk image

Change-Id: I511515361cfd7a2e06ede0df3ddcc595de15f38b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26992
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

power: Hook up the readlink system call.

Change-Id: I28dcbd6fb3c54479eefea26d810d10c00195cc08
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26830
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

power: Add the AT_RANDOM aux vector to the initial stack.

This is blindly used by at least modern glibc-s

Change-Id: I8ee7872c8072ee8aa1b3718e988679968ac172d0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26829
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Make the semihosting implementation use GuestABI.

Remove the ability to not have an implementation for a semihosting call
in 32 or 64 bit mode since that was not actually being used. It can be
reintroduced if needed in the future.

Turn the physProxy helper function into a static function which
maintains a single secure port proxy. That makes the proxy available
outside of the ArmSemihosting class itself.

Change-Id: Ie99e7d79c08c039384250fab0c98117554c93128
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25946
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch-arm: Make load_addr_mask=0 for ArmFsLinux only

This is restoring the situaton pre:

https://gem5-review.googlesource.com/c/public/gem5/+/26466

Where load_addr_mask was set to 0 (forcing the loader to discard
the kernel entry point) for LinuxArmSystem only.

With this patch the masking is done for ArmFsLinux workloads
only and it is using the default 0xffffffffffffffff (no masking)
for common ArmFsWorkload

Change-Id: I68970edcac61ad0de79433ffd84fef580a94b480
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/27024
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

arch-arm: Fix aapcs32/aapcs64 compilation issues

Some compilers won't build ARM due to how guest ABI
has been implemented.

The error is: "left shift count >= width of type"
[-Werror=shift-count-overflow]

The error is triggered when there is a left shift > the variable size
(in bits); this leads to undefined behaviour.

This is a compile time vs run time problem; the code is technically
fine, but the compiler is not able to understand this.

For example in aapcs64:

struct Argument<Aapcs64, Integer, typename std::enable_if<
 std::is_integral<Integer>::value>::type> : public Aapcs64ArgumentBase
{
    [...]
    if (sizeof(Integer) == 16 && state.ngrn + 1 <= state.MAX_GRN) {
        Integer low = tc->readIntReg(state.ngrn++);
        Integer high = tc->readIntReg(state.ngrn++);
        high = high << 64;
        return high | low;
    }
}

Even if the sizeof operator will be evaluated at compile time,
the block will be executed at runtime: the block will still be part of
the code if Integer = uint32_t.
The compiler will then throw an error because we are left shifting an
uint32_t by 64 bits.

Error arising on:
Compiler: gcc/5.4.0
Distro: Ubuntu 16.04 LTS

Change-Id: Iaafe030b7262c5fb162afe7118ae592a1a759a58
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26990
Reviewed-by: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Remove a check that the memory size is a multiple of the page size.

There are a few problems with this check.

1. Many ISAs support multiple page sizes.
2. Memories (particularly small ROMs) may not actually be in multiples
   of the page size.
3. In a heterogenous environment, there won't be a single page size even
   if each ISA picks a canonical page size.
4. Other than catching some egregious configuration mistakes, there's
   nothing functionally wrong/different about a memory that isn't evenly
   coverable in pages, especially in systems or configurations that
   don't even use paging.

Change-Id: I3cd241657318d2e3fd5a1226cb54fdebbf172788
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26423
Maintainer: Gabe Black <gabeblack@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

mips: Add the AT_RANDOM aux vector to the initial stack.

This is blindly used by at least modern glibc-s

Change-Id: I8fb904d487d0cb5f7747d063a6ed84894ee6b905
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26828
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Hook up fstat64 for SPARC64.

This seems to be used by a modern gcc toolchain.

Change-Id: Ia776f4d8b3f290336047d3a7e57f1bffac1feaa2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26827
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Add a definition of tgt_stat64 for SPARC64.

Change-Id: Ided4710d47436fbf8e34be2427dc7ed092a69f56
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26826
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

sparc: Hook up but not implement the get/set context traps.

gem5 will panic if it encounters a trap it doesn't know what to do with.
Newer versions of glibc, gcc, etc., use the getcontext trap in setjmp
during startup.

This change hooks up a function for both the getcontext and setcontext
traps. The getcontext one just warns that it isn't implemented. If the
context it creates is never used (likely) then that should be fine for
now. If we ever try to actually use a context with setcontext, then
something bad will almost certainly happen if it's not implemented, and
we panic.

Change-Id: Id6797ac6955249d299e975c9c30360920d380e60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26825
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Add flash1 memory to VExpress_GEM5 platform

Change-Id: I013241ac99fe42cdef437a396732447726beedd0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26833
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

dev-arm: Instantiate FVPBasePwrCtrl in VExpress_GEM5

Change-Id: I9390570ce459adece930dbbfad050bfb1100dfd2
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26832
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add some settings files for build_cross_gcc.

These files have settings for 32 and 64 bit ARM, MIPS, POWER, RISCV, and
SPARC. When used with the versions of toolchain components below, they
all generate working hello world binaries.

binutils-2.34
gcc-9.3.0
glibc-2.31
linux-5.5.9
gdb-9.1

The script was unable to install the c++ standard headers (step 8)
because a constant was not found when building one of the sanitizers. I
don't know exactly why this happens, but I suspect it's independent of
the build process.

Change-Id: I9f0068b77edf338ed63b95f007454c07651aa42a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26764
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

tests,learning-gem5: Moved MIPS ISA test from part 1 to long

The learning gem5 part 1 tests were the only "quick" tests requiring the
MIPS ISA to be compilated. This is a big cost for two very simple tests.
The MIPS ISA tests for learning gem5 part 1 have been moved to the
"long" tests.

Change-Id: I694541b4c7ea84e91262f29c67fb5ec2bbbc6fec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26844
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for clang

This will create a Docker image with all gem5 dependencies, allowing for
a specific clang version to be specified via `--build args version=X`.
I.e., to create an image with clang 6,
`docker build util/dockerfiles/clang-version --build-arg version=6`

Issue-on: https://gem5.atlassian.net/browse/GEM5-235
Change-Id: I7d12acd265d7aef2a9e90f348f4214231effe509
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26484
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for GCC of different versions

This will create a Docker image with all gem5 dependencies, allowing for
a specfic GCC version to be specified via `--build-arg version=X`. I.e.,
to create an image with GCC 8,
`docker build util/dockerfiles/gcc-version --build-arg version=8`.

Issue-on: https://gem5.atlassian.net/browse/GEM5-228
Change-Id: I927eb90b6446059cce70e3b722a8fc3985068285
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26507
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for minimum gem5 dependencies

This will create a Docker image with the minimum dependencies to build
and run gem5.

Issue-on: https://gem5.atlassian.net/browse/GEM5-236
Change-Id: Ia0ed1a84718dcd15895badf8618a661277f8349c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26583
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

misc: Added Dockerfile for Python3

This will create a docker image with all gem5 dependencies in a Python3
virtual environment.

Issue-on: https://gem5.atlassian.net/browse/GEM5-392
Change-Id: Id23777fb698977e92437c546f1fdf0ea0faa8708
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26506
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-ruby: MESI_Three_Level discriminate L0 invalidation reason

The L0 cache can now know whether a line is being invalidated
due to this cache/core's own requirements, e.g. a load from the core
causing a line eviction, or due to another cache/core's requirements,
e.g. a remote cache requesting a present line in exclusive state.

Change-Id: If57bfb92b6c8f575ca47d984606be7c859dcff9a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24259
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-ruby: MESI_Three_Level fix L1 MRU absence

The L1 cache is updating the MRU tag after acessing a cache line.
This patch updates MRU for cases when the L0 cache loads/stores
a line from/to the L1 cache.

Change-Id: I1f0ccef26b3c7614dc865a38c39145840dabfd01
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24258
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

mem-ruby: MESI_Three_Level fix L1 in_port ranks

The L1 cache contains three in_port networks with ranks 0-2-3.
This is a benign typo, however, this patch corrects the ranks to
0-1-2 for clarity.

Change-Id: Id9bb63dae310af0f962345a114b0ccb8bddcf696
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24257
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>

arch,sim: Merge Process::syscall and Process::getDesc.

When handling a system call, external code would call Process::syscall
which would extract the syscall number, that would call the base
class' doSyscall method, that would call into the subclass' getDesc
to get the appropriate descriptor, and then doSyscall would check
that a syscall was found and call into it.

Instead, we can just make the SyscallDescTable optionally check for
missing syscalls (in case we want to check multiple tables), and
make syscall look up the appropriate descriptor and call it. The base
implementation of syscall would then do the only bit of doSyscall that
is no longer being handled, incrementing the numSyscalls stat.

Change-Id: If102c156830ed2997d177dc6937cc85dddadf3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24119
Tested-by: kokoro <noreply+kokoro@google.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Maintainer: Gabe Black <gabeblack@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arch,sim: Drop the syscall number from the syscall func signature.

This value is almost never used, and is now part of the SyscallDesc.

Change-Id: Ia4ffc19774bb2eac8f29134e3765c06a264407b6
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24118
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,sim: Create a common structure to hold syscall tables.

Also add the syscall number into the SyscallDesc class.

The common table structure is basically just a map that extracts its
key value from the SyscallDesc class using a new num() accessor. By
using a map instead of an array (like RISCV was already doing), it's
easy to support gaps of arbitrary size and non-zero offsets of groups
of system calls without lots of filler or additional logic. This
simplified the ARM system call tables in particular which had a lot
of filler entries.

Also, both the 32 and 64 bit ARM syscall tables had entries for a
syscall at 123456 which was the "Angel SWI system call". This value
is actually the immediate constant passed to the SWI system call
instruction and is not interpreted as the system call number in linux.
This constant can be intercepted by hardware or a simulator to, for
instance, implement ARM semihosting.

Also, that constant in combination with the SWI instruction is only
used for semihosting in 32 bit ARM mode, not in 64 bit mode or in
thumb.

Since checking for that system call number was very likely a mistake
from misinterpreting how the semihosting calls work, this change
drops those checks.

Change-Id: I9b2a902d7326791449cf0e1b98e932dcadba54f7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24117
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

sim: Get rid of the Arguments class.

This class read arguments using the arch specific getArgument function
and then presented the arguments as an array. The problem with that
approach is that it's not possible to tell where different arguments
are without knowing the types of previous arguments, and not all
arguments can be simply represented as a native sized integer.

This class has been phased out and is no longer needed.

Change-Id: Ibb4c529fe8c51fd0ae15ed3b6ea30543ad9c23e0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24115
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>

mem-ruby: MESI_Three_level HTML reference generation fix

The SLICC HTML generator does not work without the 'desc' property of
the STATES and EVENTS found in the protocol state machine source files.
This adds the 'desc' property in MESI_Three_Level to declarations where
it was missing and cleans up the text of some existing ones.

Issue-on: https://gem5.atlassian.net/browse/GEM5-357

Change-Id: I2d0f8e11889554063fed798e724217963d4a74de
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24256
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>

sparc: Add the AT_RANDOM aux vector to the initial stack.

This is blindly used by at least modern glibc-s

Change-Id: I175ce5f1495e367badf0fab32f5837e3cdfa955a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26824
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

util: Add the ability to build a cross GDB to build_cross_gcc.py.

This is a very simple extension to what's already there.

Change-Id: I07e3711244e0de96b215f16ec05c660b19e462b5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26765
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>

base: Convert the annotation methods to take actual arguments.

Feed the arguments in from the decoder.

Change-Id: Ie2dcd09320a5de02bb91b8743fc643c446e506e7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24114
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arm,kern: Use GuestABI to call printk from the kernel.

Change-Id: I07b0f1c01f5ec8d6761903fa4aa15b9e8ae35069
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24113
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

arm: Use a non-template indexed version of laneView in aapcs32.

The lane number is constant over its lifetime, but is computed with a
variable i which is not a compile time constant. It therefore can't be
used as a template parameter, and should be marked as const and not
constexpr.

Change-Id: Ie0b950311495831d5224a8fb397cf42d5cf5f25b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26834
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

util: Add a script to help build cross compilers.

Cross compilers are very useful when working with gem5. The how-to this
script is based on assumed the compiler was targeting linux, so there
isn't any support for compilers targeting other or no OS. That might be
possible to add in the future.

Change-Id: I2cb30ecbdd4c6292146ea64940348c24385046f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26763
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Add --bin-path option to insttest regressions

Change-Id: I229f37782b1c3650dc71ee481823b41f6f67e590
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26483
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

arch-arm: Fix ArmSystem::_resetAddr evalutation

With:

https://gem5-review.googlesource.com/c/public/gem5/+/26466

The ArmSystem reset address (_resetAddr) is always forced by the
workload:

 _resetAddr = workload->entry

So there is no possibility to manually specify a reset address.

This was not the case before:
The resetAddr was forced only if auto_reset_addr was true or if there
was an associated bootloader to the kernel image. In that case even if
auto_reset_addr was false, the reset address was determined by the
bootloader entry.
This was also not ideal (but it was working)

This patch is cleaning all of this:

If you want to have automatic detection (recommended), you would need to
set auto_reset_addr (now turned to true by default).  This will allow to
keep most fs script untouched.  If you don't want to use automatic
detection, set auto_reset_addr to False and provide your own reset
address.

Change-Id: I5d7a55fd9060b9973c7d5b5542bd199950e1073e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26723
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

dev-arm: SMMUv3, single interconnect attachment

The attachment (port binding) of the SMMUv3 master and control
ports is independent of the connection of device masters to it.

This behaviour is now moved from SMMUv3::connect to
RealView::attachSmmu, as it is a responsibility of the Platform
designer.

This fixes crashes when connecting multiple device masters.

Change-Id: If1e8f55d51876fe761f881e3044ffec637c21b09
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26923
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: Gem5 Cloud Project GCB service account <345032938727@cloudbuild.gserviceaccount.com>

sim-se: Implement Virtual Memory Area API

Virtual memory areas are used to track regions of memory which may
change over the course of execution, such as heap, stack, and mmap. It
is a high-level mimicry of Linux' memory management. VMAs are intended
to be used to support lazy allocation of physical pages to valid VMAs
as the virtual addresses are touched. Lazy allocation increases speed
of simulation for SE mode processes which, for example, mmap large
files.

The VMAs can also be queried to generate a map of the process' memory
which is used in some libraries such as pthreads.

This changeset only adds APIs for virtual memory areas. These are used
in a subsequent changeset.

Change-Id: Ibbdce5be79a95e3231d2e1c9ee8f397b4503f0fb
Signed-off-by: Brandon Potter <Brandon.Potter@amd.com>
Signed-off-by: Michael LeBeane <Michael.Lebeane@amd.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25365
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Add a Request::Flags parameter to the translating port proxies.

These flags will be given to the Request object which is used to do the
translation.

Change-Id: I21755f5f9369311e2f2d5be73ebd4f5865f73265
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26623
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,base,cpu,dev,kern,mem,sim: Drop FS from FSTranslatingPortProxy.

This translating proxy can be used in FS, or in SE with a failure
handing case in place.

Change-Id: I2e6421f52529fa833e42f8d3e64d4341c282634f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26551
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

arch,cpu,mem,sim: Reimplement the SE translating proxy using the FS one.

The only functional difference between them was that the SE one might
have optionally fixed up missing translations for demand paging.

This lets us get rid of some code recreating the proxy ports in
setProcessPtr since the SE translating port no longer keeps a copy of
the process object pointer.

Change-Id: Id97df1874f1de138ffd4f2dbb5846dda79d9e4ac
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26550
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>

sparc: Make translateFunctional ignore alignment and use the page tables.

translateFunctional might be used with unaligned addresses which should
be allowed in that context. Also, in SE mode, if the translation isn't
in the TLB itself, then it should be looked up in the SE mode fake page
tables and not in a page table resident in memory.

Change-Id: Ibb39685cfdcd4eb6cb8a0486a1de014a4e452518
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26831
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch: Eliminate vtophys and its switching header file.

This function is no longer used anywhere in gem5.

Small helper functions which had been put alongside vtophys on ARM and
RISCV were also moved into src/arch/arm/remote_gdb.cc and
src/arch/power/pagetable.hh, the only places they were used.

Change-Id: Iba72f6c4b797a35a785a5bb781d602c943541fa7
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26234
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem: Make the FSTranslatingPortProxy stop using vtophys.

That was the only place vtophys was still being used. Instead, use the
data TLB to translate functional, and if that fails try the the
instruction TLB.

Change-Id: Ie5e1e1b5d470f010e25482d785f111dc4292db60
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26233
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arm: Demote PCEvent subclass pointers to PCEvent pointers.

Nothing is actually accessed through these pointers. This simplifies
their declration, and gives more flexibility when setting up those
events.

Change-Id: If857de5c8df37b6ead7eae53e3c0c6c3103938c0
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24112
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>

riscv: Implement translateFunctional.

Change-Id: Ibe8adea8f66c7de22ee2ab0da54e866cd05fc257
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26547
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

arch,kern: Rename some function events to have better names.

Rename many of the Event classes to have more succinct or
consistent names, and fix various style issues.

Change-Id: Ib322da31d81e7a245a00d21786c2aa417c9f2cde
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26703
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Use relative path for python3 compliance

Change-Id: Ie18c52982e2083d0fc2723147f2493b39bcb3786
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26743
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Do not treat addresses < 10 specially

The RSP stub (base/remote_gdb.cc) treats virtual addresses below 0x000A as
meaning "the address used in the previous m-packet".  This leads to nasty
surprises, and is not justified by neither the RSP protocol documentation
nor other existing RSP implementations.

Jira Issue: https://gem5.atlassian.net/browse/GEM5-407

Change-Id: I5fccc10a58d9af856eeee6d45418905c0f47ffab
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26605
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Gabe Black <gabeblack@google.com>

tests: Increased Kokoro's timeout to 5 hours

Change-Id: Ice9fc5f17dfa06f61bc5583ecca15c54742bc254
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26843
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Removed old scon-based 40.m5threads-test-atomic tests

These have been migrated to be run via testlib.

Change-Id: I186e4048096f718c0de378033924cd23328168d7
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25843
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 40.m5threads-test-atomic scons tests to testlib

At present, the 40.m5threads-test-atomic tests fail as the SPARC binary
(generated from `tests/test-progs/pthread/src/test_atomic.cpp`) is not
present. This has been noted in:
https://gem5.atlassian.net/browse/GEM5-368

Change-Id: I7865826388be46cec06a201712081146a58518f2
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25824
Reviewed-by: Ayaz Akram <yazakram@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

tests,arch-alpha: Removing ALPHA ISA from testlib config

Change-Id: Icded5f4aec7bc212a818a97c4de5d7b8f8757121
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26823
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

kern,arch: Refactor SkipFuncEvent to not use skipFunction.

Replace it with a new virtual function.

Change-Id: I9d516d21ab3b1d1d70ea1297f984f868d3e7c3fb
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24111
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Implement translateFunctional.

This function is based off of vtophys in the full system case, and off
of the page table fill mechanism used in SE mode. It ignores what's
already in the TLB, and also ignores protection mechanisms.

This may need to be reworked in the future if, for instance, pages
still resident in the TLB but not in the page tables need to be
considered, but it should work at least for the time being.

Change-Id: If21701ca36a30805f4199312933a8afc91f20501
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26405
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Gabe Black <gabeblack@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>

tests: Migrated 80.dram scons-based tests to testlib framework

"configs/dram/low_power_sweep.py" has been modified to keep the
generated "lowp_sweep.cfg" file in "configs/dram". This generated file
is now ignored by git.

Change-Id: I700d04944fee58f8a506c71fd474b84024ec4374
Jira: https://gem5.atlassian.net/browse/GEM5-109
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25923
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in CrossbarSwitch

There is no need to dynamically allocate these variables.

Change-Id: I6efeaffe75f2b4ba706c26d2a12c42c07dc7c7ee
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24983
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use smart pointers in Router's members

Use smart pointers for the pointers managed by Router, and do
static allocation when possible.

Change-Id: I5fad8b2d17ac7950d478d37000ac80a4d2f68b15
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24248
Reviewed-by: Bobby R. Bruce <bbruce@ucdavis.edu>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in Switch

Make pointers non pointers when possible.

Change-Id: I272387c2ac1fd77deef06feb637127e232910e30
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24250
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in NetworkLink

Use static allocation to manage NetworkLink's pointers.

Change-Id: I3ab22b1f912f0119448f9013fd0dfff9bf5a6999
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24252
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in NetworkInterface

Use static allocation for the pointers managed by NetworkInterface.

Change-Id: Ib97d95165337659f92cb8a078020692baae5b5ca
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24247
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-by: Srikant Bharadwaj <srikant.bharadwaj@amd.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in InputUnit

Use static allocation for the pointers managed by InputUnit.

Change-Id: I3eab42c6c08b1a519b9b55de26e820bad2ef03c4
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24245
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in OutputUnit

Use static allocation for the pointers created by OutputUnit.

Change-Id: Ica4fd5d4994078764769702311520c9daf8dba72
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24243
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Use static allocation in VirtualChannel

The input buffer does not need to be dynamically allocated.

Change-Id: Ice64f40d2a7e16af325ddb6803e34b3eed2e99db
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24253
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Remove delete of param pointers of SimpleNetwork

All over gem5 the params pointers are not deleted within the classes
that they were created for. Although this is a potential memory leak
as of now, it is probably safer to follow general convention so that
it can be fixed at once in the future.

Change-Id: If96f04058d51513fa8763610880e5524785ee9cf
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24249
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

mem-garnet: Remove delete of param pointers of GarnetNetwork

All over gem5 the params pointers are not deleted within the classes
that they were created for. Although this is a potential memory leak
as of now, it is probably safer to follow general convention so that
it can be fixed at once in the future.

Change-Id: I74b662a8e635cdfb4dc1eae732dd114659fab2e9
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/24246
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

base: Add static assert to trie

Trie is based on the condition that they key is an integral. As so,
add a static_assert to guarantee that. Also, added some general info
about tries to the class.

Change-Id: Idc18f6a685db8047cd44b791f427666d3dd2d187
Signed-off-by: Daniel R. Carvalho <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26784
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

x86: Hook up pread64 in 32/64 bit linux, and pwrite64 in 32 bit.

My new computer has a dynamic linker which seems to use the pread64
system call, and since that gets pulled in when running tests, that
needs to be implemented for tests to pass on that machine, making it
possible to detect problems the failure might ohterwise mask.

This is only really necessary for 64 bit linux, but while I'm here I
hooked it up for 32 bit linux as well. I also added pwrite64 for 32 bit
linux since that was only enabled for 64 bit.

Change-Id: I8d2061d30e98a1581c5e30b522b6ba12aea20ecd
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26604
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

sim: Provide an implementation for the pread64 system call.

This implementation is very similar to the pwrite64 system call, just
with data going the other direction as you'd expect.

Change-Id: I4f8ec9d83bf2339f9c84e31f25309c58e6157304
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26603
Reviewed-by: Matthew Poremba <matthew.poremba@amd.com>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>

configs: fix forwarding of --bootloader to fs.py

Since I02919207d6f175854017ae7b603d811da63d618e the fs.py --bootloader
option can be used to select a bootloader explicitly.

Ia3d863db276a023b6a2c7ee7a656d8142ff75589 forgot to pass that parameter
likely due to a rebase issue and it gets searched in M5_PATH.

Change-Id: Ic4cf3ccf041e1c34eac7753424fe842bd34a77f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26724
Reviewed-by: Gabe Black <gabeblack@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

power: Fix regStats for PowerModel and PowerModelState

Every Stats::Group need to call the parent regStats to
make sure that the base Stats::Group::regStats() gets
called

JIRA: https://gem5.atlassian.net/projects/GEM5/issues/GEM5-319

Change-Id: I931941d8ec5f375f7e51e719d43ae31af095f661
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26643
Tested-by: kokoro <noreply+kokoro@google.com>

arch-x86: Add Python 3 workarounds for long

Python 3 doesn't have a separate long type. Make long an alias for int
where needed to maintain compatibility.

This is aligning with https://gem5-review.googlesource.com/c/15988

Change-Id: I20e52d7f796d143534fa7dabeb6ff0ae8b62fd2b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26257
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>

arch-x86: Fix imports for Python 3 compatibility

Change-Id: I7e486a6f3d38af54ac1eff431ca40a5af29e3ca7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26256
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

tests: Use relative path for python3 compliance

Change-Id: I9a45a7800f1b69037781374df86e29bd5eb0f014
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26255
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: list.sort() sorting by key only in python3

list.sort() no longer accept a comparison function. Use the key argument
instead for key based sorting.

Change-Id: I2af2732628721faee3870af0d53c1267839896da
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26254
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

dev-arm: Fix VExpressFastmodel.py indentation

Convert TAB with four spaces

Change-Id: I7472a01423953c68aed60b37f56fe86eca249fac
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26253
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>

arch: Convert exec keyword to exec() function

The function syntax was also accepted in 2.x

Change-Id: I3d9bef3ddcd5e98ff589796d21dbfeb9796bff1d
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/26252
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <jason@lowepower.com>
Maintainer: Jason Lowe-Power <jason@lowepower.com>